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18#include <linux/clk.h>
19#include <linux/delay.h>
20#include <linux/dma-mapping.h>
21#include <linux/dmapool.h>
22#include <linux/i2c.h>
23#include <linux/interrupt.h>
24#include <linux/module.h>
25#include <linux/of.h>
26#include <linux/platform_device.h>
27#include <linux/prefetch.h>
28#include <linux/proc_fs.h>
29#include <linux/slab.h>
30#include <linux/usb/ch9.h>
31#include <linux/usb/gadget.h>
32#include <linux/usb/isp1301.h>
33
34#ifdef CONFIG_USB_GADGET_DEBUG_FILES
35#include <linux/debugfs.h>
36#include <linux/seq_file.h>
37#endif
38
39
40
41
42typedef void (*usc_chg_event)(int);
43struct lpc32xx_usbd_cfg {
44 int vbus_drv_pol;
45 usc_chg_event conn_chgb;
46 usc_chg_event susp_chgb;
47 usc_chg_event rmwk_chgb;
48};
49
50
51
52
53
54
55#define NUM_ENDPOINTS 16
56
57
58
59
60#define IRQ_USB_LP 0
61#define IRQ_USB_HP 1
62#define IRQ_USB_DEVDMA 2
63#define IRQ_USB_ATX 3
64
65#define EP_OUT 0
66#define EP_IN 1
67
68
69#define EP_MASK_SEL(ep, dir) (1 << (((ep) * 2) + dir))
70
71#define EP_INT_TYPE 0
72#define EP_ISO_TYPE 1
73#define EP_BLK_TYPE 2
74#define EP_CTL_TYPE 3
75
76
77#define WAIT_FOR_SETUP 0
78#define DATA_IN 1
79#define DATA_OUT 2
80
81
82
83
84struct lpc32xx_usbd_dd_gad {
85 u32 dd_next_phy;
86 u32 dd_setup;
87 u32 dd_buffer_addr;
88 u32 dd_status;
89 u32 dd_iso_ps_mem_addr;
90 u32 this_dma;
91 u32 iso_status[6];
92 u32 dd_next_v;
93};
94
95
96
97
98struct lpc32xx_ep {
99 struct usb_ep ep;
100 struct list_head queue;
101 struct lpc32xx_udc *udc;
102
103 u32 hwep_num_base;
104 u32 hwep_num;
105 u32 maxpacket;
106 u32 lep;
107
108 bool is_in;
109 bool req_pending;
110 u32 eptype;
111
112 u32 totalints;
113
114 bool wedge;
115};
116
117enum atx_type {
118 ISP1301,
119 STOTG04,
120};
121
122
123
124
125struct lpc32xx_udc {
126 struct usb_gadget gadget;
127 struct usb_gadget_driver *driver;
128 struct platform_device *pdev;
129 struct device *dev;
130 struct dentry *pde;
131 spinlock_t lock;
132 struct i2c_client *isp1301_i2c_client;
133
134
135 struct lpc32xx_usbd_cfg *board;
136 void __iomem *udp_baseaddr;
137 int udp_irq[4];
138 struct clk *usb_slv_clk;
139
140
141 u32 *udca_v_base;
142 u32 udca_p_base;
143 struct dma_pool *dd_cache;
144
145
146 u32 enabled_devints;
147 u32 enabled_hwepints;
148 u32 dev_status;
149 u32 realized_eps;
150
151
152 u8 vbus;
153 u8 last_vbus;
154 int pullup;
155 int poweron;
156 enum atx_type atx;
157
158
159 struct work_struct pullup_job;
160 struct work_struct power_job;
161
162
163 struct lpc32xx_ep ep[NUM_ENDPOINTS];
164 bool enabled;
165 bool clocked;
166 bool suspended;
167 int ep0state;
168 atomic_t enabled_ep_cnt;
169 wait_queue_head_t ep_disable_wait_queue;
170};
171
172
173
174
175struct lpc32xx_request {
176 struct usb_request req;
177 struct list_head queue;
178 struct lpc32xx_usbd_dd_gad *dd_desc_ptr;
179 bool mapped;
180 bool send_zlp;
181};
182
183static inline struct lpc32xx_udc *to_udc(struct usb_gadget *g)
184{
185 return container_of(g, struct lpc32xx_udc, gadget);
186}
187
188#define ep_dbg(epp, fmt, arg...) \
189 dev_dbg(epp->udc->dev, "%s: " fmt, __func__, ## arg)
190#define ep_err(epp, fmt, arg...) \
191 dev_err(epp->udc->dev, "%s: " fmt, __func__, ## arg)
192#define ep_info(epp, fmt, arg...) \
193 dev_info(epp->udc->dev, "%s: " fmt, __func__, ## arg)
194#define ep_warn(epp, fmt, arg...) \
195 dev_warn(epp->udc->dev, "%s:" fmt, __func__, ## arg)
196
197#define UDCA_BUFF_SIZE (128)
198
199
200
201
202
203#define USBD_DEVINTST(x) ((x) + 0x200)
204#define USBD_DEVINTEN(x) ((x) + 0x204)
205#define USBD_DEVINTCLR(x) ((x) + 0x208)
206#define USBD_DEVINTSET(x) ((x) + 0x20C)
207#define USBD_CMDCODE(x) ((x) + 0x210)
208#define USBD_CMDDATA(x) ((x) + 0x214)
209#define USBD_RXDATA(x) ((x) + 0x218)
210#define USBD_TXDATA(x) ((x) + 0x21C)
211#define USBD_RXPLEN(x) ((x) + 0x220)
212#define USBD_TXPLEN(x) ((x) + 0x224)
213#define USBD_CTRL(x) ((x) + 0x228)
214#define USBD_DEVINTPRI(x) ((x) + 0x22C)
215#define USBD_EPINTST(x) ((x) + 0x230)
216#define USBD_EPINTEN(x) ((x) + 0x234)
217#define USBD_EPINTCLR(x) ((x) + 0x238)
218#define USBD_EPINTSET(x) ((x) + 0x23C)
219#define USBD_EPINTPRI(x) ((x) + 0x240)
220#define USBD_REEP(x) ((x) + 0x244)
221#define USBD_EPIND(x) ((x) + 0x248)
222#define USBD_EPMAXPSIZE(x) ((x) + 0x24C)
223
224
225
226#define USBD_DMARST(x) ((x) + 0x250)
227#define USBD_DMARCLR(x) ((x) + 0x254)
228#define USBD_DMARSET(x) ((x) + 0x258)
229
230#define USBD_UDCAH(x) ((x) + 0x280)
231
232
233#define USBD_EPDMAST(x) ((x) + 0x284)
234#define USBD_EPDMAEN(x) ((x) + 0x288)
235#define USBD_EPDMADIS(x) ((x) + 0x28C)
236
237#define USBD_DMAINTST(x) ((x) + 0x290)
238#define USBD_DMAINTEN(x) ((x) + 0x294)
239
240#define USBD_EOTINTST(x) ((x) + 0x2A0)
241#define USBD_EOTINTCLR(x) ((x) + 0x2A4)
242#define USBD_EOTINTSET(x) ((x) + 0x2A8)
243
244#define USBD_NDDRTINTST(x) ((x) + 0x2AC)
245#define USBD_NDDRTINTCLR(x) ((x) + 0x2B0)
246#define USBD_NDDRTINTSET(x) ((x) + 0x2B4)
247
248#define USBD_SYSERRTINTST(x) ((x) + 0x2B8)
249#define USBD_SYSERRTINTCLR(x) ((x) + 0x2BC)
250#define USBD_SYSERRTINTSET(x) ((x) + 0x2C0)
251
252
253
254
255
256#define USBD_ERR_INT (1 << 9)
257#define USBD_EP_RLZED (1 << 8)
258#define USBD_TXENDPKT (1 << 7)
259#define USBD_RXENDPKT (1 << 6)
260#define USBD_CDFULL (1 << 5)
261#define USBD_CCEMPTY (1 << 4)
262#define USBD_DEV_STAT (1 << 3)
263#define USBD_EP_SLOW (1 << 2)
264#define USBD_EP_FAST (1 << 1)
265#define USBD_FRAME (1 << 0)
266
267
268
269
270
271
272#define USBD_RX_EP_SEL(e) (1 << ((e) << 1))
273
274
275#define USBD_TX_EP_SEL(e) (1 << (((e) << 1) + 1))
276
277
278
279
280
281
282
283
284
285
286#define USBD_EP_SEL(e) (1 << (e))
287
288
289
290
291#define USBD_SYS_ERR_INT (1 << 2)
292#define USBD_NEW_DD_INT (1 << 1)
293#define USBD_EOT_INT (1 << 0)
294
295
296
297
298#define USBD_PKT_RDY (1 << 11)
299#define USBD_DV (1 << 10)
300#define USBD_PK_LEN_MASK 0x3FF
301
302
303
304
305#define USBD_LOG_ENDPOINT(e) ((e) << 2)
306#define USBD_WR_EN (1 << 1)
307#define USBD_RD_EN (1 << 0)
308
309
310
311
312#define USBD_CMD_CODE(c) ((c) << 16)
313#define USBD_CMD_PHASE(p) ((p) << 8)
314
315
316
317
318#define USBD_DMAEP(e) (1 << (e))
319
320
321struct lpc32xx_usbd_dd {
322 u32 *dd_next;
323 u32 dd_setup;
324 u32 dd_buffer_addr;
325 u32 dd_status;
326 u32 dd_iso_ps_mem_addr;
327};
328
329
330#define DD_SETUP_ATLE_DMA_MODE 0x01
331#define DD_SETUP_NEXT_DD_VALID 0x04
332#define DD_SETUP_ISO_EP 0x10
333#define DD_SETUP_PACKETLEN(n) (((n) & 0x7FF) << 5)
334#define DD_SETUP_DMALENBYTES(n) (((n) & 0xFFFF) << 16)
335
336
337#define DD_STATUS_DD_RETIRED 0x01
338#define DD_STATUS_STS_MASK 0x1E
339#define DD_STATUS_STS_NS 0x00
340#define DD_STATUS_STS_BS 0x02
341#define DD_STATUS_STS_NC 0x04
342#define DD_STATUS_STS_DUR 0x06
343#define DD_STATUS_STS_DOR 0x08
344#define DD_STATUS_STS_SE 0x12
345#define DD_STATUS_PKT_VAL 0x20
346#define DD_STATUS_LSB_EX 0x40
347#define DD_STATUS_MSB_EX 0x80
348#define DD_STATUS_MLEN(n) (((n) >> 8) & 0x3F)
349#define DD_STATUS_CURDMACNT(n) (((n) >> 16) & 0xFFFF)
350
351
352
353
354
355
356
357#define FRAME_INT 0x00000001
358#define EP_FAST_INT 0x00000002
359#define EP_SLOW_INT 0x00000004
360#define DEV_STAT_INT 0x00000008
361#define CCEMTY_INT 0x00000010
362#define CDFULL_INT 0x00000020
363#define RxENDPKT_INT 0x00000040
364#define TxENDPKT_INT 0x00000080
365#define EP_RLZED_INT 0x00000100
366#define ERR_INT 0x00000200
367
368
369#define PKT_LNGTH_MASK 0x000003FF
370#define PKT_DV 0x00000400
371#define PKT_RDY 0x00000800
372
373
374#define CTRL_RD_EN 0x00000001
375#define CTRL_WR_EN 0x00000002
376
377
378#define CMD_SET_ADDR 0x00D00500
379#define CMD_CFG_DEV 0x00D80500
380#define CMD_SET_MODE 0x00F30500
381#define CMD_RD_FRAME 0x00F50500
382#define DAT_RD_FRAME 0x00F50200
383#define CMD_RD_TEST 0x00FD0500
384#define DAT_RD_TEST 0x00FD0200
385#define CMD_SET_DEV_STAT 0x00FE0500
386#define CMD_GET_DEV_STAT 0x00FE0500
387#define DAT_GET_DEV_STAT 0x00FE0200
388#define CMD_GET_ERR_CODE 0x00FF0500
389#define DAT_GET_ERR_CODE 0x00FF0200
390#define CMD_RD_ERR_STAT 0x00FB0500
391#define DAT_RD_ERR_STAT 0x00FB0200
392#define DAT_WR_BYTE(x) (0x00000100 | ((x) << 16))
393#define CMD_SEL_EP(x) (0x00000500 | ((x) << 16))
394#define DAT_SEL_EP(x) (0x00000200 | ((x) << 16))
395#define CMD_SEL_EP_CLRI(x) (0x00400500 | ((x) << 16))
396#define DAT_SEL_EP_CLRI(x) (0x00400200 | ((x) << 16))
397#define CMD_SET_EP_STAT(x) (0x00400500 | ((x) << 16))
398#define CMD_CLR_BUF 0x00F20500
399#define DAT_CLR_BUF 0x00F20200
400#define CMD_VALID_BUF 0x00FA0500
401
402
403#define DEV_ADDR_MASK 0x7F
404#define DEV_EN 0x80
405
406
407#define CONF_DVICE 0x01
408
409
410#define AP_CLK 0x01
411#define INAK_CI 0x02
412#define INAK_CO 0x04
413#define INAK_II 0x08
414#define INAK_IO 0x10
415#define INAK_BI 0x20
416#define INAK_BO 0x40
417
418
419#define DEV_CON 0x01
420#define DEV_CON_CH 0x02
421#define DEV_SUS 0x04
422#define DEV_SUS_CH 0x08
423#define DEV_RST 0x10
424
425
426#define ERR_EC_MASK 0x0F
427#define ERR_EA 0x10
428
429
430#define ERR_PID 0x01
431#define ERR_UEPKT 0x02
432#define ERR_DCRC 0x04
433#define ERR_TIMOUT 0x08
434#define ERR_EOP 0x10
435#define ERR_B_OVRN 0x20
436#define ERR_BTSTF 0x40
437#define ERR_TGL 0x80
438
439
440#define EP_SEL_F 0x01
441#define EP_SEL_ST 0x02
442#define EP_SEL_STP 0x04
443#define EP_SEL_PO 0x08
444#define EP_SEL_EPN 0x10
445#define EP_SEL_B_1_FULL 0x20
446#define EP_SEL_B_2_FULL 0x40
447
448
449#define EP_STAT_ST 0x01
450#define EP_STAT_DA 0x20
451#define EP_STAT_RF_MO 0x40
452#define EP_STAT_CND_ST 0x80
453
454
455#define CLR_BUF_PO 0x01
456
457
458#define EOT_INT 0x01
459#define NDD_REQ_INT 0x02
460#define SYS_ERR_INT 0x04
461
462#define DRIVER_VERSION "1.03"
463static const char driver_name[] = "lpc32xx_udc";
464
465
466
467
468
469
470#ifdef CONFIG_USB_GADGET_DEBUG_FILES
471static char *epnames[] = {"INT", "ISO", "BULK", "CTRL"};
472static const char debug_filename[] = "driver/udc";
473
474static void proc_ep_show(struct seq_file *s, struct lpc32xx_ep *ep)
475{
476 struct lpc32xx_request *req;
477
478 seq_printf(s, "\n");
479 seq_printf(s, "%12s, maxpacket %4d %3s",
480 ep->ep.name, ep->ep.maxpacket,
481 ep->is_in ? "in" : "out");
482 seq_printf(s, " type %4s", epnames[ep->eptype]);
483 seq_printf(s, " ints: %12d", ep->totalints);
484
485 if (list_empty(&ep->queue))
486 seq_printf(s, "\t(queue empty)\n");
487 else {
488 list_for_each_entry(req, &ep->queue, queue) {
489 u32 length = req->req.actual;
490
491 seq_printf(s, "\treq %p len %d/%d buf %p\n",
492 &req->req, length,
493 req->req.length, req->req.buf);
494 }
495 }
496}
497
498static int proc_udc_show(struct seq_file *s, void *unused)
499{
500 struct lpc32xx_udc *udc = s->private;
501 struct lpc32xx_ep *ep;
502 unsigned long flags;
503
504 seq_printf(s, "%s: version %s\n", driver_name, DRIVER_VERSION);
505
506 spin_lock_irqsave(&udc->lock, flags);
507
508 seq_printf(s, "vbus %s, pullup %s, %s powered%s, gadget %s\n\n",
509 udc->vbus ? "present" : "off",
510 udc->enabled ? (udc->vbus ? "active" : "enabled") :
511 "disabled",
512 udc->gadget.is_selfpowered ? "self" : "VBUS",
513 udc->suspended ? ", suspended" : "",
514 udc->driver ? udc->driver->driver.name : "(none)");
515
516 if (udc->enabled && udc->vbus) {
517 proc_ep_show(s, &udc->ep[0]);
518 list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list)
519 proc_ep_show(s, ep);
520 }
521
522 spin_unlock_irqrestore(&udc->lock, flags);
523
524 return 0;
525}
526
527static int proc_udc_open(struct inode *inode, struct file *file)
528{
529 return single_open(file, proc_udc_show, PDE_DATA(inode));
530}
531
532static const struct file_operations proc_ops = {
533 .owner = THIS_MODULE,
534 .open = proc_udc_open,
535 .read = seq_read,
536 .llseek = seq_lseek,
537 .release = single_release,
538};
539
540static void create_debug_file(struct lpc32xx_udc *udc)
541{
542 udc->pde = debugfs_create_file(debug_filename, 0, NULL, udc, &proc_ops);
543}
544
545static void remove_debug_file(struct lpc32xx_udc *udc)
546{
547 debugfs_remove(udc->pde);
548}
549
550#else
551static inline void create_debug_file(struct lpc32xx_udc *udc) {}
552static inline void remove_debug_file(struct lpc32xx_udc *udc) {}
553#endif
554
555
556static void isp1301_udc_configure(struct lpc32xx_udc *udc)
557{
558 u8 value;
559 s32 vendor, product;
560
561 vendor = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x00);
562 product = i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x02);
563
564 if (vendor == 0x0483 && product == 0xa0c4)
565 udc->atx = STOTG04;
566
567
568
569
570
571 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
572 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
573 MC1_UART_EN);
574
575
576 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
577 (ISP1301_I2C_MODE_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
578 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
579 ISP1301_I2C_MODE_CONTROL_1, (MC1_SPEED_REG | MC1_DAT_SE0));
580
581
582
583
584 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
585 (ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
586
587 value = MC2_BI_DI;
588 if (udc->atx != STOTG04)
589 value |= MC2_SPD_SUSP_CTRL;
590 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
591 ISP1301_I2C_MODE_CONTROL_2, value);
592
593
594 if (udc->board->vbus_drv_pol != 0)
595 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
596 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DRV);
597 else
598 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
599 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
600 OTG1_VBUS_DRV);
601
602
603
604
605 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
606 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR), ~0);
607 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
608 ISP1301_I2C_OTG_CONTROL_1,
609 (0 | OTG1_DM_PULLDOWN | OTG1_DP_PULLDOWN));
610
611
612 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
613 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
614 msleep(1);
615 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
616 (ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR),
617 OTG1_VBUS_DISCHRG);
618
619 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
620 ISP1301_I2C_INTERRUPT_LATCH | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
621
622 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
623 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
624 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
625 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
626
627 dev_info(udc->dev, "ISP1301 Vendor ID : 0x%04x\n", vendor);
628 dev_info(udc->dev, "ISP1301 Product ID : 0x%04x\n", product);
629 dev_info(udc->dev, "ISP1301 Version ID : 0x%04x\n",
630 i2c_smbus_read_word_data(udc->isp1301_i2c_client, 0x14));
631
632}
633
634
635static void isp1301_pullup_set(struct lpc32xx_udc *udc)
636{
637 if (udc->pullup)
638
639 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
640 ISP1301_I2C_OTG_CONTROL_1, OTG1_DP_PULLUP);
641 else
642
643 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
644 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
645 OTG1_DP_PULLUP);
646}
647
648static void pullup_work(struct work_struct *work)
649{
650 struct lpc32xx_udc *udc =
651 container_of(work, struct lpc32xx_udc, pullup_job);
652
653 isp1301_pullup_set(udc);
654}
655
656static void isp1301_pullup_enable(struct lpc32xx_udc *udc, int en_pullup,
657 int block)
658{
659 if (en_pullup == udc->pullup)
660 return;
661
662 udc->pullup = en_pullup;
663 if (block)
664 isp1301_pullup_set(udc);
665 else
666
667 schedule_work(&udc->pullup_job);
668}
669
670#ifdef CONFIG_PM
671
672static void isp1301_set_powerstate(struct lpc32xx_udc *udc, int enable)
673{
674
675 if (udc->atx == STOTG04)
676 return;
677
678 if (enable != 0)
679
680
681 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
682 ISP1301_I2C_MODE_CONTROL_2 | ISP1301_I2C_REG_CLEAR_ADDR,
683 MC2_GLOBAL_PWR_DN);
684 else
685
686 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
687 ISP1301_I2C_MODE_CONTROL_2, MC2_GLOBAL_PWR_DN);
688}
689
690static void power_work(struct work_struct *work)
691{
692 struct lpc32xx_udc *udc =
693 container_of(work, struct lpc32xx_udc, power_job);
694
695 isp1301_set_powerstate(udc, udc->poweron);
696}
697#endif
698
699
700
701
702
703
704
705static void udc_protocol_cmd_w(struct lpc32xx_udc *udc, u32 cmd)
706{
707 u32 pass = 0;
708 int to;
709
710
711 u32 tmp = readl(USBD_DEVINTST(udc->udp_baseaddr));
712 (void) tmp;
713
714 while (pass == 0) {
715 writel(USBD_CCEMPTY, USBD_DEVINTCLR(udc->udp_baseaddr));
716
717
718 writel(cmd, USBD_CMDCODE(udc->udp_baseaddr));
719 to = 10000;
720 while (((readl(USBD_DEVINTST(udc->udp_baseaddr)) &
721 USBD_CCEMPTY) == 0) && (to > 0)) {
722 to--;
723 }
724
725 if (to > 0)
726 pass = 1;
727
728 cpu_relax();
729 }
730}
731
732
733static inline void udc_protocol_cmd_data_w(struct lpc32xx_udc *udc, u32 cmd,
734 u32 data)
735{
736 udc_protocol_cmd_w(udc, cmd);
737 udc_protocol_cmd_w(udc, data);
738}
739
740
741
742static u32 udc_protocol_cmd_r(struct lpc32xx_udc *udc, u32 cmd)
743{
744 int to = 1000;
745
746
747 writel((USBD_CDFULL | USBD_CCEMPTY),
748 USBD_DEVINTCLR(udc->udp_baseaddr));
749
750
751 udc_protocol_cmd_w(udc, cmd);
752
753 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) & USBD_CDFULL))
754 && (to > 0))
755 to--;
756 if (!to)
757 dev_dbg(udc->dev,
758 "Protocol engine didn't receive response (CDFULL)\n");
759
760 return readl(USBD_CMDDATA(udc->udp_baseaddr));
761}
762
763
764
765
766
767
768
769static inline void uda_enable_devint(struct lpc32xx_udc *udc, u32 devmask)
770{
771 udc->enabled_devints |= devmask;
772 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
773}
774
775
776static inline void uda_disable_devint(struct lpc32xx_udc *udc, u32 mask)
777{
778 udc->enabled_devints &= ~mask;
779 writel(udc->enabled_devints, USBD_DEVINTEN(udc->udp_baseaddr));
780}
781
782
783static inline void uda_clear_devint(struct lpc32xx_udc *udc, u32 mask)
784{
785 writel(mask, USBD_DEVINTCLR(udc->udp_baseaddr));
786}
787
788
789
790
791
792
793
794static void uda_enable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
795{
796 udc->enabled_hwepints |= (1 << hwep);
797 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
798}
799
800
801static void uda_disable_hwepint(struct lpc32xx_udc *udc, u32 hwep)
802{
803 udc->enabled_hwepints &= ~(1 << hwep);
804 writel(udc->enabled_hwepints, USBD_EPINTEN(udc->udp_baseaddr));
805}
806
807
808static inline void uda_clear_hwepint(struct lpc32xx_udc *udc, u32 hwep)
809{
810 writel((1 << hwep), USBD_EPINTCLR(udc->udp_baseaddr));
811}
812
813
814static inline void udc_ep_dma_enable(struct lpc32xx_udc *udc, u32 hwep)
815{
816 writel((1 << hwep), USBD_EPDMAEN(udc->udp_baseaddr));
817}
818
819
820static inline void udc_ep_dma_disable(struct lpc32xx_udc *udc, u32 hwep)
821{
822 writel((1 << hwep), USBD_EPDMADIS(udc->udp_baseaddr));
823}
824
825
826
827
828
829
830
831
832
833static void udc_realize_hwep(struct lpc32xx_udc *udc, u32 hwep,
834 u32 maxpacket)
835{
836 int to = 1000;
837
838 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
839 writel(hwep, USBD_EPIND(udc->udp_baseaddr));
840 udc->realized_eps |= (1 << hwep);
841 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
842 writel(maxpacket, USBD_EPMAXPSIZE(udc->udp_baseaddr));
843
844
845 while ((!(readl(USBD_DEVINTST(udc->udp_baseaddr)) &
846 USBD_EP_RLZED)) && (to > 0))
847 to--;
848 if (!to)
849 dev_dbg(udc->dev, "EP not correctly realized in hardware\n");
850
851 writel(USBD_EP_RLZED, USBD_DEVINTCLR(udc->udp_baseaddr));
852}
853
854
855static void udc_unrealize_hwep(struct lpc32xx_udc *udc, u32 hwep)
856{
857 udc->realized_eps &= ~(1 << hwep);
858 writel(udc->realized_eps, USBD_REEP(udc->udp_baseaddr));
859}
860
861
862
863
864
865
866
867static u32 udc_selep_clrint(struct lpc32xx_udc *udc, u32 hwep)
868{
869 udc_protocol_cmd_w(udc, CMD_SEL_EP_CLRI(hwep));
870 return udc_protocol_cmd_r(udc, DAT_SEL_EP_CLRI(hwep));
871}
872
873
874static void udc_disable_hwep(struct lpc32xx_udc *udc, u32 hwep)
875{
876 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
877 DAT_WR_BYTE(EP_STAT_DA));
878}
879
880
881static void udc_stall_hwep(struct lpc32xx_udc *udc, u32 hwep)
882{
883 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
884 DAT_WR_BYTE(EP_STAT_ST));
885}
886
887
888static void udc_clrstall_hwep(struct lpc32xx_udc *udc, u32 hwep)
889{
890 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(hwep),
891 DAT_WR_BYTE(0));
892}
893
894
895static void udc_select_hwep(struct lpc32xx_udc *udc, u32 hwep)
896{
897 udc_protocol_cmd_w(udc, CMD_SEL_EP(hwep));
898}
899
900
901
902
903
904
905
906static void udc_clr_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
907{
908 udc_select_hwep(udc, hwep);
909 udc_protocol_cmd_w(udc, CMD_CLR_BUF);
910}
911
912
913static void udc_val_buffer_hwep(struct lpc32xx_udc *udc, u32 hwep)
914{
915 udc_select_hwep(udc, hwep);
916 udc_protocol_cmd_w(udc, CMD_VALID_BUF);
917}
918
919static inline u32 udc_clearep_getsts(struct lpc32xx_udc *udc, u32 hwep)
920{
921
922 uda_clear_hwepint(udc, hwep);
923 return udc_selep_clrint(udc, hwep);
924}
925
926
927
928
929
930
931
932static struct lpc32xx_usbd_dd_gad *udc_dd_alloc(struct lpc32xx_udc *udc)
933{
934 dma_addr_t dma;
935 struct lpc32xx_usbd_dd_gad *dd;
936
937 dd = dma_pool_alloc(udc->dd_cache, GFP_ATOMIC | GFP_DMA, &dma);
938 if (dd)
939 dd->this_dma = dma;
940
941 return dd;
942}
943
944
945static void udc_dd_free(struct lpc32xx_udc *udc, struct lpc32xx_usbd_dd_gad *dd)
946{
947 dma_pool_free(udc->dd_cache, dd, dd->this_dma);
948}
949
950
951
952
953
954
955
956
957
958static void udc_clk_set(struct lpc32xx_udc *udc, int enable)
959{
960 if (enable != 0) {
961 if (udc->clocked)
962 return;
963
964 udc->clocked = 1;
965 clk_prepare_enable(udc->usb_slv_clk);
966 } else {
967 if (!udc->clocked)
968 return;
969
970 udc->clocked = 0;
971 clk_disable_unprepare(udc->usb_slv_clk);
972 }
973}
974
975
976static void udc_set_address(struct lpc32xx_udc *udc, u32 addr)
977{
978
979
980 udc_protocol_cmd_data_w(udc, CMD_SET_ADDR,
981 DAT_WR_BYTE(DEV_EN | addr));
982}
983
984
985
986
987static int udc_ep_in_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
988{
989 struct lpc32xx_request *req;
990 u32 hwep = ep->hwep_num;
991
992 ep->req_pending = 1;
993
994
995 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
996
997
998 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
999
1000
1001 udc_ep_dma_enable(udc, hwep);
1002
1003
1004 if (req->req.length % ep->ep.maxpacket)
1005 req->send_zlp = 0;
1006
1007 return 0;
1008}
1009
1010
1011
1012
1013static int udc_ep_out_req_dma(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1014{
1015 struct lpc32xx_request *req;
1016 u32 hwep = ep->hwep_num;
1017
1018 ep->req_pending = 1;
1019
1020
1021 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1022
1023
1024 udc->udca_v_base[hwep] = req->dd_desc_ptr->this_dma;
1025
1026
1027 udc_ep_dma_enable(udc, hwep);
1028 return 0;
1029}
1030
1031static void udc_disable(struct lpc32xx_udc *udc)
1032{
1033 u32 i;
1034
1035
1036 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1037 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(0));
1038
1039
1040 uda_disable_devint(udc, 0x3FF);
1041
1042
1043 for (i = 0; i < 32; i++) {
1044 uda_disable_hwepint(udc, i);
1045 uda_clear_hwepint(udc, i);
1046 udc_disable_hwep(udc, i);
1047 udc_unrealize_hwep(udc, i);
1048 udc->udca_v_base[i] = 0;
1049
1050
1051 udc_ep_dma_disable(udc, i);
1052 writel((1 << i), USBD_EOTINTCLR(udc->udp_baseaddr));
1053 writel((1 << i), USBD_NDDRTINTCLR(udc->udp_baseaddr));
1054 writel((1 << i), USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1055 writel((1 << i), USBD_DMARCLR(udc->udp_baseaddr));
1056 }
1057
1058
1059 writel(0, USBD_DMAINTEN(udc->udp_baseaddr));
1060
1061 writel(0, USBD_UDCAH(udc->udp_baseaddr));
1062}
1063
1064static void udc_enable(struct lpc32xx_udc *udc)
1065{
1066 u32 i;
1067 struct lpc32xx_ep *ep = &udc->ep[0];
1068
1069
1070 udc_disable(udc);
1071
1072
1073 udc_protocol_cmd_data_w(udc, CMD_SET_DEV_STAT, DAT_WR_BYTE(DEV_CON));
1074
1075
1076 writel(USBD_EP_FAST, USBD_DEVINTPRI(udc->udp_baseaddr));
1077 writel(0xFFFF, USBD_EPINTPRI(udc->udp_baseaddr));
1078
1079
1080 writel(0x3FF, USBD_DEVINTCLR(udc->udp_baseaddr));
1081
1082
1083 writel(udc->udca_p_base, USBD_UDCAH(udc->udp_baseaddr));
1084
1085
1086 for (i = 0; i <= 1; i++) {
1087 udc_realize_hwep(udc, i, ep->ep.maxpacket);
1088 uda_enable_hwepint(udc, i);
1089 udc_select_hwep(udc, i);
1090 udc_clrstall_hwep(udc, i);
1091 udc_clr_buffer_hwep(udc, i);
1092 }
1093
1094
1095 uda_clear_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1096 USBD_EP_FAST));
1097 uda_enable_devint(udc, (USBD_ERR_INT | USBD_DEV_STAT | USBD_EP_SLOW |
1098 USBD_EP_FAST));
1099
1100
1101
1102 udc_set_address(udc, 0);
1103 udc_set_address(udc, 0);
1104
1105
1106 writel((USBD_SYS_ERR_INT | USBD_EOT_INT),
1107 USBD_DMAINTEN(udc->udp_baseaddr));
1108
1109 udc->dev_status = 0;
1110}
1111
1112
1113
1114
1115
1116
1117
1118static void uda_power_event(struct lpc32xx_udc *udc, u32 conn)
1119{
1120
1121 if (udc->board->conn_chgb != NULL)
1122 udc->board->conn_chgb(conn);
1123}
1124
1125
1126static void uda_resm_susp_event(struct lpc32xx_udc *udc, u32 conn)
1127{
1128
1129 if (udc->board->susp_chgb != NULL)
1130 udc->board->susp_chgb(conn);
1131
1132 if (conn)
1133 udc->suspended = 0;
1134 else
1135 udc->suspended = 1;
1136}
1137
1138
1139static void uda_remwkp_cgh(struct lpc32xx_udc *udc)
1140{
1141 if (udc->board->rmwk_chgb != NULL)
1142 udc->board->rmwk_chgb(udc->dev_status &
1143 (1 << USB_DEVICE_REMOTE_WAKEUP));
1144}
1145
1146
1147static void udc_pop_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1148{
1149 int n, i, bl;
1150 u16 *p16;
1151 u32 *p32, tmp, cbytes;
1152
1153
1154 switch (((uintptr_t) data) & 0x3) {
1155 case 0:
1156 p32 = (u32 *) data;
1157 cbytes = (bytes & ~0x3);
1158
1159
1160 for (n = 0; n < cbytes; n += 4)
1161 *p32++ = readl(USBD_RXDATA(udc->udp_baseaddr));
1162
1163
1164 bl = bytes - cbytes;
1165 if (bl) {
1166 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1167 for (n = 0; n < bl; n++)
1168 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1169
1170 }
1171 break;
1172
1173 case 1:
1174 case 3:
1175
1176 for (n = 0; n < bytes; n += 4) {
1177 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1178
1179 bl = bytes - n;
1180 if (bl > 4)
1181 bl = 4;
1182
1183 for (i = 0; i < bl; i++)
1184 data[n + i] = (u8) ((tmp >> (i * 8)) & 0xFF);
1185 }
1186 break;
1187
1188 case 2:
1189 p16 = (u16 *) data;
1190 cbytes = (bytes & ~0x3);
1191
1192
1193 for (n = 0; n < cbytes; n += 4) {
1194 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1195 *p16++ = (u16)(tmp & 0xFFFF);
1196 *p16++ = (u16)((tmp >> 16) & 0xFFFF);
1197 }
1198
1199
1200 bl = bytes - cbytes;
1201 if (bl) {
1202 tmp = readl(USBD_RXDATA(udc->udp_baseaddr));
1203 for (n = 0; n < bl; n++)
1204 data[cbytes + n] = ((tmp >> (n * 8)) & 0xFF);
1205 }
1206 break;
1207 }
1208}
1209
1210
1211
1212
1213
1214static u32 udc_read_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1215 u32 bytes)
1216{
1217 u32 tmpv;
1218 int to = 1000;
1219 u32 tmp, hwrep = ((hwep & 0x1E) << 1) | CTRL_RD_EN;
1220
1221
1222 writel(hwrep, USBD_CTRL(udc->udp_baseaddr));
1223
1224
1225 while ((((tmpv = readl(USBD_RXPLEN(udc->udp_baseaddr))) &
1226 PKT_RDY) == 0) && (to > 0))
1227 to--;
1228 if (!to)
1229 dev_dbg(udc->dev, "No packet ready on FIFO EP read\n");
1230
1231
1232 tmp = tmpv & PKT_LNGTH_MASK;
1233 if (bytes < tmp)
1234 tmp = bytes;
1235
1236 if ((tmp > 0) && (data != NULL))
1237 udc_pop_fifo(udc, (u8 *) data, tmp);
1238
1239 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1240
1241
1242 udc_clr_buffer_hwep(udc, hwep);
1243
1244 return tmp;
1245}
1246
1247
1248static void udc_stuff_fifo(struct lpc32xx_udc *udc, u8 *data, u32 bytes)
1249{
1250 int n, i, bl;
1251 u16 *p16;
1252 u32 *p32, tmp, cbytes;
1253
1254
1255 switch (((uintptr_t) data) & 0x3) {
1256 case 0:
1257 p32 = (u32 *) data;
1258 cbytes = (bytes & ~0x3);
1259
1260
1261 for (n = 0; n < cbytes; n += 4)
1262 writel(*p32++, USBD_TXDATA(udc->udp_baseaddr));
1263
1264
1265 bl = bytes - cbytes;
1266 if (bl) {
1267 tmp = 0;
1268 for (n = 0; n < bl; n++)
1269 tmp |= data[cbytes + n] << (n * 8);
1270
1271 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1272 }
1273 break;
1274
1275 case 1:
1276 case 3:
1277
1278 for (n = 0; n < bytes; n += 4) {
1279 bl = bytes - n;
1280 if (bl > 4)
1281 bl = 4;
1282
1283 tmp = 0;
1284 for (i = 0; i < bl; i++)
1285 tmp |= data[n + i] << (i * 8);
1286
1287 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1288 }
1289 break;
1290
1291 case 2:
1292 p16 = (u16 *) data;
1293 cbytes = (bytes & ~0x3);
1294
1295
1296 for (n = 0; n < cbytes; n += 4) {
1297 tmp = *p16++ & 0xFFFF;
1298 tmp |= (*p16++ & 0xFFFF) << 16;
1299 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1300 }
1301
1302
1303 bl = bytes - cbytes;
1304 if (bl) {
1305 tmp = 0;
1306 for (n = 0; n < bl; n++)
1307 tmp |= data[cbytes + n] << (n * 8);
1308
1309 writel(tmp, USBD_TXDATA(udc->udp_baseaddr));
1310 }
1311 break;
1312 }
1313}
1314
1315
1316
1317
1318static void udc_write_hwep(struct lpc32xx_udc *udc, u32 hwep, u32 *data,
1319 u32 bytes)
1320{
1321 u32 hwwep = ((hwep & 0x1E) << 1) | CTRL_WR_EN;
1322
1323 if ((bytes > 0) && (data == NULL))
1324 return;
1325
1326
1327 writel(hwwep, USBD_CTRL(udc->udp_baseaddr));
1328
1329 writel(bytes, USBD_TXPLEN(udc->udp_baseaddr));
1330
1331
1332 if (bytes == 0)
1333 writel(0, USBD_TXDATA(udc->udp_baseaddr));
1334 else
1335 udc_stuff_fifo(udc, (u8 *) data, bytes);
1336
1337 writel(((hwep & 0x1E) << 1), USBD_CTRL(udc->udp_baseaddr));
1338
1339 udc_val_buffer_hwep(udc, hwep);
1340}
1341
1342
1343
1344static void uda_usb_reset(struct lpc32xx_udc *udc)
1345{
1346 u32 i = 0;
1347
1348 udc_enable(udc);
1349 udc->gadget.speed = USB_SPEED_FULL;
1350
1351 for (i = 1; i < NUM_ENDPOINTS; i++) {
1352 struct lpc32xx_ep *ep = &udc->ep[i];
1353 ep->req_pending = 0;
1354 }
1355}
1356
1357
1358static void udc_ep0_send_zlp(struct lpc32xx_udc *udc)
1359{
1360 udc_write_hwep(udc, EP_IN, NULL, 0);
1361}
1362
1363
1364static u16 udc_get_current_frame(struct lpc32xx_udc *udc)
1365{
1366 u16 flo, fhi;
1367
1368 udc_protocol_cmd_w(udc, CMD_RD_FRAME);
1369 flo = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1370 fhi = (u16) udc_protocol_cmd_r(udc, DAT_RD_FRAME);
1371
1372 return (fhi << 8) | flo;
1373}
1374
1375
1376static inline void udc_set_device_configured(struct lpc32xx_udc *udc)
1377{
1378 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(CONF_DVICE));
1379}
1380
1381
1382static inline void udc_set_device_unconfigured(struct lpc32xx_udc *udc)
1383{
1384 udc_protocol_cmd_data_w(udc, CMD_CFG_DEV, DAT_WR_BYTE(0));
1385}
1386
1387
1388static void udc_reinit(struct lpc32xx_udc *udc)
1389{
1390 u32 i;
1391
1392 INIT_LIST_HEAD(&udc->gadget.ep_list);
1393 INIT_LIST_HEAD(&udc->gadget.ep0->ep_list);
1394
1395 for (i = 0; i < NUM_ENDPOINTS; i++) {
1396 struct lpc32xx_ep *ep = &udc->ep[i];
1397
1398 if (i != 0)
1399 list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list);
1400 usb_ep_set_maxpacket_limit(&ep->ep, ep->maxpacket);
1401 INIT_LIST_HEAD(&ep->queue);
1402 ep->req_pending = 0;
1403 }
1404
1405 udc->ep0state = WAIT_FOR_SETUP;
1406}
1407
1408
1409static void done(struct lpc32xx_ep *ep, struct lpc32xx_request *req, int status)
1410{
1411 struct lpc32xx_udc *udc = ep->udc;
1412
1413 list_del_init(&req->queue);
1414 if (req->req.status == -EINPROGRESS)
1415 req->req.status = status;
1416 else
1417 status = req->req.status;
1418
1419 if (ep->lep) {
1420 usb_gadget_unmap_request(&udc->gadget, &req->req, ep->is_in);
1421
1422
1423 udc_dd_free(udc, req->dd_desc_ptr);
1424 }
1425
1426 if (status && status != -ESHUTDOWN)
1427 ep_dbg(ep, "%s done %p, status %d\n", ep->ep.name, req, status);
1428
1429 ep->req_pending = 0;
1430 spin_unlock(&udc->lock);
1431 usb_gadget_giveback_request(&ep->ep, &req->req);
1432 spin_lock(&udc->lock);
1433}
1434
1435
1436static void nuke(struct lpc32xx_ep *ep, int status)
1437{
1438 struct lpc32xx_request *req;
1439
1440 while (!list_empty(&ep->queue)) {
1441 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1442 done(ep, req, status);
1443 }
1444
1445 if (status == -ESHUTDOWN) {
1446 uda_disable_hwepint(ep->udc, ep->hwep_num);
1447 udc_disable_hwep(ep->udc, ep->hwep_num);
1448 }
1449}
1450
1451
1452static int udc_ep0_in_req(struct lpc32xx_udc *udc)
1453{
1454 struct lpc32xx_request *req;
1455 struct lpc32xx_ep *ep0 = &udc->ep[0];
1456 u32 tsend, ts = 0;
1457
1458 if (list_empty(&ep0->queue))
1459
1460 return 0;
1461 else
1462 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1463 queue);
1464
1465 tsend = ts = req->req.length - req->req.actual;
1466 if (ts == 0) {
1467
1468 udc_ep0_send_zlp(udc);
1469 done(ep0, req, 0);
1470 return 1;
1471 } else if (ts > ep0->ep.maxpacket)
1472 ts = ep0->ep.maxpacket;
1473
1474
1475 udc_write_hwep(udc, EP_IN, (req->req.buf + req->req.actual), ts);
1476
1477
1478 req->req.actual += ts;
1479
1480 if (tsend >= ep0->ep.maxpacket)
1481 return 0;
1482
1483
1484 udc->ep0state = WAIT_FOR_SETUP;
1485 done(ep0, req, 0);
1486 return 1;
1487}
1488
1489
1490static int udc_ep0_out_req(struct lpc32xx_udc *udc)
1491{
1492 struct lpc32xx_request *req;
1493 struct lpc32xx_ep *ep0 = &udc->ep[0];
1494 u32 tr, bufferspace;
1495
1496 if (list_empty(&ep0->queue))
1497 return 0;
1498 else
1499 req = list_entry(ep0->queue.next, struct lpc32xx_request,
1500 queue);
1501
1502 if (req) {
1503 if (req->req.length == 0) {
1504
1505 done(ep0, req, 0);
1506 udc->ep0state = WAIT_FOR_SETUP;
1507 return 1;
1508 }
1509
1510
1511 bufferspace = req->req.length - req->req.actual;
1512 if (bufferspace > ep0->ep.maxpacket)
1513 bufferspace = ep0->ep.maxpacket;
1514
1515
1516 prefetchw(req->req.buf + req->req.actual);
1517 tr = udc_read_hwep(udc, EP_OUT, req->req.buf + req->req.actual,
1518 bufferspace);
1519 req->req.actual += bufferspace;
1520
1521 if (tr < ep0->ep.maxpacket) {
1522
1523 done(ep0, req, 0);
1524 udc->ep0state = WAIT_FOR_SETUP;
1525 return 1;
1526 }
1527 }
1528
1529 return 0;
1530}
1531
1532
1533static void stop_activity(struct lpc32xx_udc *udc)
1534{
1535 struct usb_gadget_driver *driver = udc->driver;
1536 int i;
1537
1538 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1539 driver = NULL;
1540
1541 udc->gadget.speed = USB_SPEED_UNKNOWN;
1542 udc->suspended = 0;
1543
1544 for (i = 0; i < NUM_ENDPOINTS; i++) {
1545 struct lpc32xx_ep *ep = &udc->ep[i];
1546 nuke(ep, -ESHUTDOWN);
1547 }
1548 if (driver) {
1549 spin_unlock(&udc->lock);
1550 driver->disconnect(&udc->gadget);
1551 spin_lock(&udc->lock);
1552 }
1553
1554 isp1301_pullup_enable(udc, 0, 0);
1555 udc_disable(udc);
1556 udc_reinit(udc);
1557}
1558
1559
1560
1561
1562
1563static void pullup(struct lpc32xx_udc *udc, int is_on)
1564{
1565 if (!udc->clocked)
1566 return;
1567
1568 if (!udc->enabled || !udc->vbus)
1569 is_on = 0;
1570
1571 if (is_on != udc->pullup)
1572 isp1301_pullup_enable(udc, is_on, 0);
1573}
1574
1575
1576static int lpc32xx_ep_disable(struct usb_ep *_ep)
1577{
1578 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1579 struct lpc32xx_udc *udc = ep->udc;
1580 unsigned long flags;
1581
1582 if ((ep->hwep_num_base == 0) || (ep->hwep_num == 0))
1583 return -EINVAL;
1584 spin_lock_irqsave(&udc->lock, flags);
1585
1586 nuke(ep, -ESHUTDOWN);
1587
1588
1589 udc_ep_dma_disable(udc, ep->hwep_num);
1590 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1591 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1592 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1593 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1594
1595
1596 udc->udca_v_base[ep->hwep_num] = 0;
1597
1598
1599 uda_clear_hwepint(udc, ep->hwep_num);
1600 udc_unrealize_hwep(udc, ep->hwep_num);
1601
1602 ep->hwep_num = 0;
1603
1604 spin_unlock_irqrestore(&udc->lock, flags);
1605
1606 atomic_dec(&udc->enabled_ep_cnt);
1607 wake_up(&udc->ep_disable_wait_queue);
1608
1609 return 0;
1610}
1611
1612
1613static int lpc32xx_ep_enable(struct usb_ep *_ep,
1614 const struct usb_endpoint_descriptor *desc)
1615{
1616 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1617 struct lpc32xx_udc *udc;
1618 u16 maxpacket;
1619 u32 tmp;
1620 unsigned long flags;
1621
1622
1623 if ((!_ep) || (!ep) || (!desc) ||
1624 (desc->bDescriptorType != USB_DT_ENDPOINT))
1625 return -EINVAL;
1626
1627 udc = ep->udc;
1628 maxpacket = usb_endpoint_maxp(desc);
1629 if ((maxpacket == 0) || (maxpacket > ep->maxpacket)) {
1630 dev_dbg(udc->dev, "bad ep descriptor's packet size\n");
1631 return -EINVAL;
1632 }
1633
1634
1635 if (ep->hwep_num_base == 0) {
1636 dev_dbg(udc->dev, "Can't re-enable EP0!!!\n");
1637 return -EINVAL;
1638 }
1639
1640
1641 if ((!udc->driver) || (udc->gadget.speed == USB_SPEED_UNKNOWN)) {
1642 dev_dbg(udc->dev, "bogus device state\n");
1643 return -ESHUTDOWN;
1644 }
1645
1646 tmp = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
1647 switch (tmp) {
1648 case USB_ENDPOINT_XFER_CONTROL:
1649 return -EINVAL;
1650
1651 case USB_ENDPOINT_XFER_INT:
1652 if (maxpacket > ep->maxpacket) {
1653 dev_dbg(udc->dev,
1654 "Bad INT endpoint maxpacket %d\n", maxpacket);
1655 return -EINVAL;
1656 }
1657 break;
1658
1659 case USB_ENDPOINT_XFER_BULK:
1660 switch (maxpacket) {
1661 case 8:
1662 case 16:
1663 case 32:
1664 case 64:
1665 break;
1666
1667 default:
1668 dev_dbg(udc->dev,
1669 "Bad BULK endpoint maxpacket %d\n", maxpacket);
1670 return -EINVAL;
1671 }
1672 break;
1673
1674 case USB_ENDPOINT_XFER_ISOC:
1675 break;
1676 }
1677 spin_lock_irqsave(&udc->lock, flags);
1678
1679
1680 ep->is_in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
1681 ep->ep.maxpacket = maxpacket;
1682
1683
1684 if (ep->is_in)
1685
1686 ep->hwep_num = ep->hwep_num_base + EP_IN;
1687 else
1688 ep->hwep_num = ep->hwep_num_base;
1689
1690 ep_dbg(ep, "EP enabled: %s, HW:%d, MP:%d IN:%d\n", ep->ep.name,
1691 ep->hwep_num, maxpacket, (ep->is_in == 1));
1692
1693
1694
1695 udc_realize_hwep(udc, ep->hwep_num, ep->ep.maxpacket);
1696 udc_clr_buffer_hwep(udc, ep->hwep_num);
1697 uda_disable_hwepint(udc, ep->hwep_num);
1698 udc_clrstall_hwep(udc, ep->hwep_num);
1699
1700
1701 udc_ep_dma_disable(udc, ep->hwep_num);
1702 writel(1 << ep->hwep_num, USBD_EOTINTCLR(udc->udp_baseaddr));
1703 writel(1 << ep->hwep_num, USBD_NDDRTINTCLR(udc->udp_baseaddr));
1704 writel(1 << ep->hwep_num, USBD_SYSERRTINTCLR(udc->udp_baseaddr));
1705 writel(1 << ep->hwep_num, USBD_DMARCLR(udc->udp_baseaddr));
1706
1707 spin_unlock_irqrestore(&udc->lock, flags);
1708
1709 atomic_inc(&udc->enabled_ep_cnt);
1710 return 0;
1711}
1712
1713
1714
1715
1716
1717static struct usb_request *lpc32xx_ep_alloc_request(struct usb_ep *_ep,
1718 gfp_t gfp_flags)
1719{
1720 struct lpc32xx_request *req;
1721
1722 req = kzalloc(sizeof(struct lpc32xx_request), gfp_flags);
1723 if (!req)
1724 return NULL;
1725
1726 INIT_LIST_HEAD(&req->queue);
1727 return &req->req;
1728}
1729
1730
1731
1732
1733
1734static void lpc32xx_ep_free_request(struct usb_ep *_ep,
1735 struct usb_request *_req)
1736{
1737 struct lpc32xx_request *req;
1738
1739 req = container_of(_req, struct lpc32xx_request, req);
1740 BUG_ON(!list_empty(&req->queue));
1741 kfree(req);
1742}
1743
1744
1745static int lpc32xx_ep_queue(struct usb_ep *_ep,
1746 struct usb_request *_req, gfp_t gfp_flags)
1747{
1748 struct lpc32xx_request *req;
1749 struct lpc32xx_ep *ep;
1750 struct lpc32xx_udc *udc;
1751 unsigned long flags;
1752 int status = 0;
1753
1754 req = container_of(_req, struct lpc32xx_request, req);
1755 ep = container_of(_ep, struct lpc32xx_ep, ep);
1756
1757 if (!_ep || !_req || !_req->complete || !_req->buf ||
1758 !list_empty(&req->queue))
1759 return -EINVAL;
1760
1761 udc = ep->udc;
1762
1763 if (udc->gadget.speed == USB_SPEED_UNKNOWN)
1764 return -EPIPE;
1765
1766 if (ep->lep) {
1767 struct lpc32xx_usbd_dd_gad *dd;
1768
1769 status = usb_gadget_map_request(&udc->gadget, _req, ep->is_in);
1770 if (status)
1771 return status;
1772
1773
1774 dd = udc_dd_alloc(udc);
1775 if (!dd) {
1776
1777 return -ENOMEM;
1778 }
1779 req->dd_desc_ptr = dd;
1780
1781
1782 dd->dd_next_phy = dd->dd_next_v = 0;
1783 dd->dd_buffer_addr = req->req.dma;
1784 dd->dd_status = 0;
1785
1786
1787 if (ep->eptype == EP_ISO_TYPE) {
1788 dd->dd_setup = DD_SETUP_ISO_EP |
1789 DD_SETUP_PACKETLEN(0) |
1790 DD_SETUP_DMALENBYTES(1);
1791 dd->dd_iso_ps_mem_addr = dd->this_dma + 24;
1792 if (ep->is_in)
1793 dd->iso_status[0] = req->req.length;
1794 else
1795 dd->iso_status[0] = 0;
1796 } else
1797 dd->dd_setup = DD_SETUP_PACKETLEN(ep->ep.maxpacket) |
1798 DD_SETUP_DMALENBYTES(req->req.length);
1799 }
1800
1801 ep_dbg(ep, "%s queue req %p len %d buf %p (in=%d) z=%d\n", _ep->name,
1802 _req, _req->length, _req->buf, ep->is_in, _req->zero);
1803
1804 spin_lock_irqsave(&udc->lock, flags);
1805
1806 _req->status = -EINPROGRESS;
1807 _req->actual = 0;
1808 req->send_zlp = _req->zero;
1809
1810
1811 if (list_empty(&ep->queue)) {
1812 list_add_tail(&req->queue, &ep->queue);
1813
1814 if (ep->hwep_num_base == 0) {
1815
1816 if (ep->is_in) {
1817
1818 udc->ep0state = DATA_IN;
1819 status = udc_ep0_in_req(udc);
1820 } else {
1821
1822 udc->ep0state = DATA_OUT;
1823 status = udc_ep0_out_req(udc);
1824 }
1825 } else if (ep->is_in) {
1826
1827 if (!ep->req_pending)
1828 udc_ep_in_req_dma(udc, ep);
1829 } else
1830
1831 if (!ep->req_pending)
1832 udc_ep_out_req_dma(udc, ep);
1833 } else
1834 list_add_tail(&req->queue, &ep->queue);
1835
1836 spin_unlock_irqrestore(&udc->lock, flags);
1837
1838 return (status < 0) ? status : 0;
1839}
1840
1841
1842static int lpc32xx_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1843{
1844 struct lpc32xx_ep *ep;
1845 struct lpc32xx_request *req;
1846 unsigned long flags;
1847
1848 ep = container_of(_ep, struct lpc32xx_ep, ep);
1849 if (!_ep || ep->hwep_num_base == 0)
1850 return -EINVAL;
1851
1852 spin_lock_irqsave(&ep->udc->lock, flags);
1853
1854
1855 list_for_each_entry(req, &ep->queue, queue) {
1856 if (&req->req == _req)
1857 break;
1858 }
1859 if (&req->req != _req) {
1860 spin_unlock_irqrestore(&ep->udc->lock, flags);
1861 return -EINVAL;
1862 }
1863
1864 done(ep, req, -ECONNRESET);
1865
1866 spin_unlock_irqrestore(&ep->udc->lock, flags);
1867
1868 return 0;
1869}
1870
1871
1872static int lpc32xx_ep_set_halt(struct usb_ep *_ep, int value)
1873{
1874 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1875 struct lpc32xx_udc *udc;
1876 unsigned long flags;
1877
1878 if ((!ep) || (ep->hwep_num <= 1))
1879 return -EINVAL;
1880
1881
1882 if (ep->is_in)
1883 return -EAGAIN;
1884
1885 udc = ep->udc;
1886 spin_lock_irqsave(&udc->lock, flags);
1887
1888 if (value == 1) {
1889
1890 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1891 DAT_WR_BYTE(EP_STAT_ST));
1892 } else {
1893
1894 ep->wedge = 0;
1895 udc_protocol_cmd_data_w(udc, CMD_SET_EP_STAT(ep->hwep_num),
1896 DAT_WR_BYTE(0));
1897 }
1898
1899 spin_unlock_irqrestore(&udc->lock, flags);
1900
1901 return 0;
1902}
1903
1904
1905static int lpc32xx_ep_set_wedge(struct usb_ep *_ep)
1906{
1907 struct lpc32xx_ep *ep = container_of(_ep, struct lpc32xx_ep, ep);
1908
1909 if (!_ep || !ep->udc)
1910 return -EINVAL;
1911
1912 ep->wedge = 1;
1913
1914 return usb_ep_set_halt(_ep);
1915}
1916
1917static const struct usb_ep_ops lpc32xx_ep_ops = {
1918 .enable = lpc32xx_ep_enable,
1919 .disable = lpc32xx_ep_disable,
1920 .alloc_request = lpc32xx_ep_alloc_request,
1921 .free_request = lpc32xx_ep_free_request,
1922 .queue = lpc32xx_ep_queue,
1923 .dequeue = lpc32xx_ep_dequeue,
1924 .set_halt = lpc32xx_ep_set_halt,
1925 .set_wedge = lpc32xx_ep_set_wedge,
1926};
1927
1928
1929static void udc_send_in_zlp(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1930{
1931
1932 udc_clearep_getsts(udc, ep->hwep_num);
1933
1934
1935 udc_write_hwep(udc, ep->hwep_num, NULL, 0);
1936}
1937
1938
1939
1940
1941
1942
1943static void udc_handle_eps(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1944{
1945 u32 epstatus;
1946 struct lpc32xx_request *req;
1947
1948 if (ep->hwep_num <= 0)
1949 return;
1950
1951 uda_clear_hwepint(udc, ep->hwep_num);
1952
1953
1954 if (!(udc->enabled_hwepints & (1 << ep->hwep_num)))
1955 return;
1956
1957
1958 epstatus = udc_clearep_getsts(udc, ep->hwep_num);
1959
1960
1961
1962
1963
1964 if (epstatus & EP_SEL_F)
1965 return;
1966
1967 if (ep->is_in) {
1968 udc_send_in_zlp(udc, ep);
1969 uda_disable_hwepint(udc, ep->hwep_num);
1970 } else
1971 return;
1972
1973
1974 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
1975 if (req) {
1976 done(ep, req, 0);
1977
1978
1979 if (!list_empty(&ep->queue)) {
1980 if (ep->is_in)
1981 udc_ep_in_req_dma(udc, ep);
1982 else
1983 udc_ep_out_req_dma(udc, ep);
1984 } else
1985 ep->req_pending = 0;
1986 }
1987}
1988
1989
1990
1991static void udc_handle_dma_ep(struct lpc32xx_udc *udc, struct lpc32xx_ep *ep)
1992{
1993 u32 status;
1994 struct lpc32xx_request *req;
1995 struct lpc32xx_usbd_dd_gad *dd;
1996
1997#ifdef CONFIG_USB_GADGET_DEBUG_FILES
1998 ep->totalints++;
1999#endif
2000
2001 req = list_entry(ep->queue.next, struct lpc32xx_request, queue);
2002 if (!req) {
2003 ep_err(ep, "DMA interrupt on no req!\n");
2004 return;
2005 }
2006 dd = req->dd_desc_ptr;
2007
2008
2009 if (!(dd->dd_status & DD_STATUS_DD_RETIRED))
2010 ep_warn(ep, "DMA descriptor did not retire\n");
2011
2012
2013 udc_ep_dma_disable(udc, ep->hwep_num);
2014 writel((1 << ep->hwep_num), USBD_EOTINTCLR(udc->udp_baseaddr));
2015 writel((1 << ep->hwep_num), USBD_NDDRTINTCLR(udc->udp_baseaddr));
2016
2017
2018 if (readl(USBD_SYSERRTINTST(udc->udp_baseaddr)) &
2019 (1 << ep->hwep_num)) {
2020 writel((1 << ep->hwep_num),
2021 USBD_SYSERRTINTCLR(udc->udp_baseaddr));
2022 ep_err(ep, "AHB critical error!\n");
2023 ep->req_pending = 0;
2024
2025
2026
2027
2028 done(ep, req, -ECONNABORTED);
2029 return;
2030 }
2031
2032
2033 status = dd->dd_status;
2034 switch (status & DD_STATUS_STS_MASK) {
2035 case DD_STATUS_STS_NS:
2036
2037 ep->req_pending = 0;
2038 ep_err(ep, "DMA critical EP error: DD not serviced (0x%x)!\n",
2039 status);
2040
2041 done(ep, req, -ECONNABORTED);
2042 return;
2043
2044 case DD_STATUS_STS_BS:
2045
2046 ep->req_pending = 0;
2047 ep_err(ep, "DMA critical EP error: EOT prior to service completion (0x%x)!\n",
2048 status);
2049 done(ep, req, -ECONNABORTED);
2050 return;
2051
2052 case DD_STATUS_STS_NC:
2053 case DD_STATUS_STS_DUR:
2054
2055
2056 break;
2057
2058 default:
2059
2060 ep->req_pending = 0;
2061 ep_err(ep, "DMA critical EP error: System error (0x%x)!\n",
2062 status);
2063 done(ep, req, -ECONNABORTED);
2064 return;
2065 }
2066
2067
2068 if (ep->eptype == EP_ISO_TYPE) {
2069 if (ep->is_in)
2070 req->req.actual = req->req.length;
2071 else
2072 req->req.actual = dd->iso_status[0] & 0xFFFF;
2073 } else
2074 req->req.actual += DD_STATUS_CURDMACNT(status);
2075
2076
2077
2078 if (req->send_zlp) {
2079
2080
2081
2082
2083
2084 if (udc_clearep_getsts(udc, ep->hwep_num) & EP_SEL_F) {
2085 udc_clearep_getsts(udc, ep->hwep_num);
2086 uda_enable_hwepint(udc, ep->hwep_num);
2087 udc_clearep_getsts(udc, ep->hwep_num);
2088
2089
2090 return;
2091 } else
2092 udc_send_in_zlp(udc, ep);
2093 }
2094
2095
2096 done(ep, req, 0);
2097
2098
2099 udc_clearep_getsts(udc, ep->hwep_num);
2100 if (!list_empty((&ep->queue))) {
2101 if (ep->is_in)
2102 udc_ep_in_req_dma(udc, ep);
2103 else
2104 udc_ep_out_req_dma(udc, ep);
2105 } else
2106 ep->req_pending = 0;
2107
2108}
2109
2110
2111
2112
2113
2114
2115static void udc_handle_dev(struct lpc32xx_udc *udc)
2116{
2117 u32 tmp;
2118
2119 udc_protocol_cmd_w(udc, CMD_GET_DEV_STAT);
2120 tmp = udc_protocol_cmd_r(udc, DAT_GET_DEV_STAT);
2121
2122 if (tmp & DEV_RST)
2123 uda_usb_reset(udc);
2124 else if (tmp & DEV_CON_CH)
2125 uda_power_event(udc, (tmp & DEV_CON));
2126 else if (tmp & DEV_SUS_CH) {
2127 if (tmp & DEV_SUS) {
2128 if (udc->vbus == 0)
2129 stop_activity(udc);
2130 else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2131 udc->driver) {
2132
2133 udc->poweron = 0;
2134 schedule_work(&udc->pullup_job);
2135 uda_resm_susp_event(udc, 1);
2136 }
2137 } else if ((udc->gadget.speed != USB_SPEED_UNKNOWN) &&
2138 udc->driver && udc->vbus) {
2139 uda_resm_susp_event(udc, 0);
2140
2141 udc->poweron = 1;
2142 schedule_work(&udc->pullup_job);
2143 }
2144 }
2145}
2146
2147static int udc_get_status(struct lpc32xx_udc *udc, u16 reqtype, u16 wIndex)
2148{
2149 struct lpc32xx_ep *ep;
2150 u32 ep0buff = 0, tmp;
2151
2152 switch (reqtype & USB_RECIP_MASK) {
2153 case USB_RECIP_INTERFACE:
2154 break;
2155
2156 case USB_RECIP_DEVICE:
2157 ep0buff = udc->gadget.is_selfpowered;
2158 if (udc->dev_status & (1 << USB_DEVICE_REMOTE_WAKEUP))
2159 ep0buff |= (1 << USB_DEVICE_REMOTE_WAKEUP);
2160 break;
2161
2162 case USB_RECIP_ENDPOINT:
2163 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2164 ep = &udc->ep[tmp];
2165 if ((tmp == 0) || (tmp >= NUM_ENDPOINTS))
2166 return -EOPNOTSUPP;
2167
2168 if (wIndex & USB_DIR_IN) {
2169 if (!ep->is_in)
2170 return -EOPNOTSUPP;
2171 } else if (ep->is_in)
2172 return -EOPNOTSUPP;
2173
2174
2175 udc_protocol_cmd_w(udc, CMD_SEL_EP(ep->hwep_num));
2176 tmp = udc_protocol_cmd_r(udc, DAT_SEL_EP(ep->hwep_num));
2177
2178 if (tmp & EP_SEL_ST)
2179 ep0buff = (1 << USB_ENDPOINT_HALT);
2180 else
2181 ep0buff = 0;
2182 break;
2183
2184 default:
2185 break;
2186 }
2187
2188
2189 udc_write_hwep(udc, EP_IN, &ep0buff, 2);
2190
2191 return 0;
2192}
2193
2194static void udc_handle_ep0_setup(struct lpc32xx_udc *udc)
2195{
2196 struct lpc32xx_ep *ep, *ep0 = &udc->ep[0];
2197 struct usb_ctrlrequest ctrlpkt;
2198 int i, bytes;
2199 u16 wIndex, wValue, reqtype, req, tmp;
2200
2201
2202 nuke(ep0, -EPROTO);
2203
2204
2205 bytes = udc_read_hwep(udc, EP_OUT, (u32 *) &ctrlpkt, 8);
2206 if (bytes != 8) {
2207 ep_warn(ep0, "Incorrectly sized setup packet (s/b 8, is %d)!\n",
2208 bytes);
2209 return;
2210 }
2211
2212
2213 wIndex = le16_to_cpu(ctrlpkt.wIndex);
2214 wValue = le16_to_cpu(ctrlpkt.wValue);
2215 reqtype = le16_to_cpu(ctrlpkt.bRequestType);
2216
2217
2218 if (likely(reqtype & USB_DIR_IN))
2219 ep0->is_in = 1;
2220 else
2221 ep0->is_in = 0;
2222
2223
2224 req = le16_to_cpu(ctrlpkt.bRequest);
2225 switch (req) {
2226 case USB_REQ_CLEAR_FEATURE:
2227 case USB_REQ_SET_FEATURE:
2228 switch (reqtype) {
2229 case (USB_TYPE_STANDARD | USB_RECIP_DEVICE):
2230 if (wValue != USB_DEVICE_REMOTE_WAKEUP)
2231 goto stall;
2232
2233
2234 if (req == USB_REQ_CLEAR_FEATURE)
2235 udc->dev_status &=
2236 ~(1 << USB_DEVICE_REMOTE_WAKEUP);
2237 else
2238 udc->dev_status |=
2239 (1 << USB_DEVICE_REMOTE_WAKEUP);
2240 uda_remwkp_cgh(udc);
2241 goto zlp_send;
2242
2243 case (USB_TYPE_STANDARD | USB_RECIP_ENDPOINT):
2244 tmp = wIndex & USB_ENDPOINT_NUMBER_MASK;
2245 if ((wValue != USB_ENDPOINT_HALT) ||
2246 (tmp >= NUM_ENDPOINTS))
2247 break;
2248
2249
2250 ep = &udc->ep[tmp];
2251 tmp = ep->hwep_num;
2252 if (tmp == 0)
2253 break;
2254
2255 if (req == USB_REQ_SET_FEATURE)
2256 udc_stall_hwep(udc, tmp);
2257 else if (!ep->wedge)
2258 udc_clrstall_hwep(udc, tmp);
2259
2260 goto zlp_send;
2261
2262 default:
2263 break;
2264 }
2265 break;
2266
2267 case USB_REQ_SET_ADDRESS:
2268 if (reqtype == (USB_TYPE_STANDARD | USB_RECIP_DEVICE)) {
2269 udc_set_address(udc, wValue);
2270 goto zlp_send;
2271 }
2272 break;
2273
2274 case USB_REQ_GET_STATUS:
2275 udc_get_status(udc, reqtype, wIndex);
2276 return;
2277
2278 default:
2279 break;
2280 }
2281
2282 if (likely(udc->driver)) {
2283
2284
2285 spin_unlock(&udc->lock);
2286 i = udc->driver->setup(&udc->gadget, &ctrlpkt);
2287
2288 spin_lock(&udc->lock);
2289 if (req == USB_REQ_SET_CONFIGURATION) {
2290
2291 if (wValue) {
2292
2293 udc_set_device_configured(udc);
2294
2295 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2296 DAT_WR_BYTE(AP_CLK |
2297 INAK_BI | INAK_II));
2298 } else {
2299
2300 udc_set_device_unconfigured(udc);
2301
2302
2303 udc_protocol_cmd_data_w(udc, CMD_SET_MODE,
2304 DAT_WR_BYTE(AP_CLK));
2305 }
2306 }
2307
2308 if (i < 0) {
2309
2310 dev_dbg(udc->dev,
2311 "req %02x.%02x protocol STALL; stat %d\n",
2312 reqtype, req, i);
2313 udc->ep0state = WAIT_FOR_SETUP;
2314 goto stall;
2315 }
2316 }
2317
2318 if (!ep0->is_in)
2319 udc_ep0_send_zlp(udc);
2320
2321 return;
2322
2323stall:
2324 udc_stall_hwep(udc, EP_IN);
2325 return;
2326
2327zlp_send:
2328 udc_ep0_send_zlp(udc);
2329 return;
2330}
2331
2332
2333static void udc_handle_ep0_in(struct lpc32xx_udc *udc)
2334{
2335 struct lpc32xx_ep *ep0 = &udc->ep[0];
2336 u32 epstatus;
2337
2338
2339 epstatus = udc_clearep_getsts(udc, EP_IN);
2340
2341#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2342 ep0->totalints++;
2343#endif
2344
2345
2346 if (epstatus & EP_SEL_ST) {
2347 udc_clrstall_hwep(udc, EP_IN);
2348 nuke(ep0, -ECONNABORTED);
2349 udc->ep0state = WAIT_FOR_SETUP;
2350 return;
2351 }
2352
2353
2354 if (!(epstatus & EP_SEL_F)) {
2355
2356 if (udc->ep0state == DATA_IN)
2357 udc_ep0_in_req(udc);
2358 else {
2359
2360 nuke(ep0, -ECONNABORTED);
2361 udc->ep0state = WAIT_FOR_SETUP;
2362 }
2363 }
2364}
2365
2366
2367static void udc_handle_ep0_out(struct lpc32xx_udc *udc)
2368{
2369 struct lpc32xx_ep *ep0 = &udc->ep[0];
2370 u32 epstatus;
2371
2372
2373 epstatus = udc_clearep_getsts(udc, EP_OUT);
2374
2375
2376#ifdef CONFIG_USB_GADGET_DEBUG_FILES
2377 ep0->totalints++;
2378#endif
2379
2380
2381 if (epstatus & EP_SEL_ST) {
2382 udc_clrstall_hwep(udc, EP_OUT);
2383 nuke(ep0, -ECONNABORTED);
2384 udc->ep0state = WAIT_FOR_SETUP;
2385 return;
2386 }
2387
2388
2389 if (epstatus & EP_SEL_EPN)
2390 return;
2391
2392 if (epstatus & EP_SEL_STP) {
2393 nuke(ep0, 0);
2394 udc->ep0state = WAIT_FOR_SETUP;
2395 }
2396
2397
2398 if (epstatus & EP_SEL_F)
2399
2400 switch (udc->ep0state) {
2401 case WAIT_FOR_SETUP:
2402 udc_handle_ep0_setup(udc);
2403 break;
2404
2405 case DATA_OUT:
2406 udc_ep0_out_req(udc);
2407 break;
2408
2409 default:
2410
2411 nuke(ep0, -ECONNABORTED);
2412 udc->ep0state = WAIT_FOR_SETUP;
2413 }
2414}
2415
2416
2417static int lpc32xx_get_frame(struct usb_gadget *gadget)
2418{
2419 int frame;
2420 unsigned long flags;
2421 struct lpc32xx_udc *udc = to_udc(gadget);
2422
2423 if (!udc->clocked)
2424 return -EINVAL;
2425
2426 spin_lock_irqsave(&udc->lock, flags);
2427
2428 frame = (int) udc_get_current_frame(udc);
2429
2430 spin_unlock_irqrestore(&udc->lock, flags);
2431
2432 return frame;
2433}
2434
2435static int lpc32xx_wakeup(struct usb_gadget *gadget)
2436{
2437 return -ENOTSUPP;
2438}
2439
2440static int lpc32xx_set_selfpowered(struct usb_gadget *gadget, int is_on)
2441{
2442 gadget->is_selfpowered = (is_on != 0);
2443
2444 return 0;
2445}
2446
2447
2448
2449
2450
2451static int lpc32xx_vbus_session(struct usb_gadget *gadget, int is_active)
2452{
2453 unsigned long flags;
2454 struct lpc32xx_udc *udc = to_udc(gadget);
2455
2456 spin_lock_irqsave(&udc->lock, flags);
2457
2458
2459 if (udc->driver) {
2460 udc_clk_set(udc, 1);
2461 udc_enable(udc);
2462 pullup(udc, is_active);
2463 } else {
2464 stop_activity(udc);
2465 pullup(udc, 0);
2466
2467 spin_unlock_irqrestore(&udc->lock, flags);
2468
2469
2470
2471
2472
2473 if (atomic_read(&udc->enabled_ep_cnt))
2474 wait_event_interruptible(udc->ep_disable_wait_queue,
2475 (atomic_read(&udc->enabled_ep_cnt) == 0));
2476
2477 spin_lock_irqsave(&udc->lock, flags);
2478
2479 udc_clk_set(udc, 0);
2480 }
2481
2482 spin_unlock_irqrestore(&udc->lock, flags);
2483
2484 return 0;
2485}
2486
2487
2488static int lpc32xx_pullup(struct usb_gadget *gadget, int is_on)
2489{
2490 struct lpc32xx_udc *udc = to_udc(gadget);
2491
2492
2493 pullup(udc, is_on);
2494
2495 return 0;
2496}
2497
2498static int lpc32xx_start(struct usb_gadget *, struct usb_gadget_driver *);
2499static int lpc32xx_stop(struct usb_gadget *);
2500
2501static const struct usb_gadget_ops lpc32xx_udc_ops = {
2502 .get_frame = lpc32xx_get_frame,
2503 .wakeup = lpc32xx_wakeup,
2504 .set_selfpowered = lpc32xx_set_selfpowered,
2505 .vbus_session = lpc32xx_vbus_session,
2506 .pullup = lpc32xx_pullup,
2507 .udc_start = lpc32xx_start,
2508 .udc_stop = lpc32xx_stop,
2509};
2510
2511static void nop_release(struct device *dev)
2512{
2513
2514}
2515
2516static const struct lpc32xx_udc controller_template = {
2517 .gadget = {
2518 .ops = &lpc32xx_udc_ops,
2519 .name = driver_name,
2520 .dev = {
2521 .init_name = "gadget",
2522 .release = nop_release,
2523 }
2524 },
2525 .ep[0] = {
2526 .ep = {
2527 .name = "ep0",
2528 .ops = &lpc32xx_ep_ops,
2529 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_CONTROL,
2530 USB_EP_CAPS_DIR_ALL),
2531 },
2532 .maxpacket = 64,
2533 .hwep_num_base = 0,
2534 .hwep_num = 0,
2535 .lep = 0,
2536 .eptype = EP_CTL_TYPE,
2537 },
2538 .ep[1] = {
2539 .ep = {
2540 .name = "ep1-int",
2541 .ops = &lpc32xx_ep_ops,
2542 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2543 USB_EP_CAPS_DIR_ALL),
2544 },
2545 .maxpacket = 64,
2546 .hwep_num_base = 2,
2547 .hwep_num = 0,
2548 .lep = 1,
2549 .eptype = EP_INT_TYPE,
2550 },
2551 .ep[2] = {
2552 .ep = {
2553 .name = "ep2-bulk",
2554 .ops = &lpc32xx_ep_ops,
2555 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2556 USB_EP_CAPS_DIR_ALL),
2557 },
2558 .maxpacket = 64,
2559 .hwep_num_base = 4,
2560 .hwep_num = 0,
2561 .lep = 2,
2562 .eptype = EP_BLK_TYPE,
2563 },
2564 .ep[3] = {
2565 .ep = {
2566 .name = "ep3-iso",
2567 .ops = &lpc32xx_ep_ops,
2568 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2569 USB_EP_CAPS_DIR_ALL),
2570 },
2571 .maxpacket = 1023,
2572 .hwep_num_base = 6,
2573 .hwep_num = 0,
2574 .lep = 3,
2575 .eptype = EP_ISO_TYPE,
2576 },
2577 .ep[4] = {
2578 .ep = {
2579 .name = "ep4-int",
2580 .ops = &lpc32xx_ep_ops,
2581 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2582 USB_EP_CAPS_DIR_ALL),
2583 },
2584 .maxpacket = 64,
2585 .hwep_num_base = 8,
2586 .hwep_num = 0,
2587 .lep = 4,
2588 .eptype = EP_INT_TYPE,
2589 },
2590 .ep[5] = {
2591 .ep = {
2592 .name = "ep5-bulk",
2593 .ops = &lpc32xx_ep_ops,
2594 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2595 USB_EP_CAPS_DIR_ALL),
2596 },
2597 .maxpacket = 64,
2598 .hwep_num_base = 10,
2599 .hwep_num = 0,
2600 .lep = 5,
2601 .eptype = EP_BLK_TYPE,
2602 },
2603 .ep[6] = {
2604 .ep = {
2605 .name = "ep6-iso",
2606 .ops = &lpc32xx_ep_ops,
2607 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2608 USB_EP_CAPS_DIR_ALL),
2609 },
2610 .maxpacket = 1023,
2611 .hwep_num_base = 12,
2612 .hwep_num = 0,
2613 .lep = 6,
2614 .eptype = EP_ISO_TYPE,
2615 },
2616 .ep[7] = {
2617 .ep = {
2618 .name = "ep7-int",
2619 .ops = &lpc32xx_ep_ops,
2620 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2621 USB_EP_CAPS_DIR_ALL),
2622 },
2623 .maxpacket = 64,
2624 .hwep_num_base = 14,
2625 .hwep_num = 0,
2626 .lep = 7,
2627 .eptype = EP_INT_TYPE,
2628 },
2629 .ep[8] = {
2630 .ep = {
2631 .name = "ep8-bulk",
2632 .ops = &lpc32xx_ep_ops,
2633 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2634 USB_EP_CAPS_DIR_ALL),
2635 },
2636 .maxpacket = 64,
2637 .hwep_num_base = 16,
2638 .hwep_num = 0,
2639 .lep = 8,
2640 .eptype = EP_BLK_TYPE,
2641 },
2642 .ep[9] = {
2643 .ep = {
2644 .name = "ep9-iso",
2645 .ops = &lpc32xx_ep_ops,
2646 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2647 USB_EP_CAPS_DIR_ALL),
2648 },
2649 .maxpacket = 1023,
2650 .hwep_num_base = 18,
2651 .hwep_num = 0,
2652 .lep = 9,
2653 .eptype = EP_ISO_TYPE,
2654 },
2655 .ep[10] = {
2656 .ep = {
2657 .name = "ep10-int",
2658 .ops = &lpc32xx_ep_ops,
2659 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2660 USB_EP_CAPS_DIR_ALL),
2661 },
2662 .maxpacket = 64,
2663 .hwep_num_base = 20,
2664 .hwep_num = 0,
2665 .lep = 10,
2666 .eptype = EP_INT_TYPE,
2667 },
2668 .ep[11] = {
2669 .ep = {
2670 .name = "ep11-bulk",
2671 .ops = &lpc32xx_ep_ops,
2672 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2673 USB_EP_CAPS_DIR_ALL),
2674 },
2675 .maxpacket = 64,
2676 .hwep_num_base = 22,
2677 .hwep_num = 0,
2678 .lep = 11,
2679 .eptype = EP_BLK_TYPE,
2680 },
2681 .ep[12] = {
2682 .ep = {
2683 .name = "ep12-iso",
2684 .ops = &lpc32xx_ep_ops,
2685 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_ISO,
2686 USB_EP_CAPS_DIR_ALL),
2687 },
2688 .maxpacket = 1023,
2689 .hwep_num_base = 24,
2690 .hwep_num = 0,
2691 .lep = 12,
2692 .eptype = EP_ISO_TYPE,
2693 },
2694 .ep[13] = {
2695 .ep = {
2696 .name = "ep13-int",
2697 .ops = &lpc32xx_ep_ops,
2698 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_INT,
2699 USB_EP_CAPS_DIR_ALL),
2700 },
2701 .maxpacket = 64,
2702 .hwep_num_base = 26,
2703 .hwep_num = 0,
2704 .lep = 13,
2705 .eptype = EP_INT_TYPE,
2706 },
2707 .ep[14] = {
2708 .ep = {
2709 .name = "ep14-bulk",
2710 .ops = &lpc32xx_ep_ops,
2711 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2712 USB_EP_CAPS_DIR_ALL),
2713 },
2714 .maxpacket = 64,
2715 .hwep_num_base = 28,
2716 .hwep_num = 0,
2717 .lep = 14,
2718 .eptype = EP_BLK_TYPE,
2719 },
2720 .ep[15] = {
2721 .ep = {
2722 .name = "ep15-bulk",
2723 .ops = &lpc32xx_ep_ops,
2724 .caps = USB_EP_CAPS(USB_EP_CAPS_TYPE_BULK,
2725 USB_EP_CAPS_DIR_ALL),
2726 },
2727 .maxpacket = 1023,
2728 .hwep_num_base = 30,
2729 .hwep_num = 0,
2730 .lep = 15,
2731 .eptype = EP_BLK_TYPE,
2732 },
2733};
2734
2735
2736static irqreturn_t lpc32xx_usb_lp_irq(int irq, void *_udc)
2737{
2738 u32 tmp, devstat;
2739 struct lpc32xx_udc *udc = _udc;
2740
2741 spin_lock(&udc->lock);
2742
2743
2744 devstat = readl(USBD_DEVINTST(udc->udp_baseaddr));
2745
2746 devstat &= ~USBD_EP_FAST;
2747 writel(devstat, USBD_DEVINTCLR(udc->udp_baseaddr));
2748 devstat = devstat & udc->enabled_devints;
2749
2750
2751 if (devstat & USBD_DEV_STAT)
2752 udc_handle_dev(udc);
2753
2754
2755
2756
2757
2758
2759 if (devstat & ERR_INT) {
2760
2761
2762
2763
2764 udc_protocol_cmd_w(udc, CMD_RD_ERR_STAT);
2765 tmp = udc_protocol_cmd_r(udc, DAT_RD_ERR_STAT);
2766 dev_dbg(udc->dev, "Device error (0x%x)!\n", tmp);
2767 }
2768
2769 spin_unlock(&udc->lock);
2770
2771 return IRQ_HANDLED;
2772}
2773
2774
2775static irqreturn_t lpc32xx_usb_hp_irq(int irq, void *_udc)
2776{
2777 u32 tmp;
2778 struct lpc32xx_udc *udc = _udc;
2779
2780 spin_lock(&udc->lock);
2781
2782
2783 writel(USBD_EP_FAST, USBD_DEVINTCLR(udc->udp_baseaddr));
2784
2785
2786 tmp = readl(USBD_EPINTST(udc->udp_baseaddr));
2787
2788
2789 if (tmp & (EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2790
2791 if (tmp & (EP_MASK_SEL(0, EP_IN)))
2792 udc_handle_ep0_in(udc);
2793
2794
2795 if (tmp & (EP_MASK_SEL(0, EP_OUT)))
2796 udc_handle_ep0_out(udc);
2797 }
2798
2799
2800 if (tmp & ~(EP_MASK_SEL(0, EP_OUT) | EP_MASK_SEL(0, EP_IN))) {
2801 int i;
2802
2803
2804 for (i = 1; i < NUM_ENDPOINTS; i++) {
2805 if (tmp & (1 << udc->ep[i].hwep_num))
2806 udc_handle_eps(udc, &udc->ep[i]);
2807 }
2808 }
2809
2810 spin_unlock(&udc->lock);
2811
2812 return IRQ_HANDLED;
2813}
2814
2815static irqreturn_t lpc32xx_usb_devdma_irq(int irq, void *_udc)
2816{
2817 struct lpc32xx_udc *udc = _udc;
2818
2819 int i;
2820 u32 tmp;
2821
2822 spin_lock(&udc->lock);
2823
2824
2825 tmp = readl(USBD_EOTINTST(udc->udp_baseaddr)) |
2826 (readl(USBD_EPDMAST(udc->udp_baseaddr)) &
2827 readl(USBD_NDDRTINTST(udc->udp_baseaddr))) |
2828 readl(USBD_SYSERRTINTST(udc->udp_baseaddr));
2829 for (i = 1; i < NUM_ENDPOINTS; i++) {
2830 if (tmp & (1 << udc->ep[i].hwep_num))
2831 udc_handle_dma_ep(udc, &udc->ep[i]);
2832 }
2833
2834 spin_unlock(&udc->lock);
2835
2836 return IRQ_HANDLED;
2837}
2838
2839
2840
2841
2842
2843
2844static void vbus_work(struct lpc32xx_udc *udc)
2845{
2846 u8 value;
2847
2848 if (udc->enabled != 0) {
2849
2850 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2851 ISP1301_I2C_OTG_CONTROL_1, OTG1_VBUS_DISCHRG);
2852
2853
2854 msleep(100);
2855
2856
2857 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2858 ISP1301_I2C_OTG_CONTROL_1 | ISP1301_I2C_REG_CLEAR_ADDR,
2859 OTG1_VBUS_DISCHRG);
2860
2861
2862 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2863 ISP1301_I2C_INTERRUPT_LATCH |
2864 ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2865
2866
2867 value = i2c_smbus_read_byte_data(udc->isp1301_i2c_client,
2868 ISP1301_I2C_INTERRUPT_SOURCE);
2869
2870
2871 if (value & INT_SESS_VLD)
2872 udc->vbus = 1;
2873 else
2874 udc->vbus = 0;
2875
2876
2877 if (udc->last_vbus != udc->vbus) {
2878 udc->last_vbus = udc->vbus;
2879 lpc32xx_vbus_session(&udc->gadget, udc->vbus);
2880 }
2881 }
2882}
2883
2884static irqreturn_t lpc32xx_usb_vbus_irq(int irq, void *_udc)
2885{
2886 struct lpc32xx_udc *udc = _udc;
2887
2888 vbus_work(udc);
2889
2890 return IRQ_HANDLED;
2891}
2892
2893static int lpc32xx_start(struct usb_gadget *gadget,
2894 struct usb_gadget_driver *driver)
2895{
2896 struct lpc32xx_udc *udc = to_udc(gadget);
2897
2898 if (!driver || driver->max_speed < USB_SPEED_FULL || !driver->setup) {
2899 dev_err(udc->dev, "bad parameter.\n");
2900 return -EINVAL;
2901 }
2902
2903 if (udc->driver) {
2904 dev_err(udc->dev, "UDC already has a gadget driver\n");
2905 return -EBUSY;
2906 }
2907
2908 udc->driver = driver;
2909 udc->gadget.dev.of_node = udc->dev->of_node;
2910 udc->enabled = 1;
2911 udc->gadget.is_selfpowered = 1;
2912 udc->vbus = 0;
2913
2914
2915 udc->last_vbus = udc->vbus = 0;
2916 vbus_work(udc);
2917
2918
2919 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2920 ISP1301_I2C_INTERRUPT_FALLING, INT_SESS_VLD | INT_VBUS_VLD);
2921 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2922 ISP1301_I2C_INTERRUPT_RISING, INT_SESS_VLD | INT_VBUS_VLD);
2923
2924 return 0;
2925}
2926
2927static int lpc32xx_stop(struct usb_gadget *gadget)
2928{
2929 struct lpc32xx_udc *udc = to_udc(gadget);
2930
2931 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2932 ISP1301_I2C_INTERRUPT_FALLING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2933 i2c_smbus_write_byte_data(udc->isp1301_i2c_client,
2934 ISP1301_I2C_INTERRUPT_RISING | ISP1301_I2C_REG_CLEAR_ADDR, ~0);
2935
2936 if (udc->clocked) {
2937 spin_lock(&udc->lock);
2938 stop_activity(udc);
2939 spin_unlock(&udc->lock);
2940
2941
2942
2943
2944
2945
2946 if (atomic_read(&udc->enabled_ep_cnt))
2947 wait_event_interruptible(udc->ep_disable_wait_queue,
2948 (atomic_read(&udc->enabled_ep_cnt) == 0));
2949
2950 spin_lock(&udc->lock);
2951 udc_clk_set(udc, 0);
2952 spin_unlock(&udc->lock);
2953 }
2954
2955 udc->enabled = 0;
2956 udc->driver = NULL;
2957
2958 return 0;
2959}
2960
2961static void lpc32xx_udc_shutdown(struct platform_device *dev)
2962{
2963
2964 struct lpc32xx_udc *udc = platform_get_drvdata(dev);
2965
2966 pullup(udc, 0);
2967}
2968
2969
2970
2971
2972
2973static void lpc32xx_usbd_conn_chg(int conn)
2974{
2975
2976
2977}
2978
2979static void lpc32xx_usbd_susp_chg(int susp)
2980{
2981
2982}
2983
2984static void lpc32xx_rmwkup_chg(int remote_wakup_enable)
2985{
2986
2987}
2988
2989static struct lpc32xx_usbd_cfg lpc32xx_usbddata = {
2990 .vbus_drv_pol = 0,
2991 .conn_chgb = &lpc32xx_usbd_conn_chg,
2992 .susp_chgb = &lpc32xx_usbd_susp_chg,
2993 .rmwk_chgb = &lpc32xx_rmwkup_chg,
2994};
2995
2996
2997static u64 lpc32xx_usbd_dmamask = ~(u32) 0x7F;
2998
2999static int lpc32xx_udc_probe(struct platform_device *pdev)
3000{
3001 struct device *dev = &pdev->dev;
3002 struct lpc32xx_udc *udc;
3003 int retval, i;
3004 dma_addr_t dma_handle;
3005 struct device_node *isp1301_node;
3006
3007 udc = devm_kmemdup(dev, &controller_template, sizeof(*udc), GFP_KERNEL);
3008 if (!udc)
3009 return -ENOMEM;
3010
3011 for (i = 0; i <= 15; i++)
3012 udc->ep[i].udc = udc;
3013 udc->gadget.ep0 = &udc->ep[0].ep;
3014
3015
3016 udc->gadget.dev.parent = dev;
3017 udc->pdev = pdev;
3018 udc->dev = &pdev->dev;
3019 udc->enabled = 0;
3020
3021 if (pdev->dev.of_node) {
3022 isp1301_node = of_parse_phandle(pdev->dev.of_node,
3023 "transceiver", 0);
3024 } else {
3025 isp1301_node = NULL;
3026 }
3027
3028 udc->isp1301_i2c_client = isp1301_get_client(isp1301_node);
3029 if (!udc->isp1301_i2c_client) {
3030 return -EPROBE_DEFER;
3031 }
3032
3033 dev_info(udc->dev, "ISP1301 I2C device at address 0x%x\n",
3034 udc->isp1301_i2c_client->addr);
3035
3036 pdev->dev.dma_mask = &lpc32xx_usbd_dmamask;
3037 retval = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
3038 if (retval)
3039 return retval;
3040
3041 udc->board = &lpc32xx_usbddata;
3042
3043
3044
3045
3046
3047
3048
3049
3050
3051
3052 spin_lock_init(&udc->lock);
3053
3054
3055 for (i = 0; i < 4; i++) {
3056 udc->udp_irq[i] = platform_get_irq(pdev, i);
3057 if (udc->udp_irq[i] < 0)
3058 return udc->udp_irq[i];
3059 }
3060
3061 udc->udp_baseaddr = devm_platform_ioremap_resource(pdev, 0);
3062 if (IS_ERR(udc->udp_baseaddr)) {
3063 dev_err(udc->dev, "IO map failure\n");
3064 return PTR_ERR(udc->udp_baseaddr);
3065 }
3066
3067
3068 udc->usb_slv_clk = devm_clk_get(&pdev->dev, NULL);
3069 if (IS_ERR(udc->usb_slv_clk)) {
3070 dev_err(udc->dev, "failed to acquire USB device clock\n");
3071 return PTR_ERR(udc->usb_slv_clk);
3072 }
3073
3074
3075 retval = clk_prepare_enable(udc->usb_slv_clk);
3076 if (retval < 0) {
3077 dev_err(udc->dev, "failed to start USB device clock\n");
3078 return retval;
3079 }
3080
3081
3082 udc->poweron = udc->pullup = 0;
3083 INIT_WORK(&udc->pullup_job, pullup_work);
3084#ifdef CONFIG_PM
3085 INIT_WORK(&udc->power_job, power_work);
3086#endif
3087
3088
3089 udc->clocked = 1;
3090
3091 isp1301_udc_configure(udc);
3092
3093 udc->udca_v_base = dma_alloc_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3094 &dma_handle,
3095 (GFP_KERNEL | GFP_DMA));
3096 if (!udc->udca_v_base) {
3097 dev_err(udc->dev, "error getting UDCA region\n");
3098 retval = -ENOMEM;
3099 goto i2c_fail;
3100 }
3101 udc->udca_p_base = dma_handle;
3102 dev_dbg(udc->dev, "DMA buffer(0x%x bytes), P:0x%08x, V:0x%p\n",
3103 UDCA_BUFF_SIZE, udc->udca_p_base, udc->udca_v_base);
3104
3105
3106 udc->dd_cache = dma_pool_create("udc_dd", udc->dev,
3107 sizeof(struct lpc32xx_usbd_dd_gad),
3108 sizeof(u32), 0);
3109 if (!udc->dd_cache) {
3110 dev_err(udc->dev, "error getting DD DMA region\n");
3111 retval = -ENOMEM;
3112 goto dma_alloc_fail;
3113 }
3114
3115
3116 udc_disable(udc);
3117 udc_reinit(udc);
3118
3119
3120
3121 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_LP],
3122 lpc32xx_usb_lp_irq, 0, "udc_lp", udc);
3123 if (retval < 0) {
3124 dev_err(udc->dev, "LP request irq %d failed\n",
3125 udc->udp_irq[IRQ_USB_LP]);
3126 goto irq_req_fail;
3127 }
3128 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_HP],
3129 lpc32xx_usb_hp_irq, 0, "udc_hp", udc);
3130 if (retval < 0) {
3131 dev_err(udc->dev, "HP request irq %d failed\n",
3132 udc->udp_irq[IRQ_USB_HP]);
3133 goto irq_req_fail;
3134 }
3135
3136 retval = devm_request_irq(dev, udc->udp_irq[IRQ_USB_DEVDMA],
3137 lpc32xx_usb_devdma_irq, 0, "udc_dma", udc);
3138 if (retval < 0) {
3139 dev_err(udc->dev, "DEV request irq %d failed\n",
3140 udc->udp_irq[IRQ_USB_DEVDMA]);
3141 goto irq_req_fail;
3142 }
3143
3144
3145
3146 retval = devm_request_threaded_irq(dev, udc->udp_irq[IRQ_USB_ATX], NULL,
3147 lpc32xx_usb_vbus_irq, IRQF_ONESHOT,
3148 "udc_otg", udc);
3149 if (retval < 0) {
3150 dev_err(udc->dev, "VBUS request irq %d failed\n",
3151 udc->udp_irq[IRQ_USB_ATX]);
3152 goto irq_req_fail;
3153 }
3154
3155
3156 init_waitqueue_head(&udc->ep_disable_wait_queue);
3157 atomic_set(&udc->enabled_ep_cnt, 0);
3158
3159 retval = usb_add_gadget_udc(dev, &udc->gadget);
3160 if (retval < 0)
3161 goto add_gadget_fail;
3162
3163 dev_set_drvdata(dev, udc);
3164 device_init_wakeup(dev, 1);
3165 create_debug_file(udc);
3166
3167
3168 udc_clk_set(udc, 0);
3169
3170 dev_info(udc->dev, "%s version %s\n", driver_name, DRIVER_VERSION);
3171 return 0;
3172
3173add_gadget_fail:
3174irq_req_fail:
3175 dma_pool_destroy(udc->dd_cache);
3176dma_alloc_fail:
3177 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3178 udc->udca_v_base, udc->udca_p_base);
3179i2c_fail:
3180 clk_disable_unprepare(udc->usb_slv_clk);
3181 dev_err(udc->dev, "%s probe failed, %d\n", driver_name, retval);
3182
3183 return retval;
3184}
3185
3186static int lpc32xx_udc_remove(struct platform_device *pdev)
3187{
3188 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3189
3190 usb_del_gadget_udc(&udc->gadget);
3191 if (udc->driver)
3192 return -EBUSY;
3193
3194 udc_clk_set(udc, 1);
3195 udc_disable(udc);
3196 pullup(udc, 0);
3197
3198 device_init_wakeup(&pdev->dev, 0);
3199 remove_debug_file(udc);
3200
3201 dma_pool_destroy(udc->dd_cache);
3202 dma_free_coherent(&pdev->dev, UDCA_BUFF_SIZE,
3203 udc->udca_v_base, udc->udca_p_base);
3204
3205 clk_disable_unprepare(udc->usb_slv_clk);
3206
3207 return 0;
3208}
3209
3210#ifdef CONFIG_PM
3211static int lpc32xx_udc_suspend(struct platform_device *pdev, pm_message_t mesg)
3212{
3213 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3214
3215 if (udc->clocked) {
3216
3217 udc->poweron = 0;
3218 isp1301_set_powerstate(udc, 0);
3219
3220
3221 udc_clk_set(udc, 0);
3222
3223
3224
3225 udc->clocked = 1;
3226
3227
3228 clk_disable_unprepare(udc->usb_slv_clk);
3229 }
3230
3231 return 0;
3232}
3233
3234static int lpc32xx_udc_resume(struct platform_device *pdev)
3235{
3236 struct lpc32xx_udc *udc = platform_get_drvdata(pdev);
3237
3238 if (udc->clocked) {
3239
3240 clk_prepare_enable(udc->usb_slv_clk);
3241
3242
3243 udc_clk_set(udc, 1);
3244
3245
3246 udc->poweron = 1;
3247 isp1301_set_powerstate(udc, 1);
3248 }
3249
3250 return 0;
3251}
3252#else
3253#define lpc32xx_udc_suspend NULL
3254#define lpc32xx_udc_resume NULL
3255#endif
3256
3257#ifdef CONFIG_OF
3258static const struct of_device_id lpc32xx_udc_of_match[] = {
3259 { .compatible = "nxp,lpc3220-udc", },
3260 { },
3261};
3262MODULE_DEVICE_TABLE(of, lpc32xx_udc_of_match);
3263#endif
3264
3265static struct platform_driver lpc32xx_udc_driver = {
3266 .remove = lpc32xx_udc_remove,
3267 .shutdown = lpc32xx_udc_shutdown,
3268 .suspend = lpc32xx_udc_suspend,
3269 .resume = lpc32xx_udc_resume,
3270 .driver = {
3271 .name = driver_name,
3272 .of_match_table = of_match_ptr(lpc32xx_udc_of_match),
3273 },
3274};
3275
3276module_platform_driver_probe(lpc32xx_udc_driver, lpc32xx_udc_probe);
3277
3278MODULE_DESCRIPTION("LPC32XX udc driver");
3279MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>");
3280MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>");
3281MODULE_LICENSE("GPL");
3282MODULE_ALIAS("platform:lpc32xx_udc");
3283