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10#ifndef __ACTBL2_H__
11#define __ACTBL2_H__
12
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25
26
27#define ACPI_SIG_IORT "IORT"
28#define ACPI_SIG_IVRS "IVRS"
29#define ACPI_SIG_LPIT "LPIT"
30#define ACPI_SIG_MADT "APIC"
31#define ACPI_SIG_MCFG "MCFG"
32#define ACPI_SIG_MCHI "MCHI"
33#define ACPI_SIG_MPST "MPST"
34#define ACPI_SIG_MSCT "MSCT"
35#define ACPI_SIG_MSDM "MSDM"
36#define ACPI_SIG_MTMR "MTMR"
37#define ACPI_SIG_NFIT "NFIT"
38#define ACPI_SIG_PCCT "PCCT"
39#define ACPI_SIG_PDTT "PDTT"
40#define ACPI_SIG_PMTT "PMTT"
41#define ACPI_SIG_PPTT "PPTT"
42#define ACPI_SIG_RASF "RASF"
43#define ACPI_SIG_SBST "SBST"
44#define ACPI_SIG_SDEI "SDEI"
45#define ACPI_SIG_SDEV "SDEV"
46#define ACPI_SIG_NHLT "NHLT"
47
48
49
50
51
52#pragma pack(1)
53
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74
75struct acpi_table_iort {
76 struct acpi_table_header header;
77 u32 node_count;
78 u32 node_offset;
79 u32 reserved;
80};
81
82
83
84
85struct acpi_iort_node {
86 u8 type;
87 u16 length;
88 u8 revision;
89 u32 reserved;
90 u32 mapping_count;
91 u32 mapping_offset;
92 char node_data[1];
93};
94
95
96
97enum acpi_iort_node_type {
98 ACPI_IORT_NODE_ITS_GROUP = 0x00,
99 ACPI_IORT_NODE_NAMED_COMPONENT = 0x01,
100 ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02,
101 ACPI_IORT_NODE_SMMU = 0x03,
102 ACPI_IORT_NODE_SMMU_V3 = 0x04,
103 ACPI_IORT_NODE_PMCG = 0x05
104};
105
106struct acpi_iort_id_mapping {
107 u32 input_base;
108 u32 id_count;
109 u32 output_base;
110 u32 output_reference;
111 u32 flags;
112};
113
114
115
116#define ACPI_IORT_ID_SINGLE_MAPPING (1)
117
118struct acpi_iort_memory_access {
119 u32 cache_coherency;
120 u8 hints;
121 u16 reserved;
122 u8 memory_flags;
123};
124
125
126
127#define ACPI_IORT_NODE_COHERENT 0x00000001
128#define ACPI_IORT_NODE_NOT_COHERENT 0x00000000
129
130
131
132#define ACPI_IORT_HT_TRANSIENT (1)
133#define ACPI_IORT_HT_WRITE (1<<1)
134#define ACPI_IORT_HT_READ (1<<2)
135#define ACPI_IORT_HT_OVERRIDE (1<<3)
136
137
138
139#define ACPI_IORT_MF_COHERENCY (1)
140#define ACPI_IORT_MF_ATTRIBUTES (1<<1)
141
142
143
144
145struct acpi_iort_its_group {
146 u32 its_count;
147 u32 identifiers[1];
148};
149
150struct acpi_iort_named_component {
151 u32 node_flags;
152 u64 memory_properties;
153 u8 memory_address_limit;
154 char device_name[1];
155};
156
157
158
159#define ACPI_IORT_NC_STALL_SUPPORTED (1)
160#define ACPI_IORT_NC_PASID_BITS (31<<1)
161
162struct acpi_iort_root_complex {
163 u64 memory_properties;
164 u32 ats_attribute;
165 u32 pci_segment_number;
166 u8 memory_address_limit;
167 u8 reserved[3];
168};
169
170
171
172#define ACPI_IORT_ATS_SUPPORTED 0x00000001
173#define ACPI_IORT_ATS_UNSUPPORTED 0x00000000
174
175struct acpi_iort_smmu {
176 u64 base_address;
177 u64 span;
178 u32 model;
179 u32 flags;
180 u32 global_interrupt_offset;
181 u32 context_interrupt_count;
182 u32 context_interrupt_offset;
183 u32 pmu_interrupt_count;
184 u32 pmu_interrupt_offset;
185 u64 interrupts[1];
186};
187
188
189
190#define ACPI_IORT_SMMU_V1 0x00000000
191#define ACPI_IORT_SMMU_V2 0x00000001
192#define ACPI_IORT_SMMU_CORELINK_MMU400 0x00000002
193#define ACPI_IORT_SMMU_CORELINK_MMU500 0x00000003
194#define ACPI_IORT_SMMU_CORELINK_MMU401 0x00000004
195#define ACPI_IORT_SMMU_CAVIUM_THUNDERX 0x00000005
196
197
198
199#define ACPI_IORT_SMMU_DVM_SUPPORTED (1)
200#define ACPI_IORT_SMMU_COHERENT_WALK (1<<1)
201
202
203
204struct acpi_iort_smmu_gsi {
205 u32 nsg_irpt;
206 u32 nsg_irpt_flags;
207 u32 nsg_cfg_irpt;
208 u32 nsg_cfg_irpt_flags;
209};
210
211struct acpi_iort_smmu_v3 {
212 u64 base_address;
213 u32 flags;
214 u32 reserved;
215 u64 vatos_address;
216 u32 model;
217 u32 event_gsiv;
218 u32 pri_gsiv;
219 u32 gerr_gsiv;
220 u32 sync_gsiv;
221 u32 pxm;
222 u32 id_mapping_index;
223};
224
225
226
227#define ACPI_IORT_SMMU_V3_GENERIC 0x00000000
228#define ACPI_IORT_SMMU_V3_HISILICON_HI161X 0x00000001
229#define ACPI_IORT_SMMU_V3_CAVIUM_CN99XX 0x00000002
230
231
232
233#define ACPI_IORT_SMMU_V3_COHACC_OVERRIDE (1)
234#define ACPI_IORT_SMMU_V3_HTTU_OVERRIDE (3<<1)
235#define ACPI_IORT_SMMU_V3_PXM_VALID (1<<3)
236
237struct acpi_iort_pmcg {
238 u64 page0_base_address;
239 u32 overflow_gsiv;
240 u32 node_reference;
241 u64 page1_base_address;
242};
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252
253
254struct acpi_table_ivrs {
255 struct acpi_table_header header;
256 u32 info;
257 u64 reserved;
258};
259
260
261
262#define ACPI_IVRS_PHYSICAL_SIZE 0x00007F00
263#define ACPI_IVRS_VIRTUAL_SIZE 0x003F8000
264#define ACPI_IVRS_ATS_RESERVED 0x00400000
265
266
267
268struct acpi_ivrs_header {
269 u8 type;
270 u8 flags;
271 u16 length;
272 u16 device_id;
273};
274
275
276
277enum acpi_ivrs_type {
278 ACPI_IVRS_TYPE_HARDWARE1 = 0x10,
279 ACPI_IVRS_TYPE_HARDWARE2 = 0x11,
280 ACPI_IVRS_TYPE_MEMORY1 = 0x20,
281 ACPI_IVRS_TYPE_MEMORY2 = 0x21,
282 ACPI_IVRS_TYPE_MEMORY3 = 0x22
283};
284
285
286
287#define ACPI_IVHD_TT_ENABLE (1)
288#define ACPI_IVHD_PASS_PW (1<<1)
289#define ACPI_IVHD_RES_PASS_PW (1<<2)
290#define ACPI_IVHD_ISOC (1<<3)
291#define ACPI_IVHD_IOTLB (1<<4)
292
293
294
295#define ACPI_IVMD_UNITY (1)
296#define ACPI_IVMD_READ (1<<1)
297#define ACPI_IVMD_WRITE (1<<2)
298#define ACPI_IVMD_EXCLUSION_RANGE (1<<3)
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304
305
306struct acpi_ivrs_hardware_10 {
307 struct acpi_ivrs_header header;
308 u16 capability_offset;
309 u64 base_address;
310 u16 pci_segment_group;
311 u16 info;
312 u32 feature_reporting;
313};
314
315
316
317struct acpi_ivrs_hardware_11 {
318 struct acpi_ivrs_header header;
319 u16 capability_offset;
320 u64 base_address;
321 u16 pci_segment_group;
322 u16 info;
323 u32 attributes;
324 u64 efr_register_image;
325 u64 reserved;
326};
327
328
329
330#define ACPI_IVHD_MSI_NUMBER_MASK 0x001F
331#define ACPI_IVHD_UNIT_ID_MASK 0x1F00
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336
337
338
339struct acpi_ivrs_de_header {
340 u8 type;
341 u16 id;
342 u8 data_setting;
343};
344
345
346
347#define ACPI_IVHD_ENTRY_LENGTH 0xC0
348
349
350
351enum acpi_ivrs_device_entry_type {
352
353
354 ACPI_IVRS_TYPE_PAD4 = 0,
355 ACPI_IVRS_TYPE_ALL = 1,
356 ACPI_IVRS_TYPE_SELECT = 2,
357 ACPI_IVRS_TYPE_START = 3,
358 ACPI_IVRS_TYPE_END = 4,
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360
361
362 ACPI_IVRS_TYPE_PAD8 = 64,
363 ACPI_IVRS_TYPE_NOT_USED = 65,
364 ACPI_IVRS_TYPE_ALIAS_SELECT = 66,
365 ACPI_IVRS_TYPE_ALIAS_START = 67,
366 ACPI_IVRS_TYPE_EXT_SELECT = 70,
367 ACPI_IVRS_TYPE_EXT_START = 71,
368 ACPI_IVRS_TYPE_SPECIAL = 72
369};
370
371
372
373#define ACPI_IVHD_INIT_PASS (1)
374#define ACPI_IVHD_EINT_PASS (1<<1)
375#define ACPI_IVHD_NMI_PASS (1<<2)
376#define ACPI_IVHD_SYSTEM_MGMT (3<<4)
377#define ACPI_IVHD_LINT0_PASS (1<<6)
378#define ACPI_IVHD_LINT1_PASS (1<<7)
379
380
381
382struct acpi_ivrs_device4 {
383 struct acpi_ivrs_de_header header;
384};
385
386
387
388struct acpi_ivrs_device8a {
389 struct acpi_ivrs_de_header header;
390 u8 reserved1;
391 u16 used_id;
392 u8 reserved2;
393};
394
395
396
397struct acpi_ivrs_device8b {
398 struct acpi_ivrs_de_header header;
399 u32 extended_data;
400};
401
402
403
404#define ACPI_IVHD_ATS_DISABLED (1<<31)
405
406
407
408struct acpi_ivrs_device8c {
409 struct acpi_ivrs_de_header header;
410 u8 handle;
411 u16 used_id;
412 u8 variety;
413};
414
415
416
417#define ACPI_IVHD_IOAPIC 1
418#define ACPI_IVHD_HPET 2
419
420
421
422struct acpi_ivrs_memory {
423 struct acpi_ivrs_header header;
424 u16 aux_data;
425 u64 reserved;
426 u64 start_address;
427 u64 memory_length;
428};
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437
438struct acpi_table_lpit {
439 struct acpi_table_header header;
440};
441
442
443
444struct acpi_lpit_header {
445 u32 type;
446 u32 length;
447 u16 unique_id;
448 u16 reserved;
449 u32 flags;
450};
451
452
453
454enum acpi_lpit_type {
455 ACPI_LPIT_TYPE_NATIVE_CSTATE = 0x00,
456 ACPI_LPIT_TYPE_RESERVED = 0x01
457};
458
459
460
461#define ACPI_LPIT_STATE_DISABLED (1)
462#define ACPI_LPIT_NO_COUNTER (1<<1)
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469
470struct acpi_lpit_native {
471 struct acpi_lpit_header header;
472 struct acpi_generic_address entry_trigger;
473 u32 residency;
474 u32 latency;
475 struct acpi_generic_address residency_counter;
476 u64 counter_frequency;
477};
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484
485
486struct acpi_table_madt {
487 struct acpi_table_header header;
488 u32 address;
489 u32 flags;
490};
491
492
493
494#define ACPI_MADT_PCAT_COMPAT (1)
495
496
497
498#define ACPI_MADT_DUAL_PIC 1
499#define ACPI_MADT_MULTIPLE_APIC 0
500
501
502
503enum acpi_madt_type {
504 ACPI_MADT_TYPE_LOCAL_APIC = 0,
505 ACPI_MADT_TYPE_IO_APIC = 1,
506 ACPI_MADT_TYPE_INTERRUPT_OVERRIDE = 2,
507 ACPI_MADT_TYPE_NMI_SOURCE = 3,
508 ACPI_MADT_TYPE_LOCAL_APIC_NMI = 4,
509 ACPI_MADT_TYPE_LOCAL_APIC_OVERRIDE = 5,
510 ACPI_MADT_TYPE_IO_SAPIC = 6,
511 ACPI_MADT_TYPE_LOCAL_SAPIC = 7,
512 ACPI_MADT_TYPE_INTERRUPT_SOURCE = 8,
513 ACPI_MADT_TYPE_LOCAL_X2APIC = 9,
514 ACPI_MADT_TYPE_LOCAL_X2APIC_NMI = 10,
515 ACPI_MADT_TYPE_GENERIC_INTERRUPT = 11,
516 ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR = 12,
517 ACPI_MADT_TYPE_GENERIC_MSI_FRAME = 13,
518 ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR = 14,
519 ACPI_MADT_TYPE_GENERIC_TRANSLATOR = 15,
520 ACPI_MADT_TYPE_RESERVED = 16
521};
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529struct acpi_madt_local_apic {
530 struct acpi_subtable_header header;
531 u8 processor_id;
532 u8 id;
533 u32 lapic_flags;
534};
535
536
537
538struct acpi_madt_io_apic {
539 struct acpi_subtable_header header;
540 u8 id;
541 u8 reserved;
542 u32 address;
543 u32 global_irq_base;
544};
545
546
547
548struct acpi_madt_interrupt_override {
549 struct acpi_subtable_header header;
550 u8 bus;
551 u8 source_irq;
552 u32 global_irq;
553 u16 inti_flags;
554};
555
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557
558struct acpi_madt_nmi_source {
559 struct acpi_subtable_header header;
560 u16 inti_flags;
561 u32 global_irq;
562};
563
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566struct acpi_madt_local_apic_nmi {
567 struct acpi_subtable_header header;
568 u8 processor_id;
569 u16 inti_flags;
570 u8 lint;
571};
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574
575struct acpi_madt_local_apic_override {
576 struct acpi_subtable_header header;
577 u16 reserved;
578 u64 address;
579};
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582
583struct acpi_madt_io_sapic {
584 struct acpi_subtable_header header;
585 u8 id;
586 u8 reserved;
587 u32 global_irq_base;
588 u64 address;
589};
590
591
592
593struct acpi_madt_local_sapic {
594 struct acpi_subtable_header header;
595 u8 processor_id;
596 u8 id;
597 u8 eid;
598 u8 reserved[3];
599 u32 lapic_flags;
600 u32 uid;
601 char uid_string[1];
602};
603
604
605
606struct acpi_madt_interrupt_source {
607 struct acpi_subtable_header header;
608 u16 inti_flags;
609 u8 type;
610 u8 id;
611 u8 eid;
612 u8 io_sapic_vector;
613 u32 global_irq;
614 u32 flags;
615};
616
617
618
619#define ACPI_MADT_CPEI_OVERRIDE (1)
620
621
622
623struct acpi_madt_local_x2apic {
624 struct acpi_subtable_header header;
625 u16 reserved;
626 u32 local_apic_id;
627 u32 lapic_flags;
628 u32 uid;
629};
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631
632
633struct acpi_madt_local_x2apic_nmi {
634 struct acpi_subtable_header header;
635 u16 inti_flags;
636 u32 uid;
637 u8 lint;
638 u8 reserved[3];
639};
640
641
642
643struct acpi_madt_generic_interrupt {
644 struct acpi_subtable_header header;
645 u16 reserved;
646 u32 cpu_interface_number;
647 u32 uid;
648 u32 flags;
649 u32 parking_version;
650 u32 performance_interrupt;
651 u64 parked_address;
652 u64 base_address;
653 u64 gicv_base_address;
654 u64 gich_base_address;
655 u32 vgic_interrupt;
656 u64 gicr_base_address;
657 u64 arm_mpidr;
658 u8 efficiency_class;
659 u8 reserved2[1];
660 u16 spe_interrupt;
661};
662
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664
665
666#define ACPI_MADT_PERFORMANCE_IRQ_MODE (1<<1)
667#define ACPI_MADT_VGIC_IRQ_MODE (1<<2)
668
669
670
671struct acpi_madt_generic_distributor {
672 struct acpi_subtable_header header;
673 u16 reserved;
674 u32 gic_id;
675 u64 base_address;
676 u32 global_irq_base;
677 u8 version;
678 u8 reserved2[3];
679};
680
681
682
683enum acpi_madt_gic_version {
684 ACPI_MADT_GIC_VERSION_NONE = 0,
685 ACPI_MADT_GIC_VERSION_V1 = 1,
686 ACPI_MADT_GIC_VERSION_V2 = 2,
687 ACPI_MADT_GIC_VERSION_V3 = 3,
688 ACPI_MADT_GIC_VERSION_V4 = 4,
689 ACPI_MADT_GIC_VERSION_RESERVED = 5
690};
691
692
693
694struct acpi_madt_generic_msi_frame {
695 struct acpi_subtable_header header;
696 u16 reserved;
697 u32 msi_frame_id;
698 u64 base_address;
699 u32 flags;
700 u16 spi_count;
701 u16 spi_base;
702};
703
704
705
706#define ACPI_MADT_OVERRIDE_SPI_VALUES (1)
707
708
709
710struct acpi_madt_generic_redistributor {
711 struct acpi_subtable_header header;
712 u16 reserved;
713 u64 base_address;
714 u32 length;
715};
716
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718
719struct acpi_madt_generic_translator {
720 struct acpi_subtable_header header;
721 u16 reserved;
722 u32 translation_id;
723 u64 base_address;
724 u32 reserved2;
725};
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731
732
733#define ACPI_MADT_ENABLED (1)
734
735
736
737#define ACPI_MADT_POLARITY_MASK (3)
738#define ACPI_MADT_TRIGGER_MASK (3<<2)
739
740
741
742#define ACPI_MADT_POLARITY_CONFORMS 0
743#define ACPI_MADT_POLARITY_ACTIVE_HIGH 1
744#define ACPI_MADT_POLARITY_RESERVED 2
745#define ACPI_MADT_POLARITY_ACTIVE_LOW 3
746
747#define ACPI_MADT_TRIGGER_CONFORMS (0)
748#define ACPI_MADT_TRIGGER_EDGE (1<<2)
749#define ACPI_MADT_TRIGGER_RESERVED (2<<2)
750#define ACPI_MADT_TRIGGER_LEVEL (3<<2)
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760
761struct acpi_table_mcfg {
762 struct acpi_table_header header;
763 u8 reserved[8];
764};
765
766
767
768struct acpi_mcfg_allocation {
769 u64 address;
770 u16 pci_segment;
771 u8 start_bus_number;
772 u8 end_bus_number;
773 u32 reserved;
774};
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784
785
786struct acpi_table_mchi {
787 struct acpi_table_header header;
788 u8 interface_type;
789 u8 protocol;
790 u64 protocol_data;
791 u8 interrupt_type;
792 u8 gpe;
793 u8 pci_device_flag;
794 u32 global_interrupt;
795 struct acpi_generic_address control_register;
796 u8 pci_segment;
797 u8 pci_bus;
798 u8 pci_device;
799 u8 pci_function;
800};
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808
809#define ACPI_MPST_CHANNEL_INFO \
810 u8 channel_id; \
811 u8 reserved1[3]; \
812 u16 power_node_count; \
813 u16 reserved2;
814
815
816
817struct acpi_table_mpst {
818 struct acpi_table_header header;
819 ACPI_MPST_CHANNEL_INFO
820};
821
822
823
824struct acpi_mpst_channel {
825 ACPI_MPST_CHANNEL_INFO
826};
827
828
829
830struct acpi_mpst_power_node {
831 u8 flags;
832 u8 reserved1;
833 u16 node_id;
834 u32 length;
835 u64 range_address;
836 u64 range_length;
837 u32 num_power_states;
838 u32 num_physical_components;
839};
840
841
842
843#define ACPI_MPST_ENABLED 1
844#define ACPI_MPST_POWER_MANAGED 2
845#define ACPI_MPST_HOT_PLUG_CAPABLE 4
846
847
848
849struct acpi_mpst_power_state {
850 u8 power_state;
851 u8 info_index;
852};
853
854
855
856struct acpi_mpst_component {
857 u16 component_id;
858};
859
860
861
862struct acpi_mpst_data_hdr {
863 u16 characteristics_count;
864 u16 reserved;
865};
866
867struct acpi_mpst_power_data {
868 u8 structure_id;
869 u8 flags;
870 u16 reserved1;
871 u32 average_power;
872 u32 power_saving;
873 u64 exit_latency;
874 u64 reserved2;
875};
876
877
878
879#define ACPI_MPST_PRESERVE 1
880#define ACPI_MPST_AUTOENTRY 2
881#define ACPI_MPST_AUTOEXIT 4
882
883
884
885struct acpi_mpst_shared {
886 u32 signature;
887 u16 pcc_command;
888 u16 pcc_status;
889 u32 command_register;
890 u32 status_register;
891 u32 power_state_id;
892 u32 power_node_id;
893 u64 energy_consumed;
894 u64 average_power;
895};
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902
903
904struct acpi_table_msct {
905 struct acpi_table_header header;
906 u32 proximity_offset;
907 u32 max_proximity_domains;
908 u32 max_clock_domains;
909 u64 max_address;
910};
911
912
913
914struct acpi_msct_proximity {
915 u8 revision;
916 u8 length;
917 u32 range_start;
918 u32 range_end;
919 u32 processor_capacity;
920 u64 memory_capacity;
921};
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933
934struct acpi_table_msdm {
935 struct acpi_table_header header;
936};
937
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948
949struct acpi_table_mtmr {
950 struct acpi_table_header header;
951};
952
953
954
955struct acpi_mtmr_entry {
956 struct acpi_generic_address physical_address;
957 u32 frequency;
958 u32 irq;
959};
960
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965
966
967
968struct acpi_table_nfit {
969 struct acpi_table_header header;
970 u32 reserved;
971};
972
973
974
975struct acpi_nfit_header {
976 u16 type;
977 u16 length;
978};
979
980
981
982enum acpi_nfit_type {
983 ACPI_NFIT_TYPE_SYSTEM_ADDRESS = 0,
984 ACPI_NFIT_TYPE_MEMORY_MAP = 1,
985 ACPI_NFIT_TYPE_INTERLEAVE = 2,
986 ACPI_NFIT_TYPE_SMBIOS = 3,
987 ACPI_NFIT_TYPE_CONTROL_REGION = 4,
988 ACPI_NFIT_TYPE_DATA_REGION = 5,
989 ACPI_NFIT_TYPE_FLUSH_ADDRESS = 6,
990 ACPI_NFIT_TYPE_CAPABILITIES = 7,
991 ACPI_NFIT_TYPE_RESERVED = 8
992};
993
994
995
996
997
998
999
1000struct acpi_nfit_system_address {
1001 struct acpi_nfit_header header;
1002 u16 range_index;
1003 u16 flags;
1004 u32 reserved;
1005 u32 proximity_domain;
1006 u8 range_guid[16];
1007 u64 address;
1008 u64 length;
1009 u64 memory_mapping;
1010};
1011
1012
1013
1014#define ACPI_NFIT_ADD_ONLINE_ONLY (1)
1015#define ACPI_NFIT_PROXIMITY_VALID (1<<1)
1016
1017
1018
1019
1020
1021struct acpi_nfit_memory_map {
1022 struct acpi_nfit_header header;
1023 u32 device_handle;
1024 u16 physical_id;
1025 u16 region_id;
1026 u16 range_index;
1027 u16 region_index;
1028 u64 region_size;
1029 u64 region_offset;
1030 u64 address;
1031 u16 interleave_index;
1032 u16 interleave_ways;
1033 u16 flags;
1034 u16 reserved;
1035};
1036
1037
1038
1039#define ACPI_NFIT_MEM_SAVE_FAILED (1)
1040#define ACPI_NFIT_MEM_RESTORE_FAILED (1<<1)
1041#define ACPI_NFIT_MEM_FLUSH_FAILED (1<<2)
1042#define ACPI_NFIT_MEM_NOT_ARMED (1<<3)
1043#define ACPI_NFIT_MEM_HEALTH_OBSERVED (1<<4)
1044#define ACPI_NFIT_MEM_HEALTH_ENABLED (1<<5)
1045#define ACPI_NFIT_MEM_MAP_FAILED (1<<6)
1046
1047
1048
1049struct acpi_nfit_interleave {
1050 struct acpi_nfit_header header;
1051 u16 interleave_index;
1052 u16 reserved;
1053 u32 line_count;
1054 u32 line_size;
1055 u32 line_offset[1];
1056};
1057
1058
1059
1060struct acpi_nfit_smbios {
1061 struct acpi_nfit_header header;
1062 u32 reserved;
1063 u8 data[1];
1064};
1065
1066
1067
1068struct acpi_nfit_control_region {
1069 struct acpi_nfit_header header;
1070 u16 region_index;
1071 u16 vendor_id;
1072 u16 device_id;
1073 u16 revision_id;
1074 u16 subsystem_vendor_id;
1075 u16 subsystem_device_id;
1076 u16 subsystem_revision_id;
1077 u8 valid_fields;
1078 u8 manufacturing_location;
1079 u16 manufacturing_date;
1080 u8 reserved[2];
1081 u32 serial_number;
1082 u16 code;
1083 u16 windows;
1084 u64 window_size;
1085 u64 command_offset;
1086 u64 command_size;
1087 u64 status_offset;
1088 u64 status_size;
1089 u16 flags;
1090 u8 reserved1[6];
1091};
1092
1093
1094
1095#define ACPI_NFIT_CONTROL_BUFFERED (1)
1096
1097
1098
1099#define ACPI_NFIT_CONTROL_MFG_INFO_VALID (1)
1100
1101
1102
1103struct acpi_nfit_data_region {
1104 struct acpi_nfit_header header;
1105 u16 region_index;
1106 u16 windows;
1107 u64 offset;
1108 u64 size;
1109 u64 capacity;
1110 u64 start_address;
1111};
1112
1113
1114
1115struct acpi_nfit_flush_address {
1116 struct acpi_nfit_header header;
1117 u32 device_handle;
1118 u16 hint_count;
1119 u8 reserved[6];
1120 u64 hint_address[1];
1121};
1122
1123
1124
1125struct acpi_nfit_capabilities {
1126 struct acpi_nfit_header header;
1127 u8 highest_capability;
1128 u8 reserved[3];
1129 u32 capabilities;
1130 u32 reserved2;
1131};
1132
1133
1134
1135#define ACPI_NFIT_CAPABILITY_CACHE_FLUSH (1)
1136#define ACPI_NFIT_CAPABILITY_MEM_FLUSH (1<<1)
1137#define ACPI_NFIT_CAPABILITY_MEM_MIRRORING (1<<2)
1138
1139
1140
1141
1142struct nfit_device_handle {
1143 u32 handle;
1144};
1145
1146
1147
1148#define ACPI_NFIT_DIMM_NUMBER_MASK 0x0000000F
1149#define ACPI_NFIT_CHANNEL_NUMBER_MASK 0x000000F0
1150#define ACPI_NFIT_MEMORY_ID_MASK 0x00000F00
1151#define ACPI_NFIT_SOCKET_ID_MASK 0x0000F000
1152#define ACPI_NFIT_NODE_ID_MASK 0x0FFF0000
1153
1154#define ACPI_NFIT_DIMM_NUMBER_OFFSET 0
1155#define ACPI_NFIT_CHANNEL_NUMBER_OFFSET 4
1156#define ACPI_NFIT_MEMORY_ID_OFFSET 8
1157#define ACPI_NFIT_SOCKET_ID_OFFSET 12
1158#define ACPI_NFIT_NODE_ID_OFFSET 16
1159
1160
1161
1162#define ACPI_NFIT_BUILD_DEVICE_HANDLE(dimm, channel, memory, socket, node) \
1163 ((dimm) | \
1164 ((channel) << ACPI_NFIT_CHANNEL_NUMBER_OFFSET) | \
1165 ((memory) << ACPI_NFIT_MEMORY_ID_OFFSET) | \
1166 ((socket) << ACPI_NFIT_SOCKET_ID_OFFSET) | \
1167 ((node) << ACPI_NFIT_NODE_ID_OFFSET))
1168
1169
1170
1171#define ACPI_NFIT_GET_DIMM_NUMBER(handle) \
1172 ((handle) & ACPI_NFIT_DIMM_NUMBER_MASK)
1173
1174#define ACPI_NFIT_GET_CHANNEL_NUMBER(handle) \
1175 (((handle) & ACPI_NFIT_CHANNEL_NUMBER_MASK) >> ACPI_NFIT_CHANNEL_NUMBER_OFFSET)
1176
1177#define ACPI_NFIT_GET_MEMORY_ID(handle) \
1178 (((handle) & ACPI_NFIT_MEMORY_ID_MASK) >> ACPI_NFIT_MEMORY_ID_OFFSET)
1179
1180#define ACPI_NFIT_GET_SOCKET_ID(handle) \
1181 (((handle) & ACPI_NFIT_SOCKET_ID_MASK) >> ACPI_NFIT_SOCKET_ID_OFFSET)
1182
1183#define ACPI_NFIT_GET_NODE_ID(handle) \
1184 (((handle) & ACPI_NFIT_NODE_ID_MASK) >> ACPI_NFIT_NODE_ID_OFFSET)
1185
1186
1187
1188
1189
1190
1191
1192
1193struct acpi_table_pcct {
1194 struct acpi_table_header header;
1195 u32 flags;
1196 u64 reserved;
1197};
1198
1199
1200
1201#define ACPI_PCCT_DOORBELL 1
1202
1203
1204
1205enum acpi_pcct_type {
1206 ACPI_PCCT_TYPE_GENERIC_SUBSPACE = 0,
1207 ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE = 1,
1208 ACPI_PCCT_TYPE_HW_REDUCED_SUBSPACE_TYPE2 = 2,
1209 ACPI_PCCT_TYPE_EXT_PCC_MASTER_SUBSPACE = 3,
1210 ACPI_PCCT_TYPE_EXT_PCC_SLAVE_SUBSPACE = 4,
1211 ACPI_PCCT_TYPE_RESERVED = 5
1212};
1213
1214
1215
1216
1217
1218
1219
1220struct acpi_pcct_subspace {
1221 struct acpi_subtable_header header;
1222 u8 reserved[6];
1223 u64 base_address;
1224 u64 length;
1225 struct acpi_generic_address doorbell_register;
1226 u64 preserve_mask;
1227 u64 write_mask;
1228 u32 latency;
1229 u32 max_access_rate;
1230 u16 min_turnaround_time;
1231};
1232
1233
1234
1235struct acpi_pcct_hw_reduced {
1236 struct acpi_subtable_header header;
1237 u32 platform_interrupt;
1238 u8 flags;
1239 u8 reserved;
1240 u64 base_address;
1241 u64 length;
1242 struct acpi_generic_address doorbell_register;
1243 u64 preserve_mask;
1244 u64 write_mask;
1245 u32 latency;
1246 u32 max_access_rate;
1247 u16 min_turnaround_time;
1248};
1249
1250
1251
1252struct acpi_pcct_hw_reduced_type2 {
1253 struct acpi_subtable_header header;
1254 u32 platform_interrupt;
1255 u8 flags;
1256 u8 reserved;
1257 u64 base_address;
1258 u64 length;
1259 struct acpi_generic_address doorbell_register;
1260 u64 preserve_mask;
1261 u64 write_mask;
1262 u32 latency;
1263 u32 max_access_rate;
1264 u16 min_turnaround_time;
1265 struct acpi_generic_address platform_ack_register;
1266 u64 ack_preserve_mask;
1267 u64 ack_write_mask;
1268};
1269
1270
1271
1272struct acpi_pcct_ext_pcc_master {
1273 struct acpi_subtable_header header;
1274 u32 platform_interrupt;
1275 u8 flags;
1276 u8 reserved1;
1277 u64 base_address;
1278 u32 length;
1279 struct acpi_generic_address doorbell_register;
1280 u64 preserve_mask;
1281 u64 write_mask;
1282 u32 latency;
1283 u32 max_access_rate;
1284 u32 min_turnaround_time;
1285 struct acpi_generic_address platform_ack_register;
1286 u64 ack_preserve_mask;
1287 u64 ack_set_mask;
1288 u64 reserved2;
1289 struct acpi_generic_address cmd_complete_register;
1290 u64 cmd_complete_mask;
1291 struct acpi_generic_address cmd_update_register;
1292 u64 cmd_update_preserve_mask;
1293 u64 cmd_update_set_mask;
1294 struct acpi_generic_address error_status_register;
1295 u64 error_status_mask;
1296};
1297
1298
1299
1300struct acpi_pcct_ext_pcc_slave {
1301 struct acpi_subtable_header header;
1302 u32 platform_interrupt;
1303 u8 flags;
1304 u8 reserved1;
1305 u64 base_address;
1306 u32 length;
1307 struct acpi_generic_address doorbell_register;
1308 u64 preserve_mask;
1309 u64 write_mask;
1310 u32 latency;
1311 u32 max_access_rate;
1312 u32 min_turnaround_time;
1313 struct acpi_generic_address platform_ack_register;
1314 u64 ack_preserve_mask;
1315 u64 ack_set_mask;
1316 u64 reserved2;
1317 struct acpi_generic_address cmd_complete_register;
1318 u64 cmd_complete_mask;
1319 struct acpi_generic_address cmd_update_register;
1320 u64 cmd_update_preserve_mask;
1321 u64 cmd_update_set_mask;
1322 struct acpi_generic_address error_status_register;
1323 u64 error_status_mask;
1324};
1325
1326
1327
1328#define ACPI_PCCT_INTERRUPT_POLARITY (1)
1329#define ACPI_PCCT_INTERRUPT_MODE (1<<1)
1330
1331
1332
1333
1334
1335
1336
1337struct acpi_pcct_shared_memory {
1338 u32 signature;
1339 u16 command;
1340 u16 status;
1341};
1342
1343
1344
1345struct acpi_pcct_ext_pcc_shared_memory {
1346 u32 signature;
1347 u32 flags;
1348 u32 length;
1349 u32 command;
1350};
1351
1352
1353
1354
1355
1356
1357
1358
1359struct acpi_table_pdtt {
1360 struct acpi_table_header header;
1361 u8 trigger_count;
1362 u8 reserved[3];
1363 u32 array_offset;
1364};
1365
1366
1367
1368
1369
1370
1371struct acpi_pdtt_channel {
1372 u8 subchannel_id;
1373 u8 flags;
1374};
1375
1376
1377
1378#define ACPI_PDTT_RUNTIME_TRIGGER (1)
1379#define ACPI_PDTT_WAIT_COMPLETION (1<<1)
1380#define ACPI_PDTT_TRIGGER_ORDER (1<<2)
1381
1382
1383
1384
1385
1386
1387
1388
1389struct acpi_table_pmtt {
1390 struct acpi_table_header header;
1391 u32 reserved;
1392};
1393
1394
1395
1396struct acpi_pmtt_header {
1397 u8 type;
1398 u8 reserved1;
1399 u16 length;
1400 u16 flags;
1401 u16 reserved2;
1402};
1403
1404
1405
1406#define ACPI_PMTT_TYPE_SOCKET 0
1407#define ACPI_PMTT_TYPE_CONTROLLER 1
1408#define ACPI_PMTT_TYPE_DIMM 2
1409#define ACPI_PMTT_TYPE_RESERVED 3
1410
1411
1412
1413#define ACPI_PMTT_TOP_LEVEL 0x0001
1414#define ACPI_PMTT_PHYSICAL 0x0002
1415#define ACPI_PMTT_MEMORY_TYPE 0x000C
1416
1417
1418
1419
1420
1421
1422
1423struct acpi_pmtt_socket {
1424 struct acpi_pmtt_header header;
1425 u16 socket_id;
1426 u16 reserved;
1427};
1428
1429
1430
1431struct acpi_pmtt_controller {
1432 struct acpi_pmtt_header header;
1433 u32 read_latency;
1434 u32 write_latency;
1435 u32 read_bandwidth;
1436 u32 write_bandwidth;
1437 u16 access_width;
1438 u16 alignment;
1439 u16 reserved;
1440 u16 domain_count;
1441};
1442
1443
1444
1445struct acpi_pmtt_domain {
1446 u32 proximity_domain;
1447};
1448
1449
1450
1451struct acpi_pmtt_physical_component {
1452 struct acpi_pmtt_header header;
1453 u16 component_id;
1454 u16 reserved;
1455 u32 memory_size;
1456 u32 bios_handle;
1457};
1458
1459
1460
1461
1462
1463
1464
1465
1466struct acpi_table_pptt {
1467 struct acpi_table_header header;
1468};
1469
1470
1471
1472enum acpi_pptt_type {
1473 ACPI_PPTT_TYPE_PROCESSOR = 0,
1474 ACPI_PPTT_TYPE_CACHE = 1,
1475 ACPI_PPTT_TYPE_ID = 2,
1476 ACPI_PPTT_TYPE_RESERVED = 3
1477};
1478
1479
1480
1481struct acpi_pptt_processor {
1482 struct acpi_subtable_header header;
1483 u16 reserved;
1484 u32 flags;
1485 u32 parent;
1486 u32 acpi_processor_id;
1487 u32 number_of_priv_resources;
1488};
1489
1490
1491
1492#define ACPI_PPTT_PHYSICAL_PACKAGE (1)
1493#define ACPI_PPTT_ACPI_PROCESSOR_ID_VALID (1<<1)
1494#define ACPI_PPTT_ACPI_PROCESSOR_IS_THREAD (1<<2)
1495#define ACPI_PPTT_ACPI_LEAF_NODE (1<<3)
1496#define ACPI_PPTT_ACPI_IDENTICAL (1<<4)
1497
1498
1499
1500struct acpi_pptt_cache {
1501 struct acpi_subtable_header header;
1502 u16 reserved;
1503 u32 flags;
1504 u32 next_level_of_cache;
1505 u32 size;
1506 u32 number_of_sets;
1507 u8 associativity;
1508 u8 attributes;
1509 u16 line_size;
1510};
1511
1512
1513
1514#define ACPI_PPTT_SIZE_PROPERTY_VALID (1)
1515#define ACPI_PPTT_NUMBER_OF_SETS_VALID (1<<1)
1516#define ACPI_PPTT_ASSOCIATIVITY_VALID (1<<2)
1517#define ACPI_PPTT_ALLOCATION_TYPE_VALID (1<<3)
1518#define ACPI_PPTT_CACHE_TYPE_VALID (1<<4)
1519#define ACPI_PPTT_WRITE_POLICY_VALID (1<<5)
1520#define ACPI_PPTT_LINE_SIZE_VALID (1<<6)
1521
1522
1523
1524#define ACPI_PPTT_MASK_ALLOCATION_TYPE (0x03)
1525#define ACPI_PPTT_MASK_CACHE_TYPE (0x0C)
1526#define ACPI_PPTT_MASK_WRITE_POLICY (0x10)
1527
1528
1529#define ACPI_PPTT_CACHE_READ_ALLOCATE (0x0)
1530#define ACPI_PPTT_CACHE_WRITE_ALLOCATE (0x01)
1531#define ACPI_PPTT_CACHE_RW_ALLOCATE (0x02)
1532#define ACPI_PPTT_CACHE_RW_ALLOCATE_ALT (0x03)
1533
1534#define ACPI_PPTT_CACHE_TYPE_DATA (0x0)
1535#define ACPI_PPTT_CACHE_TYPE_INSTR (1<<2)
1536#define ACPI_PPTT_CACHE_TYPE_UNIFIED (2<<2)
1537#define ACPI_PPTT_CACHE_TYPE_UNIFIED_ALT (3<<2)
1538
1539#define ACPI_PPTT_CACHE_POLICY_WB (0x0)
1540#define ACPI_PPTT_CACHE_POLICY_WT (1<<4)
1541
1542
1543
1544struct acpi_pptt_id {
1545 struct acpi_subtable_header header;
1546 u16 reserved;
1547 u32 vendor_id;
1548 u64 level1_id;
1549 u64 level2_id;
1550 u16 major_rev;
1551 u16 minor_rev;
1552 u16 spin_rev;
1553};
1554
1555
1556
1557
1558
1559
1560
1561
1562struct acpi_table_rasf {
1563 struct acpi_table_header header;
1564 u8 channel_id[12];
1565};
1566
1567
1568
1569struct acpi_rasf_shared_memory {
1570 u32 signature;
1571 u16 command;
1572 u16 status;
1573 u16 version;
1574 u8 capabilities[16];
1575 u8 set_capabilities[16];
1576 u16 num_parameter_blocks;
1577 u32 set_capabilities_status;
1578};
1579
1580
1581
1582struct acpi_rasf_parameter_block {
1583 u16 type;
1584 u16 version;
1585 u16 length;
1586};
1587
1588
1589
1590struct acpi_rasf_patrol_scrub_parameter {
1591 struct acpi_rasf_parameter_block header;
1592 u16 patrol_scrub_command;
1593 u64 requested_address_range[2];
1594 u64 actual_address_range[2];
1595 u16 flags;
1596 u8 requested_speed;
1597};
1598
1599
1600
1601#define ACPI_RASF_SCRUBBER_RUNNING 1
1602#define ACPI_RASF_SPEED (7<<1)
1603#define ACPI_RASF_SPEED_SLOW (0<<1)
1604#define ACPI_RASF_SPEED_MEDIUM (4<<1)
1605#define ACPI_RASF_SPEED_FAST (7<<1)
1606
1607
1608
1609enum acpi_rasf_commands {
1610 ACPI_RASF_EXECUTE_RASF_COMMAND = 1
1611};
1612
1613
1614
1615enum acpi_rasf_capabiliities {
1616 ACPI_HW_PATROL_SCRUB_SUPPORTED = 0,
1617 ACPI_SW_PATROL_SCRUB_EXPOSED = 1
1618};
1619
1620
1621
1622enum acpi_rasf_patrol_scrub_commands {
1623 ACPI_RASF_GET_PATROL_PARAMETERS = 1,
1624 ACPI_RASF_START_PATROL_SCRUBBER = 2,
1625 ACPI_RASF_STOP_PATROL_SCRUBBER = 3
1626};
1627
1628
1629
1630#define ACPI_RASF_GENERATE_SCI (1<<15)
1631
1632
1633
1634enum acpi_rasf_status {
1635 ACPI_RASF_SUCCESS = 0,
1636 ACPI_RASF_NOT_VALID = 1,
1637 ACPI_RASF_NOT_SUPPORTED = 2,
1638 ACPI_RASF_BUSY = 3,
1639 ACPI_RASF_FAILED = 4,
1640 ACPI_RASF_ABORTED = 5,
1641 ACPI_RASF_INVALID_DATA = 6
1642};
1643
1644
1645
1646#define ACPI_RASF_COMMAND_COMPLETE (1)
1647#define ACPI_RASF_SCI_DOORBELL (1<<1)
1648#define ACPI_RASF_ERROR (1<<2)
1649#define ACPI_RASF_STATUS (0x1F<<3)
1650
1651
1652
1653
1654
1655
1656
1657
1658struct acpi_table_sbst {
1659 struct acpi_table_header header;
1660 u32 warning_level;
1661 u32 low_level;
1662 u32 critical_level;
1663};
1664
1665
1666
1667
1668
1669
1670
1671
1672
1673
1674struct acpi_table_sdei {
1675 struct acpi_table_header header;
1676};
1677
1678
1679
1680
1681
1682
1683
1684
1685struct acpi_table_sdev {
1686 struct acpi_table_header header;
1687};
1688
1689struct acpi_sdev_header {
1690 u8 type;
1691 u8 flags;
1692 u16 length;
1693};
1694
1695
1696
1697enum acpi_sdev_type {
1698 ACPI_SDEV_TYPE_NAMESPACE_DEVICE = 0,
1699 ACPI_SDEV_TYPE_PCIE_ENDPOINT_DEVICE = 1,
1700 ACPI_SDEV_TYPE_RESERVED = 2
1701};
1702
1703
1704
1705#define ACPI_SDEV_HANDOFF_TO_UNSECURE_OS (1)
1706
1707
1708
1709
1710
1711
1712
1713struct acpi_sdev_namespace {
1714 struct acpi_sdev_header header;
1715 u16 device_id_offset;
1716 u16 device_id_length;
1717 u16 vendor_data_offset;
1718 u16 vendor_data_length;
1719};
1720
1721
1722
1723struct acpi_sdev_pcie {
1724 struct acpi_sdev_header header;
1725 u16 segment;
1726 u16 start_bus;
1727 u16 path_offset;
1728 u16 path_length;
1729 u16 vendor_data_offset;
1730 u16 vendor_data_length;
1731};
1732
1733
1734
1735struct acpi_sdev_pcie_path {
1736 u8 device;
1737 u8 function;
1738};
1739
1740
1741
1742#pragma pack()
1743
1744#endif
1745