LXR linux/include/linux/clk/tegra.h

   1/* SPDX-License-Identifier: GPL-2.0-only */
   2/*
   3 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
   4 */
   5
   6#ifndef __LINUX_CLK_TEGRA_H_
   7#define __LINUX_CLK_TEGRA_H_
   8
   9#include <linux/types.h>
  10#include <linux/bug.h>
  11
  12/*
  13 * Tegra CPU clock and reset control ops
  14 *
  15 * wait_for_reset:
  16 *      keep waiting until the CPU in reset state
  17 * put_in_reset:
  18 *      put the CPU in reset state
  19 * out_of_reset:
  20 *      release the CPU from reset state
  21 * enable_clock:
  22 *      CPU clock un-gate
  23 * disable_clock:
  24 *      CPU clock gate
  25 * rail_off_ready:
  26 *      CPU is ready for rail off
  27 * suspend:
  28 *      save the clock settings when CPU go into low-power state
  29 * resume:
  30 *      restore the clock settings when CPU exit low-power state
  31 */
  32struct tegra_cpu_car_ops {
  33        void (*wait_for_reset)(u32 cpu);
  34        void (*put_in_reset)(u32 cpu);
  35        void (*out_of_reset)(u32 cpu);
  36        void (*enable_clock)(u32 cpu);
  37        void (*disable_clock)(u32 cpu);
  38#ifdef CONFIG_PM_SLEEP
  39        bool (*rail_off_ready)(void);
  40        void (*suspend)(void);
  41        void (*resume)(void);
  42#endif
  43};
  44
  45extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
  46
  47static inline void tegra_wait_cpu_in_reset(u32 cpu)
  48{
  49        if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
  50                return;
  51
  52        tegra_cpu_car_ops->wait_for_reset(cpu);
  53}
  54
  55static inline void tegra_put_cpu_in_reset(u32 cpu)
  56{
  57        if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
  58                return;
  59
  60        tegra_cpu_car_ops->put_in_reset(cpu);
  61}
  62
  63static inline void tegra_cpu_out_of_reset(u32 cpu)
  64{
  65        if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
  66                return;
  67
  68        tegra_cpu_car_ops->out_of_reset(cpu);
  69}
  70
  71static inline void tegra_enable_cpu_clock(u32 cpu)
  72{
  73        if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
  74                return;
  75
  76        tegra_cpu_car_ops->enable_clock(cpu);
  77}
  78
  79static inline void tegra_disable_cpu_clock(u32 cpu)
  80{
  81        if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
  82                return;
  83
  84        tegra_cpu_car_ops->disable_clock(cpu);
  85}
  86
  87#ifdef CONFIG_PM_SLEEP
  88static inline bool tegra_cpu_rail_off_ready(void)
  89{
  90        if (WARN_ON(!tegra_cpu_car_ops->rail_off_ready))
  91                return false;
  92
  93        return tegra_cpu_car_ops->rail_off_ready();
  94}
  95
  96static inline void tegra_cpu_clock_suspend(void)
  97{
  98        if (WARN_ON(!tegra_cpu_car_ops->suspend))
  99                return;
 100
 101        tegra_cpu_car_ops->suspend();
 102}
 103
 104static inline void tegra_cpu_clock_resume(void)
 105{
 106        if (WARN_ON(!tegra_cpu_car_ops->resume))
 107                return;
 108
 109        tegra_cpu_car_ops->resume();
 110}
 111#else
 112static inline bool tegra_cpu_rail_off_ready(void)
 113{
 114        return false;
 115}
 116
 117static inline void tegra_cpu_clock_suspend(void)
 118{
 119}
 120
 121static inline void tegra_cpu_clock_resume(void)
 122{
 123}
 124#endif
 125
 126extern void tegra210_xusb_pll_hw_control_enable(void);
 127extern void tegra210_xusb_pll_hw_sequence_start(void);
 128extern void tegra210_sata_pll_hw_control_enable(void);
 129extern void tegra210_sata_pll_hw_sequence_start(void);
 130extern void tegra210_set_sata_pll_seq_sw(bool state);
 131extern void tegra210_put_utmipll_in_iddq(void);
 132extern void tegra210_put_utmipll_out_iddq(void);
 133extern int tegra210_clk_handle_mbist_war(unsigned int id);
 134extern void tegra210_clk_emc_dll_enable(bool flag);
 135extern void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value);
 136extern void tegra210_clk_emc_update_setting(u32 emc_src_value);
 137
 138struct clk;
 139
 140typedef long (tegra20_clk_emc_round_cb)(unsigned long rate,
 141                                        unsigned long min_rate,
 142                                        unsigned long max_rate,
 143                                        void *arg);
 144
 145void tegra20_clk_set_emc_round_callback(tegra20_clk_emc_round_cb *round_cb,
 146                                        void *cb_arg);
 147int tegra20_clk_prepare_emc_mc_same_freq(struct clk *emc_clk, bool same);
 148
 149struct tegra210_clk_emc_config {
 150        unsigned long rate;
 151        bool same_freq;
 152        u32 value;
 153
 154        unsigned long parent_rate;
 155        u8 parent;
 156};
 157
 158struct tegra210_clk_emc_provider {
 159        struct module *owner;
 160        struct device *dev;
 161
 162        struct tegra210_clk_emc_config *configs;
 163        unsigned int num_configs;
 164
 165        int (*set_rate)(struct device *dev,
 166                        const struct tegra210_clk_emc_config *config);
 167};
 168
 169int tegra210_clk_emc_attach(struct clk *clk,
 170                            struct tegra210_clk_emc_provider *provider);
 171void tegra210_clk_emc_detach(struct clk *clk);
 172
 173#endif /* __LINUX_CLK_TEGRA_H_ */
 174