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33#ifndef MLX5_DRIVER_H
34#define MLX5_DRIVER_H
35
36#include <linux/kernel.h>
37#include <linux/completion.h>
38#include <linux/pci.h>
39#include <linux/irq.h>
40#include <linux/spinlock_types.h>
41#include <linux/semaphore.h>
42#include <linux/slab.h>
43#include <linux/vmalloc.h>
44#include <linux/xarray.h>
45#include <linux/workqueue.h>
46#include <linux/mempool.h>
47#include <linux/interrupt.h>
48#include <linux/idr.h>
49#include <linux/notifier.h>
50#include <linux/refcount.h>
51
52#include <linux/mlx5/device.h>
53#include <linux/mlx5/doorbell.h>
54#include <linux/mlx5/eq.h>
55#include <linux/timecounter.h>
56#include <linux/ptp_clock_kernel.h>
57#include <net/devlink.h>
58
59enum {
60 MLX5_BOARD_ID_LEN = 64,
61};
62
63enum {
64
65
66
67 MLX5_CMD_TIMEOUT_MSEC = 60 * 1000,
68 MLX5_CMD_WQ_MAX_NAME = 32,
69};
70
71enum {
72 CMD_OWNER_SW = 0x0,
73 CMD_OWNER_HW = 0x1,
74 CMD_STATUS_SUCCESS = 0,
75};
76
77enum mlx5_sqp_t {
78 MLX5_SQP_SMI = 0,
79 MLX5_SQP_GSI = 1,
80 MLX5_SQP_IEEE_1588 = 2,
81 MLX5_SQP_SNIFFER = 3,
82 MLX5_SQP_SYNC_UMR = 4,
83};
84
85enum {
86 MLX5_MAX_PORTS = 2,
87};
88
89enum {
90 MLX5_ATOMIC_MODE_OFFSET = 16,
91 MLX5_ATOMIC_MODE_IB_COMP = 1,
92 MLX5_ATOMIC_MODE_CX = 2,
93 MLX5_ATOMIC_MODE_8B = 3,
94 MLX5_ATOMIC_MODE_16B = 4,
95 MLX5_ATOMIC_MODE_32B = 5,
96 MLX5_ATOMIC_MODE_64B = 6,
97 MLX5_ATOMIC_MODE_128B = 7,
98 MLX5_ATOMIC_MODE_256B = 8,
99};
100
101enum {
102 MLX5_REG_QPTS = 0x4002,
103 MLX5_REG_QETCR = 0x4005,
104 MLX5_REG_QTCT = 0x400a,
105 MLX5_REG_QPDPM = 0x4013,
106 MLX5_REG_QCAM = 0x4019,
107 MLX5_REG_DCBX_PARAM = 0x4020,
108 MLX5_REG_DCBX_APP = 0x4021,
109 MLX5_REG_FPGA_CAP = 0x4022,
110 MLX5_REG_FPGA_CTRL = 0x4023,
111 MLX5_REG_FPGA_ACCESS_REG = 0x4024,
112 MLX5_REG_CORE_DUMP = 0x402e,
113 MLX5_REG_PCAP = 0x5001,
114 MLX5_REG_PMTU = 0x5003,
115 MLX5_REG_PTYS = 0x5004,
116 MLX5_REG_PAOS = 0x5006,
117 MLX5_REG_PFCC = 0x5007,
118 MLX5_REG_PPCNT = 0x5008,
119 MLX5_REG_PPTB = 0x500b,
120 MLX5_REG_PBMC = 0x500c,
121 MLX5_REG_PMAOS = 0x5012,
122 MLX5_REG_PUDE = 0x5009,
123 MLX5_REG_PMPE = 0x5010,
124 MLX5_REG_PELC = 0x500e,
125 MLX5_REG_PVLC = 0x500f,
126 MLX5_REG_PCMR = 0x5041,
127 MLX5_REG_PMLP = 0x5002,
128 MLX5_REG_PPLM = 0x5023,
129 MLX5_REG_PCAM = 0x507f,
130 MLX5_REG_NODE_DESC = 0x6001,
131 MLX5_REG_HOST_ENDIANNESS = 0x7004,
132 MLX5_REG_MCIA = 0x9014,
133 MLX5_REG_MFRL = 0x9028,
134 MLX5_REG_MLCR = 0x902b,
135 MLX5_REG_MTRC_CAP = 0x9040,
136 MLX5_REG_MTRC_CONF = 0x9041,
137 MLX5_REG_MTRC_STDB = 0x9042,
138 MLX5_REG_MTRC_CTRL = 0x9043,
139 MLX5_REG_MPEIN = 0x9050,
140 MLX5_REG_MPCNT = 0x9051,
141 MLX5_REG_MTPPS = 0x9053,
142 MLX5_REG_MTPPSE = 0x9054,
143 MLX5_REG_MPEGC = 0x9056,
144 MLX5_REG_MCQS = 0x9060,
145 MLX5_REG_MCQI = 0x9061,
146 MLX5_REG_MCC = 0x9062,
147 MLX5_REG_MCDA = 0x9063,
148 MLX5_REG_MCAM = 0x907f,
149 MLX5_REG_MIRC = 0x9162,
150 MLX5_REG_SBCAM = 0xB01F,
151 MLX5_REG_RESOURCE_DUMP = 0xC000,
152};
153
154enum mlx5_qpts_trust_state {
155 MLX5_QPTS_TRUST_PCP = 1,
156 MLX5_QPTS_TRUST_DSCP = 2,
157};
158
159enum mlx5_dcbx_oper_mode {
160 MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0,
161 MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3,
162};
163
164enum {
165 MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0,
166 MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1,
167 MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2,
168 MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3,
169};
170
171enum mlx5_page_fault_resume_flags {
172 MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0,
173 MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1,
174 MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2,
175 MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7,
176};
177
178enum dbg_rsc_type {
179 MLX5_DBG_RSC_QP,
180 MLX5_DBG_RSC_EQ,
181 MLX5_DBG_RSC_CQ,
182};
183
184enum port_state_policy {
185 MLX5_POLICY_DOWN = 0,
186 MLX5_POLICY_UP = 1,
187 MLX5_POLICY_FOLLOW = 2,
188 MLX5_POLICY_INVALID = 0xffffffff
189};
190
191enum mlx5_coredev_type {
192 MLX5_COREDEV_PF,
193 MLX5_COREDEV_VF
194};
195
196struct mlx5_field_desc {
197 int i;
198};
199
200struct mlx5_rsc_debug {
201 struct mlx5_core_dev *dev;
202 void *object;
203 enum dbg_rsc_type type;
204 struct dentry *root;
205 struct mlx5_field_desc fields[];
206};
207
208enum mlx5_dev_event {
209 MLX5_DEV_EVENT_SYS_ERROR = 128,
210 MLX5_DEV_EVENT_PORT_AFFINITY = 129,
211};
212
213enum mlx5_port_status {
214 MLX5_PORT_UP = 1,
215 MLX5_PORT_DOWN = 2,
216};
217
218enum mlx5_cmdif_state {
219 MLX5_CMDIF_STATE_UNINITIALIZED,
220 MLX5_CMDIF_STATE_UP,
221 MLX5_CMDIF_STATE_DOWN,
222};
223
224struct mlx5_cmd_first {
225 __be32 data[4];
226};
227
228struct mlx5_cmd_msg {
229 struct list_head list;
230 struct cmd_msg_cache *parent;
231 u32 len;
232 struct mlx5_cmd_first first;
233 struct mlx5_cmd_mailbox *next;
234};
235
236struct mlx5_cmd_debug {
237 struct dentry *dbg_root;
238 void *in_msg;
239 void *out_msg;
240 u8 status;
241 u16 inlen;
242 u16 outlen;
243};
244
245struct cmd_msg_cache {
246
247
248 spinlock_t lock;
249 struct list_head head;
250 unsigned int max_inbox_size;
251 unsigned int num_ent;
252};
253
254enum {
255 MLX5_NUM_COMMAND_CACHES = 5,
256};
257
258struct mlx5_cmd_stats {
259 u64 sum;
260 u64 n;
261 struct dentry *root;
262
263 spinlock_t lock;
264};
265
266struct mlx5_cmd {
267 struct mlx5_nb nb;
268
269 enum mlx5_cmdif_state state;
270 void *cmd_alloc_buf;
271 dma_addr_t alloc_dma;
272 int alloc_size;
273 void *cmd_buf;
274 dma_addr_t dma;
275 u16 cmdif_rev;
276 u8 log_sz;
277 u8 log_stride;
278 int max_reg_cmds;
279 int events;
280 u32 __iomem *vector;
281
282
283
284 spinlock_t alloc_lock;
285
286
287
288 spinlock_t token_lock;
289 u8 token;
290 unsigned long bitmask;
291 char wq_name[MLX5_CMD_WQ_MAX_NAME];
292 struct workqueue_struct *wq;
293 struct semaphore sem;
294 struct semaphore pages_sem;
295 int mode;
296 u16 allowed_opcode;
297 struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS];
298 struct dma_pool *pool;
299 struct mlx5_cmd_debug dbg;
300 struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES];
301 int checksum_disabled;
302 struct mlx5_cmd_stats *stats;
303};
304
305struct mlx5_port_caps {
306 int gid_table_len;
307 int pkey_table_len;
308 u8 ext_port_cap;
309 bool has_smi;
310};
311
312struct mlx5_cmd_mailbox {
313 void *buf;
314 dma_addr_t dma;
315 struct mlx5_cmd_mailbox *next;
316};
317
318struct mlx5_buf_list {
319 void *buf;
320 dma_addr_t map;
321};
322
323struct mlx5_frag_buf {
324 struct mlx5_buf_list *frags;
325 int npages;
326 int size;
327 u8 page_shift;
328};
329
330struct mlx5_frag_buf_ctrl {
331 struct mlx5_buf_list *frags;
332 u32 sz_m1;
333 u16 frag_sz_m1;
334 u16 strides_offset;
335 u8 log_sz;
336 u8 log_stride;
337 u8 log_frag_strides;
338};
339
340struct mlx5_core_psv {
341 u32 psv_idx;
342 struct psv_layout {
343 u32 pd;
344 u16 syndrome;
345 u16 reserved;
346 u16 bg;
347 u16 app_tag;
348 u32 ref_tag;
349 } psv;
350};
351
352struct mlx5_core_sig_ctx {
353 struct mlx5_core_psv psv_memory;
354 struct mlx5_core_psv psv_wire;
355 struct ib_sig_err err_item;
356 bool sig_status_checked;
357 bool sig_err_exists;
358 u32 sigerr_count;
359};
360
361enum {
362 MLX5_MKEY_MR = 1,
363 MLX5_MKEY_MW,
364 MLX5_MKEY_INDIRECT_DEVX,
365};
366
367struct mlx5_core_mkey {
368 u64 iova;
369 u64 size;
370 u32 key;
371 u32 pd;
372 u32 type;
373};
374
375#define MLX5_24BIT_MASK ((1 << 24) - 1)
376
377enum mlx5_res_type {
378 MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP,
379 MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ,
380 MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ,
381 MLX5_RES_SRQ = 3,
382 MLX5_RES_XSRQ = 4,
383 MLX5_RES_XRQ = 5,
384 MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT,
385};
386
387struct mlx5_core_rsc_common {
388 enum mlx5_res_type res;
389 refcount_t refcount;
390 struct completion free;
391};
392
393struct mlx5_uars_page {
394 void __iomem *map;
395 bool wc;
396 u32 index;
397 struct list_head list;
398 unsigned int bfregs;
399 unsigned long *reg_bitmap;
400 unsigned long *fp_bitmap;
401 unsigned int reg_avail;
402 unsigned int fp_avail;
403 struct kref ref_count;
404 struct mlx5_core_dev *mdev;
405};
406
407struct mlx5_bfreg_head {
408
409 struct mutex lock;
410 struct list_head list;
411};
412
413struct mlx5_bfreg_data {
414 struct mlx5_bfreg_head reg_head;
415 struct mlx5_bfreg_head wc_head;
416};
417
418struct mlx5_sq_bfreg {
419 void __iomem *map;
420 struct mlx5_uars_page *up;
421 bool wc;
422 u32 index;
423 unsigned int offset;
424};
425
426struct mlx5_core_health {
427 struct health_buffer __iomem *health;
428 __be32 __iomem *health_counter;
429 struct timer_list timer;
430 u32 prev;
431 int miss_counter;
432 u8 synd;
433 u32 fatal_error;
434 u32 crdump_size;
435
436 spinlock_t wq_lock;
437 struct workqueue_struct *wq;
438 unsigned long flags;
439 struct work_struct fatal_report_work;
440 struct work_struct report_work;
441 struct delayed_work recover_work;
442 struct devlink_health_reporter *fw_reporter;
443 struct devlink_health_reporter *fw_fatal_reporter;
444};
445
446struct mlx5_qp_table {
447 struct notifier_block nb;
448
449
450
451 spinlock_t lock;
452 struct radix_tree_root tree;
453};
454
455struct mlx5_vf_context {
456 int enabled;
457 u64 port_guid;
458 u64 node_guid;
459
460
461
462 u8 port_guid_valid:1;
463 u8 node_guid_valid:1;
464 enum port_state_policy policy;
465};
466
467struct mlx5_core_sriov {
468 struct mlx5_vf_context *vfs_ctx;
469 int num_vfs;
470 u16 max_vfs;
471};
472
473struct mlx5_fc_pool {
474 struct mlx5_core_dev *dev;
475 struct mutex pool_lock;
476 struct list_head fully_used;
477 struct list_head partially_used;
478 struct list_head unused;
479 int available_fcs;
480 int used_fcs;
481 int threshold;
482};
483
484struct mlx5_fc_stats {
485 spinlock_t counters_idr_lock;
486 struct idr counters_idr;
487 struct list_head counters;
488 struct llist_head addlist;
489 struct llist_head dellist;
490
491 struct workqueue_struct *wq;
492 struct delayed_work work;
493 unsigned long next_query;
494 unsigned long sampling_interval;
495 u32 *bulk_query_out;
496 struct mlx5_fc_pool fc_pool;
497};
498
499struct mlx5_events;
500struct mlx5_mpfs;
501struct mlx5_eswitch;
502struct mlx5_lag;
503struct mlx5_devcom;
504struct mlx5_eq_table;
505struct mlx5_irq_table;
506
507struct mlx5_rate_limit {
508 u32 rate;
509 u32 max_burst_sz;
510 u16 typical_pkt_sz;
511};
512
513struct mlx5_rl_entry {
514 u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)];
515 u16 index;
516 u64 refcount;
517 u16 uid;
518 u8 dedicated : 1;
519};
520
521struct mlx5_rl_table {
522
523 struct mutex rl_lock;
524 u16 max_size;
525 u32 max_rate;
526 u32 min_rate;
527 struct mlx5_rl_entry *rl_entry;
528};
529
530struct mlx5_core_roce {
531 struct mlx5_flow_table *ft;
532 struct mlx5_flow_group *fg;
533 struct mlx5_flow_handle *allow_rule;
534};
535
536struct mlx5_priv {
537
538 struct mlx5_irq_table *irq_table;
539 struct mlx5_eq_table *eq_table;
540
541
542 struct mlx5_nb pg_nb;
543 struct workqueue_struct *pg_wq;
544 struct xarray page_root_xa;
545 int fw_pages;
546 atomic_t reg_pages;
547 struct list_head free_list;
548 int vfs_pages;
549 int peer_pf_pages;
550
551 struct mlx5_core_health health;
552
553
554 struct dentry *qp_debugfs;
555 struct dentry *eq_debugfs;
556 struct dentry *cq_debugfs;
557 struct dentry *cmdif_debugfs;
558
559
560
561
562 struct mutex alloc_mutex;
563 int numa_node;
564
565 struct mutex pgdir_mutex;
566 struct list_head pgdir_list;
567
568 struct dentry *dbg_root;
569
570 struct list_head dev_list;
571 struct list_head ctx_list;
572 spinlock_t ctx_lock;
573 struct mlx5_events *events;
574
575 struct mlx5_flow_steering *steering;
576 struct mlx5_mpfs *mpfs;
577 struct mlx5_eswitch *eswitch;
578 struct mlx5_core_sriov sriov;
579 struct mlx5_lag *lag;
580 struct mlx5_devcom *devcom;
581 struct mlx5_core_roce roce;
582 struct mlx5_fc_stats fc_stats;
583 struct mlx5_rl_table rl_table;
584
585 struct mlx5_bfreg_data bfregs;
586 struct mlx5_uars_page *uar;
587};
588
589enum mlx5_device_state {
590 MLX5_DEVICE_STATE_UNINITIALIZED,
591 MLX5_DEVICE_STATE_UP,
592 MLX5_DEVICE_STATE_INTERNAL_ERROR,
593};
594
595enum mlx5_interface_state {
596 MLX5_INTERFACE_STATE_UP = BIT(0),
597};
598
599enum mlx5_pci_status {
600 MLX5_PCI_STATUS_DISABLED,
601 MLX5_PCI_STATUS_ENABLED,
602};
603
604enum mlx5_pagefault_type_flags {
605 MLX5_PFAULT_REQUESTOR = 1 << 0,
606 MLX5_PFAULT_WRITE = 1 << 1,
607 MLX5_PFAULT_RDMA = 1 << 2,
608};
609
610struct mlx5_td {
611
612 struct mutex list_lock;
613 struct list_head tirs_list;
614 u32 tdn;
615};
616
617struct mlx5e_resources {
618 u32 pdn;
619 struct mlx5_td td;
620 struct mlx5_core_mkey mkey;
621 struct mlx5_sq_bfreg bfreg;
622};
623
624enum mlx5_sw_icm_type {
625 MLX5_SW_ICM_TYPE_STEERING,
626 MLX5_SW_ICM_TYPE_HEADER_MODIFY,
627};
628
629#define MLX5_MAX_RESERVED_GIDS 8
630
631struct mlx5_rsvd_gids {
632 unsigned int start;
633 unsigned int count;
634 struct ida ida;
635};
636
637#define MAX_PIN_NUM 8
638struct mlx5_pps {
639 u8 pin_caps[MAX_PIN_NUM];
640 struct work_struct out_work;
641 u64 start[MAX_PIN_NUM];
642 u8 enabled;
643};
644
645struct mlx5_clock {
646 struct mlx5_core_dev *mdev;
647 struct mlx5_nb pps_nb;
648 seqlock_t lock;
649 struct cyclecounter cycles;
650 struct timecounter tc;
651 struct hwtstamp_config hwtstamp_config;
652 u32 nominal_c_mult;
653 unsigned long overflow_period;
654 struct delayed_work overflow_work;
655 struct ptp_clock *ptp;
656 struct ptp_clock_info ptp_info;
657 struct mlx5_pps pps_info;
658};
659
660struct mlx5_dm;
661struct mlx5_fw_tracer;
662struct mlx5_vxlan;
663struct mlx5_geneve;
664struct mlx5_hv_vhca;
665
666#define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity))
667#define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev))
668
669struct mlx5_core_dev {
670 struct device *device;
671 enum mlx5_coredev_type coredev_type;
672 struct pci_dev *pdev;
673
674 struct mutex pci_status_mutex;
675 enum mlx5_pci_status pci_status;
676 u8 rev_id;
677 char board_id[MLX5_BOARD_ID_LEN];
678 struct mlx5_cmd cmd;
679 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
680 struct {
681 u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
682 u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)];
683 u32 pcam[MLX5_ST_SZ_DW(pcam_reg)];
684 u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)];
685 u32 fpga[MLX5_ST_SZ_DW(fpga_cap)];
686 u32 qcam[MLX5_ST_SZ_DW(qcam_reg)];
687 u8 embedded_cpu;
688 } caps;
689 u64 sys_image_guid;
690 phys_addr_t iseg_base;
691 struct mlx5_init_seg __iomem *iseg;
692 phys_addr_t bar_addr;
693 enum mlx5_device_state state;
694
695 struct mutex intf_state_mutex;
696 unsigned long intf_state;
697 struct mlx5_priv priv;
698 struct mlx5_profile *profile;
699 u32 issi;
700 struct mlx5e_resources mlx5e_res;
701 struct mlx5_dm *dm;
702 struct mlx5_vxlan *vxlan;
703 struct mlx5_geneve *geneve;
704 struct {
705 struct mlx5_rsvd_gids reserved_gids;
706 u32 roce_en;
707 } roce;
708#ifdef CONFIG_MLX5_FPGA
709 struct mlx5_fpga_device *fpga;
710#endif
711#ifdef CONFIG_MLX5_ACCEL
712 const struct mlx5_accel_ipsec_ops *ipsec_ops;
713#endif
714 struct mlx5_clock clock;
715 struct mlx5_ib_clock_info *clock_info;
716 struct mlx5_fw_tracer *tracer;
717 struct mlx5_rsc_dump *rsc_dump;
718 u32 vsc_addr;
719 struct mlx5_hv_vhca *hv_vhca;
720};
721
722struct mlx5_db {
723 __be32 *db;
724 union {
725 struct mlx5_db_pgdir *pgdir;
726 struct mlx5_ib_user_db_page *user_page;
727 } u;
728 dma_addr_t dma;
729 int index;
730};
731
732enum {
733 MLX5_COMP_EQ_SIZE = 1024,
734};
735
736enum {
737 MLX5_PTYS_IB = 1 << 0,
738 MLX5_PTYS_EN = 1 << 2,
739};
740
741typedef void (*mlx5_cmd_cbk_t)(int status, void *context);
742
743enum {
744 MLX5_CMD_ENT_STATE_PENDING_COMP,
745};
746
747struct mlx5_cmd_work_ent {
748 unsigned long state;
749 struct mlx5_cmd_msg *in;
750 struct mlx5_cmd_msg *out;
751 void *uout;
752 int uout_size;
753 mlx5_cmd_cbk_t callback;
754 struct delayed_work cb_timeout_work;
755 void *context;
756 int idx;
757 struct completion handling;
758 struct completion done;
759 struct mlx5_cmd *cmd;
760 struct work_struct work;
761 struct mlx5_cmd_layout *lay;
762 int ret;
763 int page_queue;
764 u8 status;
765 u8 token;
766 u64 ts1;
767 u64 ts2;
768 u16 op;
769 bool polling;
770
771 refcount_t refcnt;
772};
773
774struct mlx5_pas {
775 u64 pa;
776 u8 log_sz;
777};
778
779enum phy_port_state {
780 MLX5_AAA_111
781};
782
783struct mlx5_hca_vport_context {
784 u32 field_select;
785 bool sm_virt_aware;
786 bool has_smi;
787 bool has_raw;
788 enum port_state_policy policy;
789 enum phy_port_state phys_state;
790 enum ib_port_state vport_state;
791 u8 port_physical_state;
792 u64 sys_image_guid;
793 u64 port_guid;
794 u64 node_guid;
795 u32 cap_mask1;
796 u32 cap_mask1_perm;
797 u16 cap_mask2;
798 u16 cap_mask2_perm;
799 u16 lid;
800 u8 init_type_reply;
801 u8 lmc;
802 u8 subnet_timeout;
803 u16 sm_lid;
804 u8 sm_sl;
805 u16 qkey_violation_counter;
806 u16 pkey_violation_counter;
807 bool grh_required;
808};
809
810static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset)
811{
812 return buf->frags->buf + offset;
813}
814
815#define STRUCT_FIELD(header, field) \
816 .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \
817 .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field
818
819static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev)
820{
821 return pci_get_drvdata(pdev);
822}
823
824extern struct dentry *mlx5_debugfs_root;
825
826static inline u16 fw_rev_maj(struct mlx5_core_dev *dev)
827{
828 return ioread32be(&dev->iseg->fw_rev) & 0xffff;
829}
830
831static inline u16 fw_rev_min(struct mlx5_core_dev *dev)
832{
833 return ioread32be(&dev->iseg->fw_rev) >> 16;
834}
835
836static inline u16 fw_rev_sub(struct mlx5_core_dev *dev)
837{
838 return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff;
839}
840
841static inline u32 mlx5_base_mkey(const u32 key)
842{
843 return key & 0xffffff00u;
844}
845
846static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags,
847 u8 log_stride, u8 log_sz,
848 u16 strides_offset,
849 struct mlx5_frag_buf_ctrl *fbc)
850{
851 fbc->frags = frags;
852 fbc->log_stride = log_stride;
853 fbc->log_sz = log_sz;
854 fbc->sz_m1 = (1 << fbc->log_sz) - 1;
855 fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride;
856 fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1;
857 fbc->strides_offset = strides_offset;
858}
859
860static inline void mlx5_init_fbc(struct mlx5_buf_list *frags,
861 u8 log_stride, u8 log_sz,
862 struct mlx5_frag_buf_ctrl *fbc)
863{
864 mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc);
865}
866
867static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc,
868 u32 ix)
869{
870 unsigned int frag;
871
872 ix += fbc->strides_offset;
873 frag = ix >> fbc->log_frag_strides;
874
875 return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride);
876}
877
878static inline u32
879mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix)
880{
881 u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1;
882
883 return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1);
884}
885
886enum {
887 CMD_ALLOWED_OPCODE_ALL,
888};
889
890int mlx5_cmd_init(struct mlx5_core_dev *dev);
891void mlx5_cmd_cleanup(struct mlx5_core_dev *dev);
892void mlx5_cmd_set_state(struct mlx5_core_dev *dev,
893 enum mlx5_cmdif_state cmdif_state);
894void mlx5_cmd_use_events(struct mlx5_core_dev *dev);
895void mlx5_cmd_use_polling(struct mlx5_core_dev *dev);
896void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode);
897
898struct mlx5_async_ctx {
899 struct mlx5_core_dev *dev;
900 atomic_t num_inflight;
901 struct wait_queue_head wait;
902};
903
904struct mlx5_async_work;
905
906typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context);
907
908struct mlx5_async_work {
909 struct mlx5_async_ctx *ctx;
910 mlx5_async_cbk_t user_callback;
911};
912
913void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev,
914 struct mlx5_async_ctx *ctx);
915void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx);
916int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size,
917 void *out, int out_size, mlx5_async_cbk_t callback,
918 struct mlx5_async_work *work);
919
920int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out,
921 int out_size);
922
923#define mlx5_cmd_exec_inout(dev, ifc_cmd, in, out) \
924 ({ \
925 mlx5_cmd_exec(dev, in, MLX5_ST_SZ_BYTES(ifc_cmd##_in), out, \
926 MLX5_ST_SZ_BYTES(ifc_cmd##_out)); \
927 })
928
929#define mlx5_cmd_exec_in(dev, ifc_cmd, in) \
930 ({ \
931 u32 _out[MLX5_ST_SZ_DW(ifc_cmd##_out)] = {}; \
932 mlx5_cmd_exec_inout(dev, ifc_cmd, in, _out); \
933 })
934
935int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size,
936 void *out, int out_size);
937void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome);
938bool mlx5_cmd_is_down(struct mlx5_core_dev *dev);
939
940int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type);
941int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn);
942int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn);
943void mlx5_health_flush(struct mlx5_core_dev *dev);
944void mlx5_health_cleanup(struct mlx5_core_dev *dev);
945int mlx5_health_init(struct mlx5_core_dev *dev);
946void mlx5_start_health_poll(struct mlx5_core_dev *dev);
947void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health);
948void mlx5_drain_health_wq(struct mlx5_core_dev *dev);
949void mlx5_trigger_health_work(struct mlx5_core_dev *dev);
950int mlx5_buf_alloc(struct mlx5_core_dev *dev,
951 int size, struct mlx5_frag_buf *buf);
952void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
953int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size,
954 struct mlx5_frag_buf *buf, int node);
955void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf);
956struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev,
957 gfp_t flags, int npages);
958void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev,
959 struct mlx5_cmd_mailbox *head);
960int mlx5_core_create_mkey(struct mlx5_core_dev *dev,
961 struct mlx5_core_mkey *mkey,
962 u32 *in, int inlen);
963int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev,
964 struct mlx5_core_mkey *mkey);
965int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey,
966 u32 *out, int outlen);
967int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn);
968int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn);
969int mlx5_pagealloc_init(struct mlx5_core_dev *dev);
970void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev);
971void mlx5_pagealloc_start(struct mlx5_core_dev *dev);
972void mlx5_pagealloc_stop(struct mlx5_core_dev *dev);
973void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id,
974 s32 npages, bool ec_function);
975int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot);
976int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev);
977void mlx5_register_debugfs(void);
978void mlx5_unregister_debugfs(void);
979
980void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas);
981void mlx5_fill_page_frag_array_perm(struct mlx5_frag_buf *buf, __be64 *pas, u8 perm);
982void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas);
983int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
984 unsigned int *irqn);
985int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
986int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn);
987
988void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev);
989void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev);
990int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in,
991 int size_in, void *data_out, int size_out,
992 u16 reg_num, int arg, int write);
993
994int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db);
995int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db,
996 int node);
997void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db);
998
999const char *mlx5_command_str(int command);
1000void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev);
1001void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev);
1002int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn,
1003 int npsvs, u32 *sig_index);
1004int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num);
1005void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common);
1006int mlx5_query_odp_caps(struct mlx5_core_dev *dev,
1007 struct mlx5_odp_caps *odp_caps);
1008int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev,
1009 u8 port_num, void *out, size_t sz);
1010
1011int mlx5_init_rl_table(struct mlx5_core_dev *dev);
1012void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev);
1013int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index,
1014 struct mlx5_rate_limit *rl);
1015void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl);
1016bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate);
1017int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid,
1018 bool dedicated_entry, u16 *index);
1019void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index);
1020bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0,
1021 struct mlx5_rate_limit *rl_1);
1022int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg,
1023 bool map_wc, bool fast_path);
1024void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg);
1025
1026unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev);
1027struct cpumask *
1028mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector);
1029unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev);
1030int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index,
1031 u8 roce_version, u8 roce_l3_type, const u8 *gid,
1032 const u8 *mac, bool vlan, u16 vlan_id, u8 port_num);
1033
1034static inline u32 mlx5_mkey_to_idx(u32 mkey)
1035{
1036 return mkey >> 8;
1037}
1038
1039static inline u32 mlx5_idx_to_mkey(u32 mkey_idx)
1040{
1041 return mkey_idx << 8;
1042}
1043
1044static inline u8 mlx5_mkey_variant(u32 mkey)
1045{
1046 return mkey & 0xff;
1047}
1048
1049enum {
1050 MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0,
1051 MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1,
1052};
1053
1054enum {
1055 MR_CACHE_LAST_STD_ENTRY = 20,
1056 MLX5_IMR_MTT_CACHE_ENTRY,
1057 MLX5_IMR_KSM_CACHE_ENTRY,
1058 MAX_MR_CACHE_ENTRIES
1059};
1060
1061enum {
1062 MLX5_INTERFACE_PROTOCOL_IB = 0,
1063 MLX5_INTERFACE_PROTOCOL_ETH = 1,
1064 MLX5_INTERFACE_PROTOCOL_VDPA = 2,
1065};
1066
1067struct mlx5_interface {
1068 void * (*add)(struct mlx5_core_dev *dev);
1069 void (*remove)(struct mlx5_core_dev *dev, void *context);
1070 int (*attach)(struct mlx5_core_dev *dev, void *context);
1071 void (*detach)(struct mlx5_core_dev *dev, void *context);
1072 int protocol;
1073 struct list_head list;
1074};
1075
1076int mlx5_register_interface(struct mlx5_interface *intf);
1077void mlx5_unregister_interface(struct mlx5_interface *intf);
1078int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb);
1079int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb);
1080int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1081int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb);
1082
1083int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id);
1084
1085int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev);
1086int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev);
1087bool mlx5_lag_is_roce(struct mlx5_core_dev *dev);
1088bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev);
1089bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev);
1090bool mlx5_lag_is_active(struct mlx5_core_dev *dev);
1091struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev);
1092u8 mlx5_lag_get_slave_port(struct mlx5_core_dev *dev,
1093 struct net_device *slave);
1094int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev,
1095 u64 *values,
1096 int num_counters,
1097 size_t *offsets);
1098struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev);
1099void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up);
1100int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1101 u64 length, u32 log_alignment, u16 uid,
1102 phys_addr_t *addr, u32 *obj_id);
1103int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type,
1104 u64 length, u16 uid, phys_addr_t addr, u32 obj_id);
1105
1106#ifdef CONFIG_MLX5_CORE_IPOIB
1107struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev,
1108 struct ib_device *ibdev,
1109 const char *name,
1110 void (*setup)(struct net_device *));
1111#endif
1112int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev,
1113 struct ib_device *device,
1114 struct rdma_netdev_alloc_params *params);
1115
1116struct mlx5_profile {
1117 u64 mask;
1118 u8 log_max_qp;
1119 struct {
1120 int size;
1121 int limit;
1122 } mr_cache[MAX_MR_CACHE_ENTRIES];
1123};
1124
1125enum {
1126 MLX5_PCI_DEV_IS_VF = 1 << 0,
1127};
1128
1129static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev)
1130{
1131 return dev->coredev_type == MLX5_COREDEV_PF;
1132}
1133
1134static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev)
1135{
1136 return dev->coredev_type == MLX5_COREDEV_VF;
1137}
1138
1139static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev)
1140{
1141 return dev->caps.embedded_cpu;
1142}
1143
1144static inline bool
1145mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev)
1146{
1147 return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager);
1148}
1149
1150static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev)
1151{
1152 return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists);
1153}
1154
1155static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev)
1156{
1157 return dev->priv.sriov.max_vfs;
1158}
1159
1160static inline int mlx5_get_gid_table_len(u16 param)
1161{
1162 if (param > 4) {
1163 pr_warn("gid table length is zero\n");
1164 return 0;
1165 }
1166
1167 return 8 * (1 << param);
1168}
1169
1170static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev)
1171{
1172 return !!(dev->priv.rl_table.max_size);
1173}
1174
1175static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev)
1176{
1177 return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) &&
1178 MLX5_CAP_GEN(dev, num_vhca_ports) <= 1;
1179}
1180
1181static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev)
1182{
1183 return MLX5_CAP_GEN(dev, num_vhca_ports) > 1;
1184}
1185
1186static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev)
1187{
1188 return mlx5_core_is_mp_slave(dev) ||
1189 mlx5_core_is_mp_master(dev);
1190}
1191
1192static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev)
1193{
1194 if (!mlx5_core_mp_enabled(dev))
1195 return 1;
1196
1197 return MLX5_CAP_GEN(dev, native_port_num);
1198}
1199
1200enum {
1201 MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32,
1202};
1203
1204static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev)
1205{
1206 struct devlink *devlink = priv_to_devlink(dev);
1207 union devlink_param_value val;
1208
1209 devlink_param_driverinit_value_get(devlink,
1210 DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE,
1211 &val);
1212 return val.vbool;
1213}
1214
1215#endif
1216
