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6#ifndef __LINUX_MTD_SPI_NOR_H
7#define __LINUX_MTD_SPI_NOR_H
8
9#include <linux/bitops.h>
10#include <linux/mtd/cfi.h>
11#include <linux/mtd/mtd.h>
12#include <linux/spi/spi-mem.h>
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22
23#define SPINOR_OP_WRDI 0x04
24#define SPINOR_OP_WREN 0x06
25#define SPINOR_OP_RDSR 0x05
26#define SPINOR_OP_WRSR 0x01
27#define SPINOR_OP_RDSR2 0x3f
28#define SPINOR_OP_WRSR2 0x3e
29#define SPINOR_OP_READ 0x03
30#define SPINOR_OP_READ_FAST 0x0b
31#define SPINOR_OP_READ_1_1_2 0x3b
32#define SPINOR_OP_READ_1_2_2 0xbb
33#define SPINOR_OP_READ_1_1_4 0x6b
34#define SPINOR_OP_READ_1_4_4 0xeb
35#define SPINOR_OP_READ_1_1_8 0x8b
36#define SPINOR_OP_READ_1_8_8 0xcb
37#define SPINOR_OP_PP 0x02
38#define SPINOR_OP_PP_1_1_4 0x32
39#define SPINOR_OP_PP_1_4_4 0x38
40#define SPINOR_OP_PP_1_1_8 0x82
41#define SPINOR_OP_PP_1_8_8 0xc2
42#define SPINOR_OP_BE_4K 0x20
43#define SPINOR_OP_BE_4K_PMC 0xd7
44#define SPINOR_OP_BE_32K 0x52
45#define SPINOR_OP_CHIP_ERASE 0xc7
46#define SPINOR_OP_SE 0xd8
47#define SPINOR_OP_RDID 0x9f
48#define SPINOR_OP_RDSFDP 0x5a
49#define SPINOR_OP_RDCR 0x35
50#define SPINOR_OP_RDFSR 0x70
51#define SPINOR_OP_CLFSR 0x50
52#define SPINOR_OP_RDEAR 0xc8
53#define SPINOR_OP_WREAR 0xc5
54
55
56#define SPINOR_OP_READ_4B 0x13
57#define SPINOR_OP_READ_FAST_4B 0x0c
58#define SPINOR_OP_READ_1_1_2_4B 0x3c
59#define SPINOR_OP_READ_1_2_2_4B 0xbc
60#define SPINOR_OP_READ_1_1_4_4B 0x6c
61#define SPINOR_OP_READ_1_4_4_4B 0xec
62#define SPINOR_OP_READ_1_1_8_4B 0x7c
63#define SPINOR_OP_READ_1_8_8_4B 0xcc
64#define SPINOR_OP_PP_4B 0x12
65#define SPINOR_OP_PP_1_1_4_4B 0x34
66#define SPINOR_OP_PP_1_4_4_4B 0x3e
67#define SPINOR_OP_PP_1_1_8_4B 0x84
68#define SPINOR_OP_PP_1_8_8_4B 0x8e
69#define SPINOR_OP_BE_4K_4B 0x21
70#define SPINOR_OP_BE_32K_4B 0x5c
71#define SPINOR_OP_SE_4B 0xdc
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73
74#define SPINOR_OP_READ_1_1_1_DTR 0x0d
75#define SPINOR_OP_READ_1_2_2_DTR 0xbd
76#define SPINOR_OP_READ_1_4_4_DTR 0xed
77
78#define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
79#define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
80#define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
81
82
83#define SPINOR_OP_BP 0x02
84#define SPINOR_OP_AAI_WP 0xad
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86
87#define SPINOR_OP_XSE 0x50
88#define SPINOR_OP_XPP 0x82
89#define SPINOR_OP_XRDSR 0xd7
90
91#define XSR_PAGESIZE BIT(0)
92#define XSR_RDY BIT(7)
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95
96#define SPINOR_OP_EN4B 0xb7
97#define SPINOR_OP_EX4B 0xe9
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99
100#define SPINOR_OP_BRWR 0x17
101#define SPINOR_OP_CLSR 0x30
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103
104#define SPINOR_OP_RD_EVCR 0x65
105#define SPINOR_OP_WD_EVCR 0x61
106
107
108#define SR_WIP BIT(0)
109#define SR_WEL BIT(1)
110
111#define SR_BP0 BIT(2)
112#define SR_BP1 BIT(3)
113#define SR_BP2 BIT(4)
114#define SR_BP3 BIT(5)
115#define SR_TB_BIT5 BIT(5)
116#define SR_BP3_BIT6 BIT(6)
117#define SR_TB_BIT6 BIT(6)
118#define SR_SRWD BIT(7)
119
120#define SR_E_ERR BIT(5)
121#define SR_P_ERR BIT(6)
122
123#define SR1_QUAD_EN_BIT6 BIT(6)
124
125#define SR_BP_SHIFT 2
126
127
128#define EVCR_QUAD_EN_MICRON BIT(7)
129
130
131#define FSR_READY BIT(7)
132#define FSR_E_ERR BIT(5)
133#define FSR_P_ERR BIT(4)
134#define FSR_PT_ERR BIT(1)
135
136
137#define SR2_QUAD_EN_BIT1 BIT(1)
138#define SR2_QUAD_EN_BIT7 BIT(7)
139
140
141#define SNOR_PROTO_INST_MASK GENMASK(23, 16)
142#define SNOR_PROTO_INST_SHIFT 16
143#define SNOR_PROTO_INST(_nbits) \
144 ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
145 SNOR_PROTO_INST_MASK)
146
147#define SNOR_PROTO_ADDR_MASK GENMASK(15, 8)
148#define SNOR_PROTO_ADDR_SHIFT 8
149#define SNOR_PROTO_ADDR(_nbits) \
150 ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
151 SNOR_PROTO_ADDR_MASK)
152
153#define SNOR_PROTO_DATA_MASK GENMASK(7, 0)
154#define SNOR_PROTO_DATA_SHIFT 0
155#define SNOR_PROTO_DATA(_nbits) \
156 ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
157 SNOR_PROTO_DATA_MASK)
158
159#define SNOR_PROTO_IS_DTR BIT(24)
160
161#define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits) \
162 (SNOR_PROTO_INST(_inst_nbits) | \
163 SNOR_PROTO_ADDR(_addr_nbits) | \
164 SNOR_PROTO_DATA(_data_nbits))
165#define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits) \
166 (SNOR_PROTO_IS_DTR | \
167 SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
168
169enum spi_nor_protocol {
170 SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
171 SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
172 SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
173 SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
174 SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
175 SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
176 SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
177 SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
178 SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
179 SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
180
181 SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
182 SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
183 SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
184 SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
185};
186
187static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
188{
189 return !!(proto & SNOR_PROTO_IS_DTR);
190}
191
192static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
193{
194 return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
195 SNOR_PROTO_INST_SHIFT;
196}
197
198static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
199{
200 return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
201 SNOR_PROTO_ADDR_SHIFT;
202}
203
204static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
205{
206 return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
207 SNOR_PROTO_DATA_SHIFT;
208}
209
210static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
211{
212 return spi_nor_get_protocol_data_nbits(proto);
213}
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220struct spi_nor_hwcaps {
221 u32 mask;
222};
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231#define SNOR_HWCAPS_READ_MASK GENMASK(14, 0)
232#define SNOR_HWCAPS_READ BIT(0)
233#define SNOR_HWCAPS_READ_FAST BIT(1)
234#define SNOR_HWCAPS_READ_1_1_1_DTR BIT(2)
235
236#define SNOR_HWCAPS_READ_DUAL GENMASK(6, 3)
237#define SNOR_HWCAPS_READ_1_1_2 BIT(3)
238#define SNOR_HWCAPS_READ_1_2_2 BIT(4)
239#define SNOR_HWCAPS_READ_2_2_2 BIT(5)
240#define SNOR_HWCAPS_READ_1_2_2_DTR BIT(6)
241
242#define SNOR_HWCAPS_READ_QUAD GENMASK(10, 7)
243#define SNOR_HWCAPS_READ_1_1_4 BIT(7)
244#define SNOR_HWCAPS_READ_1_4_4 BIT(8)
245#define SNOR_HWCAPS_READ_4_4_4 BIT(9)
246#define SNOR_HWCAPS_READ_1_4_4_DTR BIT(10)
247
248#define SNOR_HWCAPS_READ_OCTAL GENMASK(14, 11)
249#define SNOR_HWCAPS_READ_1_1_8 BIT(11)
250#define SNOR_HWCAPS_READ_1_8_8 BIT(12)
251#define SNOR_HWCAPS_READ_8_8_8 BIT(13)
252#define SNOR_HWCAPS_READ_1_8_8_DTR BIT(14)
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263#define SNOR_HWCAPS_PP_MASK GENMASK(22, 16)
264#define SNOR_HWCAPS_PP BIT(16)
265
266#define SNOR_HWCAPS_PP_QUAD GENMASK(19, 17)
267#define SNOR_HWCAPS_PP_1_1_4 BIT(17)
268#define SNOR_HWCAPS_PP_1_4_4 BIT(18)
269#define SNOR_HWCAPS_PP_4_4_4 BIT(19)
270
271#define SNOR_HWCAPS_PP_OCTAL GENMASK(22, 20)
272#define SNOR_HWCAPS_PP_1_1_8 BIT(20)
273#define SNOR_HWCAPS_PP_1_8_8 BIT(21)
274#define SNOR_HWCAPS_PP_8_8_8 BIT(22)
275
276#define SNOR_HWCAPS_X_X_X (SNOR_HWCAPS_READ_2_2_2 | \
277 SNOR_HWCAPS_READ_4_4_4 | \
278 SNOR_HWCAPS_READ_8_8_8 | \
279 SNOR_HWCAPS_PP_4_4_4 | \
280 SNOR_HWCAPS_PP_8_8_8)
281
282#define SNOR_HWCAPS_DTR (SNOR_HWCAPS_READ_1_1_1_DTR | \
283 SNOR_HWCAPS_READ_1_2_2_DTR | \
284 SNOR_HWCAPS_READ_1_4_4_DTR | \
285 SNOR_HWCAPS_READ_1_8_8_DTR)
286
287#define SNOR_HWCAPS_ALL (SNOR_HWCAPS_READ_MASK | \
288 SNOR_HWCAPS_PP_MASK)
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290
291struct spi_nor;
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308struct spi_nor_controller_ops {
309 int (*prepare)(struct spi_nor *nor);
310 void (*unprepare)(struct spi_nor *nor);
311 int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len);
312 int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf,
313 size_t len);
314
315 ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf);
316 ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len,
317 const u8 *buf);
318 int (*erase)(struct spi_nor *nor, loff_t offs);
319};
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325struct flash_info;
326struct spi_nor_manufacturer;
327struct spi_nor_flash_parameter;
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359struct spi_nor {
360 struct mtd_info mtd;
361 struct mutex lock;
362 struct device *dev;
363 struct spi_mem *spimem;
364 u8 *bouncebuf;
365 size_t bouncebuf_size;
366 const struct flash_info *info;
367 const struct spi_nor_manufacturer *manufacturer;
368 u32 page_size;
369 u8 addr_width;
370 u8 erase_opcode;
371 u8 read_opcode;
372 u8 read_dummy;
373 u8 program_opcode;
374 enum spi_nor_protocol read_proto;
375 enum spi_nor_protocol write_proto;
376 enum spi_nor_protocol reg_proto;
377 bool sst_write_second;
378 u32 flags;
379
380 const struct spi_nor_controller_ops *controller_ops;
381
382 struct spi_nor_flash_parameter *params;
383
384 struct {
385 struct spi_mem_dirmap_desc *rdesc;
386 struct spi_mem_dirmap_desc *wdesc;
387 } dirmap;
388
389 void *priv;
390};
391
392static inline void spi_nor_set_flash_node(struct spi_nor *nor,
393 struct device_node *np)
394{
395 mtd_set_of_node(&nor->mtd, np);
396}
397
398static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
399{
400 return mtd_get_of_node(&nor->mtd);
401}
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417int spi_nor_scan(struct spi_nor *nor, const char *name,
418 const struct spi_nor_hwcaps *hwcaps);
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424void spi_nor_restore(struct spi_nor *nor);
425
426#endif
427