1/* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */ 2/* Copyright(c) 2015-17 Intel Corporation. */ 3 4#ifndef __SOUNDWIRE_H 5#define __SOUNDWIRE_H 6 7#include <linux/mod_devicetable.h> 8 9struct sdw_bus; 10struct sdw_slave; 11 12/* SDW spec defines and enums, as defined by MIPI 1.1. Spec */ 13 14/* SDW Broadcast Device Number */ 15#define SDW_BROADCAST_DEV_NUM 15 16 17/* SDW Enumeration Device Number */ 18#define SDW_ENUM_DEV_NUM 0 19 20/* SDW Group Device Numbers */ 21#define SDW_GROUP12_DEV_NUM 12 22#define SDW_GROUP13_DEV_NUM 13 23 24/* SDW Master Device Number, not supported yet */ 25#define SDW_MASTER_DEV_NUM 14 26 27#define SDW_NUM_DEV_ID_REGISTERS 6 28/* frame shape defines */ 29 30/* 31 * Note: The maximum row define in SoundWire spec 1.1 is 23. In order to 32 * fill hole with 0, one more dummy entry is added 33 */ 34#define SDW_FRAME_ROWS 24 35#define SDW_FRAME_COLS 8 36#define SDW_FRAME_ROW_COLS (SDW_FRAME_ROWS * SDW_FRAME_COLS) 37 38#define SDW_FRAME_CTRL_BITS 48 39#define SDW_MAX_DEVICES 11 40 41#define SDW_VALID_PORT_RANGE(n) ((n) <= 14 && (n) >= 1) 42 43enum { 44 SDW_PORT_DIRN_SINK = 0, 45 SDW_PORT_DIRN_SOURCE, 46 SDW_PORT_DIRN_MAX, 47}; 48 49/* 50 * constants for flow control, ports and transport 51 * 52 * these are bit masks as devices can have multiple capabilities 53 */ 54 55/* 56 * flow modes for SDW port. These can be isochronous, tx controlled, 57 * rx controlled or async 58 */ 59#define SDW_PORT_FLOW_MODE_ISOCH 0 60#define SDW_PORT_FLOW_MODE_TX_CNTRL BIT(0) 61#define SDW_PORT_FLOW_MODE_RX_CNTRL BIT(1) 62#define SDW_PORT_FLOW_MODE_ASYNC GENMASK(1, 0) 63 64/* sample packaging for block. It can be per port or per channel */ 65#define SDW_BLOCK_PACKG_PER_PORT BIT(0) 66#define SDW_BLOCK_PACKG_PER_CH BIT(1) 67 68/** 69 * enum sdw_slave_status - Slave status 70 * @SDW_SLAVE_UNATTACHED: Slave is not attached with the bus. 71 * @SDW_SLAVE_ATTACHED: Slave is attached with bus. 72 * @SDW_SLAVE_ALERT: Some alert condition on the Slave 73 * @SDW_SLAVE_RESERVED: Reserved for future use 74 */ 75enum sdw_slave_status { 76 SDW_SLAVE_UNATTACHED = 0, 77 SDW_SLAVE_ATTACHED = 1, 78 SDW_SLAVE_ALERT = 2, 79 SDW_SLAVE_RESERVED = 3, 80}; 81 82/** 83 * enum sdw_clk_stop_type: clock stop operations 84 * 85 * @SDW_CLK_PRE_PREPARE: pre clock stop prepare 86 * @SDW_CLK_POST_PREPARE: post clock stop prepare 87 * @SDW_CLK_PRE_DEPREPARE: pre clock stop de-prepare 88 * @SDW_CLK_POST_DEPREPARE: post clock stop de-prepare 89 */ 90enum sdw_clk_stop_type { 91 SDW_CLK_PRE_PREPARE = 0, 92 SDW_CLK_POST_PREPARE, 93 SDW_CLK_PRE_DEPREPARE, 94 SDW_CLK_POST_DEPREPARE, 95}; 96 97/** 98 * enum sdw_command_response - Command response as defined by SDW spec 99 * @SDW_CMD_OK: cmd was successful 100 * @SDW_CMD_IGNORED: cmd was ignored 101 * @SDW_CMD_FAIL: cmd was NACKed 102 * @SDW_CMD_TIMEOUT: cmd timedout 103 * @SDW_CMD_FAIL_OTHER: cmd failed due to other reason than above 104 * 105 * NOTE: The enum is different than actual Spec as response in the Spec is 106 * combination of ACK/NAK bits 107 * 108 * SDW_CMD_TIMEOUT/FAIL_OTHER is defined for SW use, not in spec 109 */ 110enum sdw_command_response { 111 SDW_CMD_OK = 0, 112 SDW_CMD_IGNORED = 1, 113 SDW_CMD_FAIL = 2, 114 SDW_CMD_TIMEOUT = 3, 115 SDW_CMD_FAIL_OTHER = 4, 116}; 117 118/* block group count enum */ 119enum sdw_dpn_grouping { 120 SDW_BLK_GRP_CNT_1 = 0, 121 SDW_BLK_GRP_CNT_2 = 1, 122 SDW_BLK_GRP_CNT_3 = 2, 123 SDW_BLK_GRP_CNT_4 = 3, 124}; 125 126/** 127 * enum sdw_stream_type: data stream type 128 * 129 * @SDW_STREAM_PCM: PCM data stream 130 * @SDW_STREAM_PDM: PDM data stream 131 * 132 * spec doesn't define this, but is used in implementation 133 */ 134enum sdw_stream_type { 135 SDW_STREAM_PCM = 0, 136 SDW_STREAM_PDM = 1, 137}; 138 139/** 140 * enum sdw_data_direction: Data direction 141 * 142 * @SDW_DATA_DIR_RX: Data into Port 143 * @SDW_DATA_DIR_TX: Data out of Port 144 */ 145enum sdw_data_direction { 146 SDW_DATA_DIR_RX = 0, 147 SDW_DATA_DIR_TX = 1, 148}; 149 150/** 151 * enum sdw_port_data_mode: Data Port mode 152 * 153 * @SDW_PORT_DATA_MODE_NORMAL: Normal data mode where audio data is received 154 * and transmitted. 155 * @SDW_PORT_DATA_MODE_PRBS: Test mode which uses a PRBS generator to produce 156 * a pseudo random data pattern that is transferred 157 * @SDW_PORT_DATA_MODE_STATIC_0: Simple test mode which uses static value of 158 * logic 0. The encoding will result in no signal transitions 159 * @SDW_PORT_DATA_MODE_STATIC_1: Simple test mode which uses static value of 160 * logic 1. The encoding will result in signal transitions at every bitslot 161 * owned by this Port 162 */ 163enum sdw_port_data_mode { 164 SDW_PORT_DATA_MODE_NORMAL = 0, 165 SDW_PORT_DATA_MODE_PRBS = 1, 166 SDW_PORT_DATA_MODE_STATIC_0 = 2, 167 SDW_PORT_DATA_MODE_STATIC_1 = 3, 168}; 169 170/* 171 * SDW properties, defined in MIPI DisCo spec v1.0 172 */ 173enum sdw_clk_stop_reset_behave { 174 SDW_CLK_STOP_KEEP_STATUS = 1, 175}; 176 177/** 178 * enum sdw_p15_behave - Slave Port 15 behaviour when the Master attempts a 179 * read 180 * @SDW_P15_READ_IGNORED: Read is ignored 181 * @SDW_P15_CMD_OK: Command is ok 182 */ 183enum sdw_p15_behave { 184 SDW_P15_READ_IGNORED = 0, 185 SDW_P15_CMD_OK = 1, 186}; 187 188/** 189 * enum sdw_dpn_type - Data port types 190 * @SDW_DPN_FULL: Full Data Port is supported 191 * @SDW_DPN_SIMPLE: Simplified Data Port as defined in spec. 192 * DPN_SampleCtrl2, DPN_OffsetCtrl2, DPN_HCtrl and DPN_BlockCtrl3 193 * are not implemented. 194 * @SDW_DPN_REDUCED: Reduced Data Port as defined in spec. 195 * DPN_SampleCtrl2, DPN_HCtrl are not implemented. 196 */ 197enum sdw_dpn_type { 198 SDW_DPN_FULL = 0, 199 SDW_DPN_SIMPLE = 1, 200 SDW_DPN_REDUCED = 2, 201}; 202 203/** 204 * enum sdw_clk_stop_mode - Clock Stop modes 205 * @SDW_CLK_STOP_MODE0: Slave can continue operation seamlessly on clock 206 * restart 207 * @SDW_CLK_STOP_MODE1: Slave may have entered a deeper power-saving mode, 208 * not capable of continuing operation seamlessly when the clock restarts 209 */ 210enum sdw_clk_stop_mode { 211 SDW_CLK_STOP_MODE0 = 0, 212 SDW_CLK_STOP_MODE1 = 1, 213}; 214 215/** 216 * struct sdw_dp0_prop - DP0 properties 217 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64 218 * (inclusive) 219 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64 220 * (inclusive) 221 * @num_words: number of wordlengths supported 222 * @words: wordlengths supported 223 * @BRA_flow_controlled: Slave implementation results in an OK_NotReady 224 * response 225 * @simple_ch_prep_sm: If channel prepare sequence is required 226 * @imp_def_interrupts: If set, each bit corresponds to support for 227 * implementation-defined interrupts 228 * 229 * The wordlengths are specified by Spec as max, min AND number of 230 * discrete values, implementation can define based on the wordlengths they 231 * support 232 */ 233struct sdw_dp0_prop { 234 u32 max_word; 235 u32 min_word; 236 u32 num_words; 237 u32 *words; 238 bool BRA_flow_controlled; 239 bool simple_ch_prep_sm; 240 bool imp_def_interrupts; 241}; 242 243/** 244 * struct sdw_dpn_audio_mode - Audio mode properties for DPn 245 * @bus_min_freq: Minimum bus frequency, in Hz 246 * @bus_max_freq: Maximum bus frequency, in Hz 247 * @bus_num_freq: Number of discrete frequencies supported 248 * @bus_freq: Discrete bus frequencies, in Hz 249 * @min_freq: Minimum sampling frequency, in Hz 250 * @max_freq: Maximum sampling bus frequency, in Hz 251 * @num_freq: Number of discrete sampling frequency supported 252 * @freq: Discrete sampling frequencies, in Hz 253 * @prep_ch_behave: Specifies the dependencies between Channel Prepare 254 * sequence and bus clock configuration 255 * If 0, Channel Prepare can happen at any Bus clock rate 256 * If 1, Channel Prepare sequence shall happen only after Bus clock is 257 * changed to a frequency supported by this mode or compatible modes 258 * described by the next field 259 * @glitchless: Bitmap describing possible glitchless transitions from this 260 * Audio Mode to other Audio Modes 261 */ 262struct sdw_dpn_audio_mode { 263 u32 bus_min_freq; 264 u32 bus_max_freq; 265 u32 bus_num_freq; 266 u32 *bus_freq; 267 u32 max_freq; 268 u32 min_freq; 269 u32 num_freq; 270 u32 *freq; 271 u32 prep_ch_behave; 272 u32 glitchless; 273}; 274 275/** 276 * struct sdw_dpn_prop - Data Port DPn properties 277 * @num: port number 278 * @max_word: Maximum number of bits in a Payload Channel Sample, 1 to 64 279 * (inclusive) 280 * @min_word: Minimum number of bits in a Payload Channel Sample, 1 to 64 281 * (inclusive) 282 * @num_words: Number of discrete supported wordlengths 283 * @words: Discrete supported wordlength 284 * @type: Data port type. Full, Simplified or Reduced 285 * @max_grouping: Maximum number of samples that can be grouped together for 286 * a full data port 287 * @simple_ch_prep_sm: If the port supports simplified channel prepare state 288 * machine 289 * @ch_prep_timeout: Port-specific timeout value, in milliseconds 290 * @imp_def_interrupts: If set, each bit corresponds to support for 291 * implementation-defined interrupts 292 * @max_ch: Maximum channels supported 293 * @min_ch: Minimum channels supported 294 * @num_channels: Number of discrete channels supported 295 * @channels: Discrete channels supported 296 * @num_ch_combinations: Number of channel combinations supported 297 * @ch_combinations: Channel combinations supported 298 * @modes: SDW mode supported 299 * @max_async_buffer: Number of samples that this port can buffer in 300 * asynchronous modes 301 * @block_pack_mode: Type of block port mode supported 302 * @read_only_wordlength: Read Only wordlength field in DPN_BlockCtrl1 register 303 * @port_encoding: Payload Channel Sample encoding schemes supported 304 * @audio_modes: Audio modes supported 305 */ 306struct sdw_dpn_prop { 307 u32 num; 308 u32 max_word; 309 u32 min_word; 310 u32 num_words; 311 u32 *words; 312 enum sdw_dpn_type type; 313 u32 max_grouping; 314 bool simple_ch_prep_sm; 315 u32 ch_prep_timeout; 316 u32 imp_def_interrupts; 317 u32 max_ch; 318 u32 min_ch; 319 u32 num_channels; 320 u32 *channels; 321 u32 num_ch_combinations; 322 u32 *ch_combinations; 323 u32 modes; 324 u32 max_async_buffer; 325 bool block_pack_mode; 326 bool read_only_wordlength; 327 u32 port_encoding; 328 struct sdw_dpn_audio_mode *audio_modes; 329}; 330 331/** 332 * struct sdw_slave_prop - SoundWire Slave properties 333 * @mipi_revision: Spec version of the implementation 334 * @wake_capable: Wake-up events are supported 335 * @test_mode_capable: If test mode is supported 336 * @clk_stop_mode1: Clock-Stop Mode 1 is supported 337 * @simple_clk_stop_capable: Simple clock mode is supported 338 * @clk_stop_timeout: Worst-case latency of the Clock Stop Prepare State 339 * Machine transitions, in milliseconds 340 * @ch_prep_timeout: Worst-case latency of the Channel Prepare State Machine 341 * transitions, in milliseconds 342 * @reset_behave: Slave keeps the status of the SlaveStopClockPrepare 343 * state machine (P=1 SCSP_SM) after exit from clock-stop mode1 344 * @high_PHY_capable: Slave is HighPHY capable 345 * @paging_support: Slave implements paging registers SCP_AddrPage1 and 346 * SCP_AddrPage2 347 * @bank_delay_support: Slave implements bank delay/bridge support registers 348 * SCP_BankDelay and SCP_NextFrame 349 * @p15_behave: Slave behavior when the Master attempts a read to the Port15 350 * alias 351 * @lane_control_support: Slave supports lane control 352 * @master_count: Number of Masters present on this Slave 353 * @source_ports: Bitmap identifying source ports 354 * @sink_ports: Bitmap identifying sink ports 355 * @dp0_prop: Data Port 0 properties 356 * @src_dpn_prop: Source Data Port N properties 357 * @sink_dpn_prop: Sink Data Port N properties 358 */ 359struct sdw_slave_prop { 360 u32 mipi_revision; 361 bool wake_capable; 362 bool test_mode_capable; 363 bool clk_stop_mode1; 364 bool simple_clk_stop_capable; 365 u32 clk_stop_timeout; 366 u32 ch_prep_timeout; 367 enum sdw_clk_stop_reset_behave reset_behave; 368 bool high_PHY_capable; 369 bool paging_support; 370 bool bank_delay_support; 371 enum sdw_p15_behave p15_behave; 372 bool lane_control_support; 373 u32 master_count; 374 u32 source_ports; 375 u32 sink_ports; 376 struct sdw_dp0_prop *dp0_prop; 377 struct sdw_dpn_prop *src_dpn_prop; 378 struct sdw_dpn_prop *sink_dpn_prop; 379}; 380 381/** 382 * struct sdw_master_prop - Master properties 383 * @revision: MIPI spec version of the implementation 384 * @clk_stop_modes: Bitmap, bit N set when clock-stop-modeN supported 385 * @max_clk_freq: Maximum Bus clock frequency, in Hz 386 * @num_clk_gears: Number of clock gears supported 387 * @clk_gears: Clock gears supported 388 * @num_clk_freq: Number of clock frequencies supported, in Hz 389 * @clk_freq: Clock frequencies supported, in Hz 390 * @default_frame_rate: Controller default Frame rate, in Hz 391 * @default_row: Number of rows 392 * @default_col: Number of columns 393 * @dynamic_frame: Dynamic frame shape supported 394 * @err_threshold: Number of times that software may retry sending a single 395 * command 396 * @mclk_freq: clock reference passed to SoundWire Master, in Hz. 397 * @hw_disabled: if true, the Master is not functional, typically due to pin-mux 398 */ 399struct sdw_master_prop { 400 u32 revision; 401 u32 clk_stop_modes; 402 u32 max_clk_freq; 403 u32 num_clk_gears; 404 u32 *clk_gears; 405 u32 num_clk_freq; 406 u32 *clk_freq; 407 u32 default_frame_rate; 408 u32 default_row; 409 u32 default_col; 410 bool dynamic_frame; 411 u32 err_threshold; 412 u32 mclk_freq; 413 bool hw_disabled; 414}; 415 416int sdw_master_read_prop(struct sdw_bus *bus); 417int sdw_slave_read_prop(struct sdw_slave *slave); 418 419/* 420 * SDW Slave Structures and APIs 421 */ 422 423#define SDW_IGNORED_UNIQUE_ID 0xFF 424 425/** 426 * struct sdw_slave_id - Slave ID 427 * @mfg_id: MIPI Manufacturer ID 428 * @part_id: Device Part ID 429 * @class_id: MIPI Class ID (defined starting with SoundWire 1.2 spec) 430 * @unique_id: Device unique ID 431 * @sdw_version: SDW version implemented 432 * 433 * The order of the IDs here does not follow the DisCo spec definitions 434 */ 435struct sdw_slave_id { 436 __u16 mfg_id; 437 __u16 part_id; 438 __u8 class_id; 439 __u8 unique_id; 440 __u8 sdw_version:4; 441}; 442 443/* 444 * Helper macros to extract the MIPI-defined IDs 445 * 446 * Spec definition 447 * Register Bit Contents 448 * DevId_0 [7:4] 47:44 sdw_version 449 * DevId_0 [3:0] 43:40 unique_id 450 * DevId_1 39:32 mfg_id [15:8] 451 * DevId_2 31:24 mfg_id [7:0] 452 * DevId_3 23:16 part_id [15:8] 453 * DevId_4 15:08 part_id [7:0] 454 * DevId_5 07:00 class_id 455 * 456 * The MIPI DisCo for SoundWire defines in addition the link_id as bits 51:48 457 */ 458 459#define SDW_DISCO_LINK_ID(adr) (((adr) >> 48) & GENMASK(3, 0)) 460#define SDW_VERSION(adr) (((adr) >> 44) & GENMASK(3, 0)) 461#define SDW_UNIQUE_ID(adr) (((adr) >> 40) & GENMASK(3, 0)) 462#define SDW_MFG_ID(adr) (((adr) >> 24) & GENMASK(15, 0)) 463#define SDW_PART_ID(adr) (((adr) >> 8) & GENMASK(15, 0)) 464#define SDW_CLASS_ID(adr) ((adr) & GENMASK(7, 0)) 465 466/** 467 * struct sdw_slave_intr_status - Slave interrupt status 468 * @control_port: control port status 469 * @port: data port status 470 */ 471struct sdw_slave_intr_status { 472 u8 control_port; 473 u8 port[15]; 474}; 475 476/** 477 * sdw_reg_bank - SoundWire register banks 478 * @SDW_BANK0: Soundwire register bank 0 479 * @SDW_BANK1: Soundwire register bank 1 480 */ 481enum sdw_reg_bank { 482 SDW_BANK0, 483 SDW_BANK1, 484}; 485 486/** 487 * struct sdw_bus_conf: Bus configuration 488 * 489 * @clk_freq: Clock frequency, in Hz 490 * @num_rows: Number of rows in frame 491 * @num_cols: Number of columns in frame 492 * @bank: Next register bank 493 */ 494struct sdw_bus_conf { 495 unsigned int clk_freq; 496 unsigned int num_rows; 497 unsigned int num_cols; 498 unsigned int bank; 499}; 500 501/** 502 * struct sdw_prepare_ch: Prepare/De-prepare Data Port channel 503 * 504 * @num: Port number 505 * @ch_mask: Active channel mask 506 * @prepare: Prepare (true) /de-prepare (false) channel 507 * @bank: Register bank, which bank Slave/Master driver should program for 508 * implementation defined registers. This is always updated to next_bank 509 * value read from bus params. 510 * 511 */ 512struct sdw_prepare_ch { 513 unsigned int num; 514 unsigned int ch_mask; 515 bool prepare; 516 unsigned int bank; 517}; 518 519/** 520 * enum sdw_port_prep_ops: Prepare operations for Data Port 521 * 522 * @SDW_OPS_PORT_PRE_PREP: Pre prepare operation for the Port 523 * @SDW_OPS_PORT_PREP: Prepare operation for the Port 524 * @SDW_OPS_PORT_POST_PREP: Post prepare operation for the Port 525 */ 526enum sdw_port_prep_ops { 527 SDW_OPS_PORT_PRE_PREP = 0, 528 SDW_OPS_PORT_PREP = 1, 529 SDW_OPS_PORT_POST_PREP = 2, 530}; 531 532/** 533 * struct sdw_bus_params: Structure holding bus configuration 534 * 535 * @curr_bank: Current bank in use (BANK0/BANK1) 536 * @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be 537 * set to !curr_bank 538 * @max_dr_freq: Maximum double rate clock frequency supported, in Hz 539 * @curr_dr_freq: Current double rate clock frequency, in Hz 540 * @bandwidth: Current bandwidth 541 * @col: Active columns 542 * @row: Active rows 543 */ 544struct sdw_bus_params { 545 enum sdw_reg_bank curr_bank; 546 enum sdw_reg_bank next_bank; 547 unsigned int max_dr_freq; 548 unsigned int curr_dr_freq; 549 unsigned int bandwidth; 550 unsigned int col; 551 unsigned int row; 552}; 553 554/** 555 * struct sdw_slave_ops: Slave driver callback ops 556 * 557 * @read_prop: Read Slave properties 558 * @interrupt_callback: Device interrupt notification (invoked in thread 559 * context) 560 * @update_status: Update Slave status 561 * @bus_config: Update the bus config for Slave 562 * @port_prep: Prepare the port with parameters 563 */ 564struct sdw_slave_ops { 565 int (*read_prop)(struct sdw_slave *sdw); 566 int (*interrupt_callback)(struct sdw_slave *slave, 567 struct sdw_slave_intr_status *status); 568 int (*update_status)(struct sdw_slave *slave, 569 enum sdw_slave_status status); 570 int (*bus_config)(struct sdw_slave *slave, 571 struct sdw_bus_params *params); 572 int (*port_prep)(struct sdw_slave *slave, 573 struct sdw_prepare_ch *prepare_ch, 574 enum sdw_port_prep_ops pre_ops); 575 int (*get_clk_stop_mode)(struct sdw_slave *slave); 576 int (*clk_stop)(struct sdw_slave *slave, 577 enum sdw_clk_stop_mode mode, 578 enum sdw_clk_stop_type type); 579 580}; 581 582/** 583 * struct sdw_slave - SoundWire Slave 584 * @id: MIPI device ID 585 * @dev: Linux device 586 * @status: Status reported by the Slave 587 * @bus: Bus handle 588 * @ops: Slave callback ops 589 * @prop: Slave properties 590 * @debugfs: Slave debugfs 591 * @node: node for bus list 592 * @port_ready: Port ready completion flag for each Slave port 593 * @dev_num: Current Device Number, values can be 0 or dev_num_sticky 594 * @dev_num_sticky: one-time static Device Number assigned by Bus 595 * @probed: boolean tracking driver state 596 * @probe_complete: completion utility to control potential races 597 * on startup between driver probe/initialization and SoundWire 598 * Slave state changes/implementation-defined interrupts 599 * @enumeration_complete: completion utility to control potential races 600 * on startup between device enumeration and read/write access to the 601 * Slave device 602 * @initialization_complete: completion utility to control potential races 603 * on startup between device enumeration and settings being restored 604 * @unattach_request: mask field to keep track why the Slave re-attached and 605 * was re-initialized. This is useful to deal with potential race conditions 606 * between the Master suspending and the codec resuming, and make sure that 607 * when the Master triggered a reset the Slave is properly enumerated and 608 * initialized 609 */ 610struct sdw_slave { 611 struct sdw_slave_id id; 612 struct device dev; 613 enum sdw_slave_status status; 614 struct sdw_bus *bus; 615 const struct sdw_slave_ops *ops; 616 struct sdw_slave_prop prop; 617#ifdef CONFIG_DEBUG_FS 618 struct dentry *debugfs; 619#endif 620 struct list_head node; 621 struct completion *port_ready; 622 enum sdw_clk_stop_mode curr_clk_stop_mode; 623 u16 dev_num; 624 u16 dev_num_sticky; 625 bool probed; 626 struct completion probe_complete; 627 struct completion enumeration_complete; 628 struct completion initialization_complete; 629 u32 unattach_request; 630}; 631 632#define dev_to_sdw_dev(_dev) container_of(_dev, struct sdw_slave, dev) 633 634/** 635 * struct sdw_master_device - SoundWire 'Master Device' representation 636 * @dev: Linux device for this Master 637 * @bus: Bus handle shortcut 638 */ 639struct sdw_master_device { 640 struct device dev; 641 struct sdw_bus *bus; 642}; 643 644#define dev_to_sdw_master_device(d) \ 645 container_of(d, struct sdw_master_device, dev) 646 647struct sdw_driver { 648 const char *name; 649 650 int (*probe)(struct sdw_slave *sdw, 651 const struct sdw_device_id *id); 652 int (*remove)(struct sdw_slave *sdw); 653 void (*shutdown)(struct sdw_slave *sdw); 654 655 const struct sdw_device_id *id_table; 656 const struct sdw_slave_ops *ops; 657 658 struct device_driver driver; 659}; 660 661#define SDW_SLAVE_ENTRY_EXT(_mfg_id, _part_id, _version, _c_id, _drv_data) \ 662 { .mfg_id = (_mfg_id), .part_id = (_part_id), \ 663 .sdw_version = (_version), .class_id = (_c_id), \ 664 .driver_data = (unsigned long)(_drv_data) } 665 666#define SDW_SLAVE_ENTRY(_mfg_id, _part_id, _drv_data) \ 667 SDW_SLAVE_ENTRY_EXT((_mfg_id), (_part_id), 0, 0, (_drv_data)) 668 669int sdw_handle_slave_status(struct sdw_bus *bus, 670 enum sdw_slave_status status[]); 671 672/* 673 * SDW master structures and APIs 674 */ 675 676/** 677 * struct sdw_port_params: Data Port parameters 678 * 679 * @num: Port number 680 * @bps: Word length of the Port 681 * @flow_mode: Port Data flow mode 682 * @data_mode: Test modes or normal mode 683 * 684 * This is used to program the Data Port based on Data Port stream 685 * parameters. 686 */ 687struct sdw_port_params { 688 unsigned int num; 689 unsigned int bps; 690 unsigned int flow_mode; 691 unsigned int data_mode; 692}; 693 694/** 695 * struct sdw_transport_params: Data Port Transport Parameters 696 * 697 * @blk_grp_ctrl_valid: Port implements block group control 698 * @num: Port number 699 * @blk_grp_ctrl: Block group control value 700 * @sample_interval: Sample interval 701 * @offset1: Blockoffset of the payload data 702 * @offset2: Blockoffset of the payload data 703 * @hstart: Horizontal start of the payload data 704 * @hstop: Horizontal stop of the payload data 705 * @blk_pkg_mode: Block per channel or block per port 706 * @lane_ctrl: Data lane Port uses for Data transfer. Currently only single 707 * data lane is supported in bus 708 * 709 * This is used to program the Data Port based on Data Port transport 710 * parameters. All these parameters are banked and can be modified 711 * during a bank switch without any artifacts in audio stream. 712 */ 713struct sdw_transport_params { 714 bool blk_grp_ctrl_valid; 715 unsigned int port_num; 716 unsigned int blk_grp_ctrl; 717 unsigned int sample_interval; 718 unsigned int offset1; 719 unsigned int offset2; 720 unsigned int hstart; 721 unsigned int hstop; 722 unsigned int blk_pkg_mode; 723 unsigned int lane_ctrl; 724}; 725 726/** 727 * struct sdw_enable_ch: Enable/disable Data Port channel 728 * 729 * @num: Port number 730 * @ch_mask: Active channel mask 731 * @enable: Enable (true) /disable (false) channel 732 */ 733struct sdw_enable_ch { 734 unsigned int port_num; 735 unsigned int ch_mask; 736 bool enable; 737}; 738 739/** 740 * struct sdw_master_port_ops: Callback functions from bus to Master 741 * driver to set Master Data ports. 742 * 743 * @dpn_set_port_params: Set the Port parameters for the Master Port. 744 * Mandatory callback 745 * @dpn_set_port_transport_params: Set transport parameters for the Master 746 * Port. Mandatory callback 747 * @dpn_port_prep: Port prepare operations for the Master Data Port. 748 * @dpn_port_enable_ch: Enable the channels of Master Port. 749 */ 750struct sdw_master_port_ops { 751 int (*dpn_set_port_params)(struct sdw_bus *bus, 752 struct sdw_port_params *port_params, 753 unsigned int bank); 754 int (*dpn_set_port_transport_params)(struct sdw_bus *bus, 755 struct sdw_transport_params *transport_params, 756 enum sdw_reg_bank bank); 757 int (*dpn_port_prep)(struct sdw_bus *bus, 758 struct sdw_prepare_ch *prepare_ch); 759 int (*dpn_port_enable_ch)(struct sdw_bus *bus, 760 struct sdw_enable_ch *enable_ch, unsigned int bank); 761}; 762 763struct sdw_msg; 764 765/** 766 * struct sdw_defer - SDW deffered message 767 * @length: message length 768 * @complete: message completion 769 * @msg: SDW message 770 */ 771struct sdw_defer { 772 int length; 773 struct completion complete; 774 struct sdw_msg *msg; 775}; 776 777/** 778 * struct sdw_master_ops - Master driver ops 779 * @read_prop: Read Master properties 780 * @xfer_msg: Transfer message callback 781 * @xfer_msg_defer: Defer version of transfer message callback 782 * @reset_page_addr: Reset the SCP page address registers 783 * @set_bus_conf: Set the bus configuration 784 * @pre_bank_switch: Callback for pre bank switch 785 * @post_bank_switch: Callback for post bank switch 786 */ 787struct sdw_master_ops { 788 int (*read_prop)(struct sdw_bus *bus); 789 790 enum sdw_command_response (*xfer_msg) 791 (struct sdw_bus *bus, struct sdw_msg *msg); 792 enum sdw_command_response (*xfer_msg_defer) 793 (struct sdw_bus *bus, struct sdw_msg *msg, 794 struct sdw_defer *defer); 795 enum sdw_command_response (*reset_page_addr) 796 (struct sdw_bus *bus, unsigned int dev_num); 797 int (*set_bus_conf)(struct sdw_bus *bus, 798 struct sdw_bus_params *params); 799 int (*pre_bank_switch)(struct sdw_bus *bus); 800 int (*post_bank_switch)(struct sdw_bus *bus); 801 802}; 803 804/** 805 * struct sdw_bus - SoundWire bus 806 * @dev: Shortcut to &bus->md->dev to avoid changing the entire code. 807 * @md: Master device 808 * @link_id: Link id number, can be 0 to N, unique for each Master 809 * @id: bus system-wide unique id 810 * @slaves: list of Slaves on this bus 811 * @assigned: Bitmap for Slave device numbers. 812 * Bit set implies used number, bit clear implies unused number. 813 * @bus_lock: bus lock 814 * @msg_lock: message lock 815 * @compute_params: points to Bus resource management implementation 816 * @ops: Master callback ops 817 * @port_ops: Master port callback ops 818 * @params: Current bus parameters 819 * @prop: Master properties 820 * @m_rt_list: List of Master instance of all stream(s) running on Bus. This 821 * is used to compute and program bus bandwidth, clock, frame shape, 822 * transport and port parameters 823 * @debugfs: Bus debugfs 824 * @defer_msg: Defer message 825 * @clk_stop_timeout: Clock stop timeout computed 826 * @bank_switch_timeout: Bank switch timeout computed 827 * @multi_link: Store bus property that indicates if multi links 828 * are supported. This flag is populated by drivers after reading 829 * appropriate firmware (ACPI/DT). 830 */ 831struct sdw_bus { 832 struct device *dev; 833 struct sdw_master_device *md; 834 unsigned int link_id; 835 int id; 836 struct list_head slaves; 837 DECLARE_BITMAP(assigned, SDW_MAX_DEVICES); 838 struct mutex bus_lock; 839 struct mutex msg_lock; 840 int (*compute_params)(struct sdw_bus *bus); 841 const struct sdw_master_ops *ops; 842 const struct sdw_master_port_ops *port_ops; 843 struct sdw_bus_params params; 844 struct sdw_master_prop prop; 845 struct list_head m_rt_list; 846#ifdef CONFIG_DEBUG_FS 847 struct dentry *debugfs; 848#endif 849 struct sdw_defer defer_msg; 850 unsigned int clk_stop_timeout; 851 u32 bank_switch_timeout; 852 bool multi_link; 853}; 854 855int sdw_bus_master_add(struct sdw_bus *bus, struct device *parent, 856 struct fwnode_handle *fwnode); 857void sdw_bus_master_delete(struct sdw_bus *bus); 858 859/** 860 * sdw_port_config: Master or Slave Port configuration 861 * 862 * @num: Port number 863 * @ch_mask: channels mask for port 864 */ 865struct sdw_port_config { 866 unsigned int num; 867 unsigned int ch_mask; 868}; 869 870/** 871 * sdw_stream_config: Master or Slave stream configuration 872 * 873 * @frame_rate: Audio frame rate of the stream, in Hz 874 * @ch_count: Channel count of the stream 875 * @bps: Number of bits per audio sample 876 * @direction: Data direction 877 * @type: Stream type PCM or PDM 878 */ 879struct sdw_stream_config { 880 unsigned int frame_rate; 881 unsigned int ch_count; 882 unsigned int bps; 883 enum sdw_data_direction direction; 884 enum sdw_stream_type type; 885}; 886 887/** 888 * sdw_stream_state: Stream states 889 * 890 * @SDW_STREAM_ALLOCATED: New stream allocated. 891 * @SDW_STREAM_CONFIGURED: Stream configured 892 * @SDW_STREAM_PREPARED: Stream prepared 893 * @SDW_STREAM_ENABLED: Stream enabled 894 * @SDW_STREAM_DISABLED: Stream disabled 895 * @SDW_STREAM_DEPREPARED: Stream de-prepared 896 * @SDW_STREAM_RELEASED: Stream released 897 */ 898enum sdw_stream_state { 899 SDW_STREAM_ALLOCATED = 0, 900 SDW_STREAM_CONFIGURED = 1, 901 SDW_STREAM_PREPARED = 2, 902 SDW_STREAM_ENABLED = 3, 903 SDW_STREAM_DISABLED = 4, 904 SDW_STREAM_DEPREPARED = 5, 905 SDW_STREAM_RELEASED = 6, 906}; 907 908/** 909 * sdw_stream_params: Stream parameters 910 * 911 * @rate: Sampling frequency, in Hz 912 * @ch_count: Number of channels 913 * @bps: bits per channel sample 914 */ 915struct sdw_stream_params { 916 unsigned int rate; 917 unsigned int ch_count; 918 unsigned int bps; 919}; 920 921/** 922 * sdw_stream_runtime: Runtime stream parameters 923 * 924 * @name: SoundWire stream name 925 * @params: Stream parameters 926 * @state: Current state of the stream 927 * @type: Stream type PCM or PDM 928 * @master_list: List of Master runtime(s) in this stream. 929 * master_list can contain only one m_rt per Master instance 930 * for a stream 931 * @m_rt_count: Count of Master runtime(s) in this stream 932 */ 933struct sdw_stream_runtime { 934 const char *name; 935 struct sdw_stream_params params; 936 enum sdw_stream_state state; 937 enum sdw_stream_type type; 938 struct list_head master_list; 939 int m_rt_count; 940}; 941 942struct sdw_stream_runtime *sdw_alloc_stream(const char *stream_name); 943void sdw_release_stream(struct sdw_stream_runtime *stream); 944int sdw_stream_add_master(struct sdw_bus *bus, 945 struct sdw_stream_config *stream_config, 946 struct sdw_port_config *port_config, 947 unsigned int num_ports, 948 struct sdw_stream_runtime *stream); 949int sdw_stream_add_slave(struct sdw_slave *slave, 950 struct sdw_stream_config *stream_config, 951 struct sdw_port_config *port_config, 952 unsigned int num_ports, 953 struct sdw_stream_runtime *stream); 954int sdw_stream_remove_master(struct sdw_bus *bus, 955 struct sdw_stream_runtime *stream); 956int sdw_stream_remove_slave(struct sdw_slave *slave, 957 struct sdw_stream_runtime *stream); 958int sdw_startup_stream(void *sdw_substream); 959int sdw_prepare_stream(struct sdw_stream_runtime *stream); 960int sdw_enable_stream(struct sdw_stream_runtime *stream); 961int sdw_disable_stream(struct sdw_stream_runtime *stream); 962int sdw_deprepare_stream(struct sdw_stream_runtime *stream); 963void sdw_shutdown_stream(void *sdw_substream); 964int sdw_bus_prep_clk_stop(struct sdw_bus *bus); 965int sdw_bus_clk_stop(struct sdw_bus *bus); 966int sdw_bus_exit_clk_stop(struct sdw_bus *bus); 967 968/* messaging and data APIs */ 969 970int sdw_read(struct sdw_slave *slave, u32 addr); 971int sdw_write(struct sdw_slave *slave, u32 addr, u8 value); 972int sdw_nread(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); 973int sdw_nwrite(struct sdw_slave *slave, u32 addr, size_t count, u8 *val); 974 975#endif /* __SOUNDWIRE_H */ 976