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18#ifndef __ETNAVIV_DRM_H__
19#define __ETNAVIV_DRM_H__
20
21#include "drm.h"
22
23#if defined(__cplusplus)
24extern "C" {
25#endif
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43
44struct drm_etnaviv_timespec {
45 __s64 tv_sec;
46 __s64 tv_nsec;
47};
48
49#define ETNAVIV_PARAM_GPU_MODEL 0x01
50#define ETNAVIV_PARAM_GPU_REVISION 0x02
51#define ETNAVIV_PARAM_GPU_FEATURES_0 0x03
52#define ETNAVIV_PARAM_GPU_FEATURES_1 0x04
53#define ETNAVIV_PARAM_GPU_FEATURES_2 0x05
54#define ETNAVIV_PARAM_GPU_FEATURES_3 0x06
55#define ETNAVIV_PARAM_GPU_FEATURES_4 0x07
56#define ETNAVIV_PARAM_GPU_FEATURES_5 0x08
57#define ETNAVIV_PARAM_GPU_FEATURES_6 0x09
58#define ETNAVIV_PARAM_GPU_FEATURES_7 0x0a
59#define ETNAVIV_PARAM_GPU_FEATURES_8 0x0b
60#define ETNAVIV_PARAM_GPU_FEATURES_9 0x0c
61#define ETNAVIV_PARAM_GPU_FEATURES_10 0x0d
62#define ETNAVIV_PARAM_GPU_FEATURES_11 0x0e
63#define ETNAVIV_PARAM_GPU_FEATURES_12 0x0f
64
65#define ETNAVIV_PARAM_GPU_STREAM_COUNT 0x10
66#define ETNAVIV_PARAM_GPU_REGISTER_MAX 0x11
67#define ETNAVIV_PARAM_GPU_THREAD_COUNT 0x12
68#define ETNAVIV_PARAM_GPU_VERTEX_CACHE_SIZE 0x13
69#define ETNAVIV_PARAM_GPU_SHADER_CORE_COUNT 0x14
70#define ETNAVIV_PARAM_GPU_PIXEL_PIPES 0x15
71#define ETNAVIV_PARAM_GPU_VERTEX_OUTPUT_BUFFER_SIZE 0x16
72#define ETNAVIV_PARAM_GPU_BUFFER_SIZE 0x17
73#define ETNAVIV_PARAM_GPU_INSTRUCTION_COUNT 0x18
74#define ETNAVIV_PARAM_GPU_NUM_CONSTANTS 0x19
75#define ETNAVIV_PARAM_GPU_NUM_VARYINGS 0x1a
76#define ETNAVIV_PARAM_SOFTPIN_START_ADDR 0x1b
77
78#define ETNA_MAX_PIPES 4
79
80struct drm_etnaviv_param {
81 __u32 pipe;
82 __u32 param;
83 __u64 value;
84};
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89
90#define ETNA_BO_CACHE_MASK 0x000f0000
91
92#define ETNA_BO_CACHED 0x00010000
93#define ETNA_BO_WC 0x00020000
94#define ETNA_BO_UNCACHED 0x00040000
95
96#define ETNA_BO_FORCE_MMU 0x00100000
97
98struct drm_etnaviv_gem_new {
99 __u64 size;
100 __u32 flags;
101 __u32 handle;
102};
103
104struct drm_etnaviv_gem_info {
105 __u32 handle;
106 __u32 pad;
107 __u64 offset;
108};
109
110#define ETNA_PREP_READ 0x01
111#define ETNA_PREP_WRITE 0x02
112#define ETNA_PREP_NOSYNC 0x04
113
114struct drm_etnaviv_gem_cpu_prep {
115 __u32 handle;
116 __u32 op;
117 struct drm_etnaviv_timespec timeout;
118};
119
120struct drm_etnaviv_gem_cpu_fini {
121 __u32 handle;
122 __u32 flags;
123};
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135struct drm_etnaviv_gem_submit_reloc {
136 __u32 submit_offset;
137 __u32 reloc_idx;
138 __u64 reloc_offset;
139 __u32 flags;
140};
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158#define ETNA_SUBMIT_BO_READ 0x0001
159#define ETNA_SUBMIT_BO_WRITE 0x0002
160struct drm_etnaviv_gem_submit_bo {
161 __u32 flags;
162 __u32 handle;
163 __u64 presumed;
164};
165
166
167#define ETNA_PM_PROCESS_PRE 0x0001
168#define ETNA_PM_PROCESS_POST 0x0002
169struct drm_etnaviv_gem_submit_pmr {
170 __u32 flags;
171 __u8 domain;
172 __u8 pad;
173 __u16 signal;
174 __u32 sequence;
175 __u32 read_offset;
176 __u32 read_idx;
177};
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183#define ETNA_SUBMIT_NO_IMPLICIT 0x0001
184#define ETNA_SUBMIT_FENCE_FD_IN 0x0002
185#define ETNA_SUBMIT_FENCE_FD_OUT 0x0004
186#define ETNA_SUBMIT_SOFTPIN 0x0008
187#define ETNA_SUBMIT_FLAGS (ETNA_SUBMIT_NO_IMPLICIT | \
188 ETNA_SUBMIT_FENCE_FD_IN | \
189 ETNA_SUBMIT_FENCE_FD_OUT| \
190 ETNA_SUBMIT_SOFTPIN)
191#define ETNA_PIPE_3D 0x00
192#define ETNA_PIPE_2D 0x01
193#define ETNA_PIPE_VG 0x02
194struct drm_etnaviv_gem_submit {
195 __u32 fence;
196 __u32 pipe;
197 __u32 exec_state;
198 __u32 nr_bos;
199 __u32 nr_relocs;
200 __u32 stream_size;
201 __u64 bos;
202 __u64 relocs;
203 __u64 stream;
204 __u32 flags;
205 __s32 fence_fd;
206 __u64 pmrs;
207 __u32 nr_pmrs;
208 __u32 pad;
209};
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218#define ETNA_WAIT_NONBLOCK 0x01
219struct drm_etnaviv_wait_fence {
220 __u32 pipe;
221 __u32 fence;
222 __u32 flags;
223 __u32 pad;
224 struct drm_etnaviv_timespec timeout;
225};
226
227#define ETNA_USERPTR_READ 0x01
228#define ETNA_USERPTR_WRITE 0x02
229struct drm_etnaviv_gem_userptr {
230 __u64 user_ptr;
231 __u64 user_size;
232 __u32 flags;
233 __u32 handle;
234};
235
236struct drm_etnaviv_gem_wait {
237 __u32 pipe;
238 __u32 handle;
239 __u32 flags;
240 __u32 pad;
241 struct drm_etnaviv_timespec timeout;
242};
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248struct drm_etnaviv_pm_domain {
249 __u32 pipe;
250 __u8 iter;
251 __u8 id;
252 __u16 nr_signals;
253 char name[64];
254};
255
256struct drm_etnaviv_pm_signal {
257 __u32 pipe;
258 __u8 domain;
259 __u8 pad;
260 __u16 iter;
261 __u16 id;
262 char name[64];
263};
264
265#define DRM_ETNAVIV_GET_PARAM 0x00
266
267
268
269#define DRM_ETNAVIV_GEM_NEW 0x02
270#define DRM_ETNAVIV_GEM_INFO 0x03
271#define DRM_ETNAVIV_GEM_CPU_PREP 0x04
272#define DRM_ETNAVIV_GEM_CPU_FINI 0x05
273#define DRM_ETNAVIV_GEM_SUBMIT 0x06
274#define DRM_ETNAVIV_WAIT_FENCE 0x07
275#define DRM_ETNAVIV_GEM_USERPTR 0x08
276#define DRM_ETNAVIV_GEM_WAIT 0x09
277#define DRM_ETNAVIV_PM_QUERY_DOM 0x0a
278#define DRM_ETNAVIV_PM_QUERY_SIG 0x0b
279#define DRM_ETNAVIV_NUM_IOCTLS 0x0c
280
281#define DRM_IOCTL_ETNAVIV_GET_PARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GET_PARAM, struct drm_etnaviv_param)
282#define DRM_IOCTL_ETNAVIV_GEM_NEW DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_NEW, struct drm_etnaviv_gem_new)
283#define DRM_IOCTL_ETNAVIV_GEM_INFO DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_INFO, struct drm_etnaviv_gem_info)
284#define DRM_IOCTL_ETNAVIV_GEM_CPU_PREP DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_PREP, struct drm_etnaviv_gem_cpu_prep)
285#define DRM_IOCTL_ETNAVIV_GEM_CPU_FINI DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_CPU_FINI, struct drm_etnaviv_gem_cpu_fini)
286#define DRM_IOCTL_ETNAVIV_GEM_SUBMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_SUBMIT, struct drm_etnaviv_gem_submit)
287#define DRM_IOCTL_ETNAVIV_WAIT_FENCE DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_WAIT_FENCE, struct drm_etnaviv_wait_fence)
288#define DRM_IOCTL_ETNAVIV_GEM_USERPTR DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_USERPTR, struct drm_etnaviv_gem_userptr)
289#define DRM_IOCTL_ETNAVIV_GEM_WAIT DRM_IOW(DRM_COMMAND_BASE + DRM_ETNAVIV_GEM_WAIT, struct drm_etnaviv_gem_wait)
290#define DRM_IOCTL_ETNAVIV_PM_QUERY_DOM DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_DOM, struct drm_etnaviv_pm_domain)
291#define DRM_IOCTL_ETNAVIV_PM_QUERY_SIG DRM_IOWR(DRM_COMMAND_BASE + DRM_ETNAVIV_PM_QUERY_SIG, struct drm_etnaviv_pm_signal)
292
293#if defined(__cplusplus)
294}
295#endif
296
297#endif
298