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23#ifndef KFD_IOCTL_H_INCLUDED
24#define KFD_IOCTL_H_INCLUDED
25
26#include <drm/drm.h>
27#include <linux/ioctl.h>
28
29
30
31
32
33#define KFD_IOCTL_MAJOR_VERSION 1
34#define KFD_IOCTL_MINOR_VERSION 3
35
36struct kfd_ioctl_get_version_args {
37 __u32 major_version;
38 __u32 minor_version;
39};
40
41
42#define KFD_IOC_QUEUE_TYPE_COMPUTE 0x0
43#define KFD_IOC_QUEUE_TYPE_SDMA 0x1
44#define KFD_IOC_QUEUE_TYPE_COMPUTE_AQL 0x2
45#define KFD_IOC_QUEUE_TYPE_SDMA_XGMI 0x3
46
47#define KFD_MAX_QUEUE_PERCENTAGE 100
48#define KFD_MAX_QUEUE_PRIORITY 15
49
50struct kfd_ioctl_create_queue_args {
51 __u64 ring_base_address;
52 __u64 write_pointer_address;
53 __u64 read_pointer_address;
54 __u64 doorbell_offset;
55
56 __u32 ring_size;
57 __u32 gpu_id;
58 __u32 queue_type;
59 __u32 queue_percentage;
60 __u32 queue_priority;
61 __u32 queue_id;
62
63 __u64 eop_buffer_address;
64 __u64 eop_buffer_size;
65 __u64 ctx_save_restore_address;
66 __u32 ctx_save_restore_size;
67 __u32 ctl_stack_size;
68};
69
70struct kfd_ioctl_destroy_queue_args {
71 __u32 queue_id;
72 __u32 pad;
73};
74
75struct kfd_ioctl_update_queue_args {
76 __u64 ring_base_address;
77
78 __u32 queue_id;
79 __u32 ring_size;
80 __u32 queue_percentage;
81 __u32 queue_priority;
82};
83
84struct kfd_ioctl_set_cu_mask_args {
85 __u32 queue_id;
86 __u32 num_cu_mask;
87 __u64 cu_mask_ptr;
88};
89
90struct kfd_ioctl_get_queue_wave_state_args {
91 __u64 ctl_stack_address;
92 __u32 ctl_stack_used_size;
93 __u32 save_area_used_size;
94 __u32 queue_id;
95 __u32 pad;
96};
97
98
99#define KFD_IOC_CACHE_POLICY_COHERENT 0
100#define KFD_IOC_CACHE_POLICY_NONCOHERENT 1
101
102struct kfd_ioctl_set_memory_policy_args {
103 __u64 alternate_aperture_base;
104 __u64 alternate_aperture_size;
105
106 __u32 gpu_id;
107 __u32 default_policy;
108 __u32 alternate_policy;
109 __u32 pad;
110};
111
112
113
114
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116
117
118
119struct kfd_ioctl_get_clock_counters_args {
120 __u64 gpu_clock_counter;
121 __u64 cpu_clock_counter;
122 __u64 system_clock_counter;
123 __u64 system_clock_freq;
124
125 __u32 gpu_id;
126 __u32 pad;
127};
128
129struct kfd_process_device_apertures {
130 __u64 lds_base;
131 __u64 lds_limit;
132 __u64 scratch_base;
133 __u64 scratch_limit;
134 __u64 gpuvm_base;
135 __u64 gpuvm_limit;
136 __u32 gpu_id;
137 __u32 pad;
138};
139
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141
142
143
144
145#define NUM_OF_SUPPORTED_GPUS 7
146struct kfd_ioctl_get_process_apertures_args {
147 struct kfd_process_device_apertures
148 process_apertures[NUM_OF_SUPPORTED_GPUS];
149
150
151 __u32 num_of_nodes;
152 __u32 pad;
153};
154
155struct kfd_ioctl_get_process_apertures_new_args {
156
157
158
159 __u64 kfd_process_device_apertures_ptr;
160
161
162
163
164 __u32 num_of_nodes;
165 __u32 pad;
166};
167
168#define MAX_ALLOWED_NUM_POINTS 100
169#define MAX_ALLOWED_AW_BUFF_SIZE 4096
170#define MAX_ALLOWED_WAC_BUFF_SIZE 128
171
172struct kfd_ioctl_dbg_register_args {
173 __u32 gpu_id;
174 __u32 pad;
175};
176
177struct kfd_ioctl_dbg_unregister_args {
178 __u32 gpu_id;
179 __u32 pad;
180};
181
182struct kfd_ioctl_dbg_address_watch_args {
183 __u64 content_ptr;
184 __u32 gpu_id;
185 __u32 buf_size_in_bytes;
186};
187
188struct kfd_ioctl_dbg_wave_control_args {
189 __u64 content_ptr;
190 __u32 gpu_id;
191 __u32 buf_size_in_bytes;
192};
193
194
195#define KFD_IOC_EVENT_SIGNAL 0
196#define KFD_IOC_EVENT_NODECHANGE 1
197#define KFD_IOC_EVENT_DEVICESTATECHANGE 2
198#define KFD_IOC_EVENT_HW_EXCEPTION 3
199#define KFD_IOC_EVENT_SYSTEM_EVENT 4
200#define KFD_IOC_EVENT_DEBUG_EVENT 5
201#define KFD_IOC_EVENT_PROFILE_EVENT 6
202#define KFD_IOC_EVENT_QUEUE_EVENT 7
203#define KFD_IOC_EVENT_MEMORY 8
204
205#define KFD_IOC_WAIT_RESULT_COMPLETE 0
206#define KFD_IOC_WAIT_RESULT_TIMEOUT 1
207#define KFD_IOC_WAIT_RESULT_FAIL 2
208
209#define KFD_SIGNAL_EVENT_LIMIT 4096
210
211
212#define KFD_HW_EXCEPTION_WHOLE_GPU_RESET 0
213#define KFD_HW_EXCEPTION_PER_ENGINE_RESET 1
214
215
216#define KFD_HW_EXCEPTION_GPU_HANG 0
217#define KFD_HW_EXCEPTION_ECC 1
218
219
220#define KFD_MEM_ERR_NO_RAS 0
221#define KFD_MEM_ERR_SRAM_ECC 1
222#define KFD_MEM_ERR_POISON_CONSUMED 2
223#define KFD_MEM_ERR_GPU_HANG 3
224
225struct kfd_ioctl_create_event_args {
226 __u64 event_page_offset;
227 __u32 event_trigger_data;
228 __u32 event_type;
229 __u32 auto_reset;
230 __u32 node_id;
231
232 __u32 event_id;
233 __u32 event_slot_index;
234};
235
236struct kfd_ioctl_destroy_event_args {
237 __u32 event_id;
238 __u32 pad;
239};
240
241struct kfd_ioctl_set_event_args {
242 __u32 event_id;
243 __u32 pad;
244};
245
246struct kfd_ioctl_reset_event_args {
247 __u32 event_id;
248 __u32 pad;
249};
250
251struct kfd_memory_exception_failure {
252 __u32 NotPresent;
253 __u32 ReadOnly;
254 __u32 NoExecute;
255 __u32 imprecise;
256};
257
258
259struct kfd_hsa_memory_exception_data {
260 struct kfd_memory_exception_failure failure;
261 __u64 va;
262 __u32 gpu_id;
263 __u32 ErrorType;
264
265
266
267
268
269};
270
271
272struct kfd_hsa_hw_exception_data {
273 __u32 reset_type;
274 __u32 reset_cause;
275 __u32 memory_lost;
276 __u32 gpu_id;
277};
278
279
280struct kfd_event_data {
281 union {
282 struct kfd_hsa_memory_exception_data memory_exception_data;
283 struct kfd_hsa_hw_exception_data hw_exception_data;
284 };
285 __u64 kfd_event_data_ext;
286
287 __u32 event_id;
288 __u32 pad;
289};
290
291struct kfd_ioctl_wait_events_args {
292 __u64 events_ptr;
293
294 __u32 num_events;
295 __u32 wait_for_all;
296 __u32 timeout;
297 __u32 wait_result;
298};
299
300struct kfd_ioctl_set_scratch_backing_va_args {
301 __u64 va_addr;
302 __u32 gpu_id;
303 __u32 pad;
304};
305
306struct kfd_ioctl_get_tile_config_args {
307
308 __u64 tile_config_ptr;
309
310 __u64 macro_tile_config_ptr;
311
312
313
314 __u32 num_tile_configs;
315
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317
318 __u32 num_macro_tile_configs;
319
320 __u32 gpu_id;
321 __u32 gb_addr_config;
322 __u32 num_banks;
323 __u32 num_ranks;
324
325
326
327};
328
329struct kfd_ioctl_set_trap_handler_args {
330 __u64 tba_addr;
331 __u64 tma_addr;
332 __u32 gpu_id;
333 __u32 pad;
334};
335
336struct kfd_ioctl_acquire_vm_args {
337 __u32 drm_fd;
338 __u32 gpu_id;
339};
340
341
342#define KFD_IOC_ALLOC_MEM_FLAGS_VRAM (1 << 0)
343#define KFD_IOC_ALLOC_MEM_FLAGS_GTT (1 << 1)
344#define KFD_IOC_ALLOC_MEM_FLAGS_USERPTR (1 << 2)
345#define KFD_IOC_ALLOC_MEM_FLAGS_DOORBELL (1 << 3)
346#define KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP (1 << 4)
347
348#define KFD_IOC_ALLOC_MEM_FLAGS_WRITABLE (1 << 31)
349#define KFD_IOC_ALLOC_MEM_FLAGS_EXECUTABLE (1 << 30)
350#define KFD_IOC_ALLOC_MEM_FLAGS_PUBLIC (1 << 29)
351#define KFD_IOC_ALLOC_MEM_FLAGS_NO_SUBSTITUTE (1 << 28)
352#define KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM (1 << 27)
353#define KFD_IOC_ALLOC_MEM_FLAGS_COHERENT (1 << 26)
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366
367struct kfd_ioctl_alloc_memory_of_gpu_args {
368 __u64 va_addr;
369 __u64 size;
370 __u64 handle;
371 __u64 mmap_offset;
372 __u32 gpu_id;
373 __u32 flags;
374};
375
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379
380struct kfd_ioctl_free_memory_of_gpu_args {
381 __u64 handle;
382};
383
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398
399struct kfd_ioctl_map_memory_to_gpu_args {
400 __u64 handle;
401 __u64 device_ids_array_ptr;
402 __u32 n_devices;
403 __u32 n_success;
404};
405
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409
410struct kfd_ioctl_unmap_memory_from_gpu_args {
411 __u64 handle;
412 __u64 device_ids_array_ptr;
413 __u32 n_devices;
414 __u32 n_success;
415};
416
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422
423
424struct kfd_ioctl_alloc_queue_gws_args {
425 __u32 queue_id;
426 __u32 num_gws;
427 __u32 first_gws;
428 __u32 pad;
429};
430
431struct kfd_ioctl_get_dmabuf_info_args {
432 __u64 size;
433 __u64 metadata_ptr;
434 __u32 metadata_size;
435
436
437 __u32 gpu_id;
438 __u32 flags;
439 __u32 dmabuf_fd;
440};
441
442struct kfd_ioctl_import_dmabuf_args {
443 __u64 va_addr;
444 __u64 handle;
445 __u32 gpu_id;
446 __u32 dmabuf_fd;
447};
448
449
450
451
452
453#define KFD_SMI_EVENT_VMFAULT 0x0000000000000001
454
455struct kfd_ioctl_smi_events_args {
456 __u32 gpuid;
457 __u32 anon_fd;
458};
459
460
461
462enum kfd_mmio_remap {
463 KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL = 0,
464 KFD_MMIO_REMAP_HDP_REG_FLUSH_CNTL = 4,
465};
466
467#define AMDKFD_IOCTL_BASE 'K'
468#define AMDKFD_IO(nr) _IO(AMDKFD_IOCTL_BASE, nr)
469#define AMDKFD_IOR(nr, type) _IOR(AMDKFD_IOCTL_BASE, nr, type)
470#define AMDKFD_IOW(nr, type) _IOW(AMDKFD_IOCTL_BASE, nr, type)
471#define AMDKFD_IOWR(nr, type) _IOWR(AMDKFD_IOCTL_BASE, nr, type)
472
473#define AMDKFD_IOC_GET_VERSION \
474 AMDKFD_IOR(0x01, struct kfd_ioctl_get_version_args)
475
476#define AMDKFD_IOC_CREATE_QUEUE \
477 AMDKFD_IOWR(0x02, struct kfd_ioctl_create_queue_args)
478
479#define AMDKFD_IOC_DESTROY_QUEUE \
480 AMDKFD_IOWR(0x03, struct kfd_ioctl_destroy_queue_args)
481
482#define AMDKFD_IOC_SET_MEMORY_POLICY \
483 AMDKFD_IOW(0x04, struct kfd_ioctl_set_memory_policy_args)
484
485#define AMDKFD_IOC_GET_CLOCK_COUNTERS \
486 AMDKFD_IOWR(0x05, struct kfd_ioctl_get_clock_counters_args)
487
488#define AMDKFD_IOC_GET_PROCESS_APERTURES \
489 AMDKFD_IOR(0x06, struct kfd_ioctl_get_process_apertures_args)
490
491#define AMDKFD_IOC_UPDATE_QUEUE \
492 AMDKFD_IOW(0x07, struct kfd_ioctl_update_queue_args)
493
494#define AMDKFD_IOC_CREATE_EVENT \
495 AMDKFD_IOWR(0x08, struct kfd_ioctl_create_event_args)
496
497#define AMDKFD_IOC_DESTROY_EVENT \
498 AMDKFD_IOW(0x09, struct kfd_ioctl_destroy_event_args)
499
500#define AMDKFD_IOC_SET_EVENT \
501 AMDKFD_IOW(0x0A, struct kfd_ioctl_set_event_args)
502
503#define AMDKFD_IOC_RESET_EVENT \
504 AMDKFD_IOW(0x0B, struct kfd_ioctl_reset_event_args)
505
506#define AMDKFD_IOC_WAIT_EVENTS \
507 AMDKFD_IOWR(0x0C, struct kfd_ioctl_wait_events_args)
508
509#define AMDKFD_IOC_DBG_REGISTER \
510 AMDKFD_IOW(0x0D, struct kfd_ioctl_dbg_register_args)
511
512#define AMDKFD_IOC_DBG_UNREGISTER \
513 AMDKFD_IOW(0x0E, struct kfd_ioctl_dbg_unregister_args)
514
515#define AMDKFD_IOC_DBG_ADDRESS_WATCH \
516 AMDKFD_IOW(0x0F, struct kfd_ioctl_dbg_address_watch_args)
517
518#define AMDKFD_IOC_DBG_WAVE_CONTROL \
519 AMDKFD_IOW(0x10, struct kfd_ioctl_dbg_wave_control_args)
520
521#define AMDKFD_IOC_SET_SCRATCH_BACKING_VA \
522 AMDKFD_IOWR(0x11, struct kfd_ioctl_set_scratch_backing_va_args)
523
524#define AMDKFD_IOC_GET_TILE_CONFIG \
525 AMDKFD_IOWR(0x12, struct kfd_ioctl_get_tile_config_args)
526
527#define AMDKFD_IOC_SET_TRAP_HANDLER \
528 AMDKFD_IOW(0x13, struct kfd_ioctl_set_trap_handler_args)
529
530#define AMDKFD_IOC_GET_PROCESS_APERTURES_NEW \
531 AMDKFD_IOWR(0x14, \
532 struct kfd_ioctl_get_process_apertures_new_args)
533
534#define AMDKFD_IOC_ACQUIRE_VM \
535 AMDKFD_IOW(0x15, struct kfd_ioctl_acquire_vm_args)
536
537#define AMDKFD_IOC_ALLOC_MEMORY_OF_GPU \
538 AMDKFD_IOWR(0x16, struct kfd_ioctl_alloc_memory_of_gpu_args)
539
540#define AMDKFD_IOC_FREE_MEMORY_OF_GPU \
541 AMDKFD_IOW(0x17, struct kfd_ioctl_free_memory_of_gpu_args)
542
543#define AMDKFD_IOC_MAP_MEMORY_TO_GPU \
544 AMDKFD_IOWR(0x18, struct kfd_ioctl_map_memory_to_gpu_args)
545
546#define AMDKFD_IOC_UNMAP_MEMORY_FROM_GPU \
547 AMDKFD_IOWR(0x19, struct kfd_ioctl_unmap_memory_from_gpu_args)
548
549#define AMDKFD_IOC_SET_CU_MASK \
550 AMDKFD_IOW(0x1A, struct kfd_ioctl_set_cu_mask_args)
551
552#define AMDKFD_IOC_GET_QUEUE_WAVE_STATE \
553 AMDKFD_IOWR(0x1B, struct kfd_ioctl_get_queue_wave_state_args)
554
555#define AMDKFD_IOC_GET_DMABUF_INFO \
556 AMDKFD_IOWR(0x1C, struct kfd_ioctl_get_dmabuf_info_args)
557
558#define AMDKFD_IOC_IMPORT_DMABUF \
559 AMDKFD_IOWR(0x1D, struct kfd_ioctl_import_dmabuf_args)
560
561#define AMDKFD_IOC_ALLOC_QUEUE_GWS \
562 AMDKFD_IOWR(0x1E, struct kfd_ioctl_alloc_queue_gws_args)
563
564#define AMDKFD_IOC_SMI_EVENTS \
565 AMDKFD_IOWR(0x1F, struct kfd_ioctl_smi_events_args)
566
567#define AMDKFD_COMMAND_START 0x01
568#define AMDKFD_COMMAND_END 0x20
569
570#endif
571