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9
10#include <linux/init.h>
11#include <linux/delay.h>
12#include <linux/interrupt.h>
13#include <linux/pci.h>
14#include <linux/firmware.h>
15#include <linux/module.h>
16#include <linux/math64.h>
17#include <linux/vmalloc.h>
18#include <linux/io.h>
19#include <linux/nospec.h>
20
21#include <sound/core.h>
22#include <sound/control.h>
23#include <sound/pcm.h>
24#include <sound/info.h>
25#include <sound/asoundef.h>
26#include <sound/rawmidi.h>
27#include <sound/hwdep.h>
28#include <sound/initval.h>
29#include <sound/hdsp.h>
30
31#include <asm/byteorder.h>
32#include <asm/current.h>
33
34static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
35static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
36static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
37
38module_param_array(index, int, NULL, 0444);
39MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
40module_param_array(id, charp, NULL, 0444);
41MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
42module_param_array(enable, bool, NULL, 0444);
43MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
44MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
45MODULE_DESCRIPTION("RME Hammerfall DSP");
46MODULE_LICENSE("GPL");
47MODULE_SUPPORTED_DEVICE("{{RME Hammerfall-DSP},"
48 "{RME HDSP-9652},"
49 "{RME HDSP-9632}}");
50MODULE_FIRMWARE("rpm_firmware.bin");
51MODULE_FIRMWARE("multiface_firmware.bin");
52MODULE_FIRMWARE("multiface_firmware_rev11.bin");
53MODULE_FIRMWARE("digiface_firmware.bin");
54MODULE_FIRMWARE("digiface_firmware_rev11.bin");
55
56#define HDSP_MAX_CHANNELS 26
57#define HDSP_MAX_DS_CHANNELS 14
58#define HDSP_MAX_QS_CHANNELS 8
59#define DIGIFACE_SS_CHANNELS 26
60#define DIGIFACE_DS_CHANNELS 14
61#define MULTIFACE_SS_CHANNELS 18
62#define MULTIFACE_DS_CHANNELS 14
63#define H9652_SS_CHANNELS 26
64#define H9652_DS_CHANNELS 14
65
66
67
68#define H9632_SS_CHANNELS 12
69#define H9632_DS_CHANNELS 8
70#define H9632_QS_CHANNELS 4
71#define RPM_CHANNELS 6
72
73
74
75#define HDSP_resetPointer 0
76#define HDSP_freqReg 0
77#define HDSP_outputBufferAddress 32
78#define HDSP_inputBufferAddress 36
79#define HDSP_controlRegister 64
80#define HDSP_interruptConfirmation 96
81#define HDSP_outputEnable 128
82#define HDSP_control2Reg 256
83#define HDSP_midiDataOut0 352
84#define HDSP_midiDataOut1 356
85#define HDSP_fifoData 368
86#define HDSP_inputEnable 384
87
88
89
90
91#define HDSP_statusRegister 0
92#define HDSP_timecode 128
93#define HDSP_status2Register 192
94#define HDSP_midiDataIn0 360
95#define HDSP_midiDataIn1 364
96#define HDSP_midiStatusOut0 384
97#define HDSP_midiStatusOut1 388
98#define HDSP_midiStatusIn0 392
99#define HDSP_midiStatusIn1 396
100#define HDSP_fifoStatus 400
101
102
103
104
105
106
107
108#define HDSP_playbackPeakLevel 4096
109#define HDSP_inputPeakLevel 4224
110#define HDSP_outputPeakLevel 4352
111#define HDSP_playbackRmsLevel 4612
112#define HDSP_inputRmsLevel 4868
113
114
115
116
117
118
119
120
121
122#define HDSP_9652_peakBase 7164
123#define HDSP_9652_rmsBase 4096
124
125
126#define HDSP_9632_metersBase 4096
127
128#define HDSP_IO_EXTENT 7168
129
130
131
132#define HDSP_TMS 0x01
133#define HDSP_TCK 0x02
134#define HDSP_TDI 0x04
135#define HDSP_JTAG 0x08
136#define HDSP_PWDN 0x10
137#define HDSP_PROGRAM 0x020
138#define HDSP_CONFIG_MODE_0 0x040
139#define HDSP_CONFIG_MODE_1 0x080
140#define HDSP_VERSION_BIT (0x100 | HDSP_S_LOAD)
141#define HDSP_BIGENDIAN_MODE 0x200
142#define HDSP_RD_MULTIPLE 0x400
143#define HDSP_9652_ENABLE_MIXER 0x800
144#define HDSP_S200 0x800
145#define HDSP_S300 (0x100 | HDSP_S200)
146#define HDSP_CYCLIC_MODE 0x1000
147#define HDSP_TDO 0x10000000
148
149#define HDSP_S_PROGRAM (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
150#define HDSP_S_LOAD (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)
151
152
153
154#define HDSP_Start (1<<0)
155#define HDSP_Latency0 (1<<1)
156#define HDSP_Latency1 (1<<2)
157#define HDSP_Latency2 (1<<3)
158#define HDSP_ClockModeMaster (1<<4)
159#define HDSP_AudioInterruptEnable (1<<5)
160#define HDSP_Frequency0 (1<<6)
161#define HDSP_Frequency1 (1<<7)
162#define HDSP_DoubleSpeed (1<<8)
163#define HDSP_SPDIFProfessional (1<<9)
164#define HDSP_SPDIFEmphasis (1<<10)
165#define HDSP_SPDIFNonAudio (1<<11)
166#define HDSP_SPDIFOpticalOut (1<<12)
167#define HDSP_SyncRef2 (1<<13)
168#define HDSP_SPDIFInputSelect0 (1<<14)
169#define HDSP_SPDIFInputSelect1 (1<<15)
170#define HDSP_SyncRef0 (1<<16)
171#define HDSP_SyncRef1 (1<<17)
172#define HDSP_AnalogExtensionBoard (1<<18)
173#define HDSP_XLRBreakoutCable (1<<20)
174#define HDSP_Midi0InterruptEnable (1<<22)
175#define HDSP_Midi1InterruptEnable (1<<23)
176#define HDSP_LineOut (1<<24)
177#define HDSP_ADGain0 (1<<25)
178#define HDSP_ADGain1 (1<<26)
179#define HDSP_DAGain0 (1<<27)
180#define HDSP_DAGain1 (1<<28)
181#define HDSP_PhoneGain0 (1<<29)
182#define HDSP_PhoneGain1 (1<<30)
183#define HDSP_QuadSpeed (1<<31)
184
185
186#define HDSP_RPM_Inp12 0x04A00
187#define HDSP_RPM_Inp12_Phon_6dB 0x00800
188#define HDSP_RPM_Inp12_Phon_0dB 0x00000
189#define HDSP_RPM_Inp12_Phon_n6dB 0x04000
190#define HDSP_RPM_Inp12_Line_0dB 0x04200
191#define HDSP_RPM_Inp12_Line_n6dB 0x00200
192
193#define HDSP_RPM_Inp34 0x32000
194#define HDSP_RPM_Inp34_Phon_6dB 0x20000
195#define HDSP_RPM_Inp34_Phon_0dB 0x00000
196#define HDSP_RPM_Inp34_Phon_n6dB 0x02000
197#define HDSP_RPM_Inp34_Line_0dB 0x30000
198#define HDSP_RPM_Inp34_Line_n6dB 0x10000
199
200#define HDSP_RPM_Bypass 0x01000
201
202#define HDSP_RPM_Disconnect 0x00001
203
204#define HDSP_ADGainMask (HDSP_ADGain0|HDSP_ADGain1)
205#define HDSP_ADGainMinus10dBV HDSP_ADGainMask
206#define HDSP_ADGainPlus4dBu (HDSP_ADGain0)
207#define HDSP_ADGainLowGain 0
208
209#define HDSP_DAGainMask (HDSP_DAGain0|HDSP_DAGain1)
210#define HDSP_DAGainHighGain HDSP_DAGainMask
211#define HDSP_DAGainPlus4dBu (HDSP_DAGain0)
212#define HDSP_DAGainMinus10dBV 0
213
214#define HDSP_PhoneGainMask (HDSP_PhoneGain0|HDSP_PhoneGain1)
215#define HDSP_PhoneGain0dB HDSP_PhoneGainMask
216#define HDSP_PhoneGainMinus6dB (HDSP_PhoneGain0)
217#define HDSP_PhoneGainMinus12dB 0
218
219#define HDSP_LatencyMask (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
220#define HDSP_FrequencyMask (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)
221
222#define HDSP_SPDIFInputMask (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
223#define HDSP_SPDIFInputADAT1 0
224#define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
225#define HDSP_SPDIFInputCdrom (HDSP_SPDIFInputSelect1)
226#define HDSP_SPDIFInputAES (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
227
228#define HDSP_SyncRefMask (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
229#define HDSP_SyncRef_ADAT1 0
230#define HDSP_SyncRef_ADAT2 (HDSP_SyncRef0)
231#define HDSP_SyncRef_ADAT3 (HDSP_SyncRef1)
232#define HDSP_SyncRef_SPDIF (HDSP_SyncRef0|HDSP_SyncRef1)
233#define HDSP_SyncRef_WORD (HDSP_SyncRef2)
234#define HDSP_SyncRef_ADAT_SYNC (HDSP_SyncRef0|HDSP_SyncRef2)
235
236
237
238#define HDSP_CLOCK_SOURCE_AUTOSYNC 0
239#define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ 1
240#define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ 2
241#define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ 3
242#define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ 4
243#define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ 5
244#define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ 6
245#define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ 7
246#define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ 8
247#define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ 9
248
249
250
251#define HDSP_SYNC_FROM_WORD 0
252#define HDSP_SYNC_FROM_SPDIF 1
253#define HDSP_SYNC_FROM_ADAT1 2
254#define HDSP_SYNC_FROM_ADAT_SYNC 3
255#define HDSP_SYNC_FROM_ADAT2 4
256#define HDSP_SYNC_FROM_ADAT3 5
257
258
259
260#define HDSP_SYNC_CHECK_NO_LOCK 0
261#define HDSP_SYNC_CHECK_LOCK 1
262#define HDSP_SYNC_CHECK_SYNC 2
263
264
265
266#define HDSP_AUTOSYNC_FROM_WORD 0
267#define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
268#define HDSP_AUTOSYNC_FROM_SPDIF 2
269#define HDSP_AUTOSYNC_FROM_NONE 3
270#define HDSP_AUTOSYNC_FROM_ADAT1 4
271#define HDSP_AUTOSYNC_FROM_ADAT2 5
272#define HDSP_AUTOSYNC_FROM_ADAT3 6
273
274
275
276#define HDSP_SPDIFIN_OPTICAL 0
277#define HDSP_SPDIFIN_COAXIAL 1
278#define HDSP_SPDIFIN_INTERNAL 2
279#define HDSP_SPDIFIN_AES 3
280
281#define HDSP_Frequency32KHz HDSP_Frequency0
282#define HDSP_Frequency44_1KHz HDSP_Frequency1
283#define HDSP_Frequency48KHz (HDSP_Frequency1|HDSP_Frequency0)
284#define HDSP_Frequency64KHz (HDSP_DoubleSpeed|HDSP_Frequency0)
285#define HDSP_Frequency88_2KHz (HDSP_DoubleSpeed|HDSP_Frequency1)
286#define HDSP_Frequency96KHz (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
287
288#define HDSP_Frequency128KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
289#define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
290#define HDSP_Frequency192KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
291
292
293
294
295#define DDS_NUMERATOR 104857600000000ULL;
296
297#define hdsp_encode_latency(x) (((x)<<1) & HDSP_LatencyMask)
298#define hdsp_decode_latency(x) (((x) & HDSP_LatencyMask)>>1)
299
300#define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
301#define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)
302
303
304
305#define HDSP_audioIRQPending (1<<0)
306#define HDSP_Lock2 (1<<1)
307#define HDSP_spdifFrequency3 HDSP_Lock2
308#define HDSP_Lock1 (1<<2)
309#define HDSP_Lock0 (1<<3)
310#define HDSP_SPDIFSync (1<<4)
311#define HDSP_TimecodeLock (1<<5)
312#define HDSP_BufferPositionMask 0x000FFC0
313#define HDSP_Sync2 (1<<16)
314#define HDSP_Sync1 (1<<17)
315#define HDSP_Sync0 (1<<18)
316#define HDSP_DoubleSpeedStatus (1<<19)
317#define HDSP_ConfigError (1<<20)
318#define HDSP_DllError (1<<21)
319#define HDSP_spdifFrequency0 (1<<22)
320#define HDSP_spdifFrequency1 (1<<23)
321#define HDSP_spdifFrequency2 (1<<24)
322#define HDSP_SPDIFErrorFlag (1<<25)
323#define HDSP_BufferID (1<<26)
324#define HDSP_TimecodeSync (1<<27)
325#define HDSP_AEBO (1<<28)
326#define HDSP_AEBI (1<<29)
327#define HDSP_midi0IRQPending (1<<30)
328#define HDSP_midi1IRQPending (1<<31)
329
330#define HDSP_spdifFrequencyMask (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
331#define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
332 HDSP_spdifFrequency1|\
333 HDSP_spdifFrequency2|\
334 HDSP_spdifFrequency3)
335
336#define HDSP_spdifFrequency32KHz (HDSP_spdifFrequency0)
337#define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
338#define HDSP_spdifFrequency48KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency1)
339
340#define HDSP_spdifFrequency64KHz (HDSP_spdifFrequency2)
341#define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
342#define HDSP_spdifFrequency96KHz (HDSP_spdifFrequency2|HDSP_spdifFrequency1)
343
344
345#define HDSP_spdifFrequency128KHz (HDSP_spdifFrequency0|\
346 HDSP_spdifFrequency1|\
347 HDSP_spdifFrequency2)
348#define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
349#define HDSP_spdifFrequency192KHz (HDSP_spdifFrequency3|HDSP_spdifFrequency0)
350
351
352
353#define HDSP_version0 (1<<0)
354#define HDSP_version1 (1<<1)
355#define HDSP_version2 (1<<2)
356#define HDSP_wc_lock (1<<3)
357#define HDSP_wc_sync (1<<4)
358#define HDSP_inp_freq0 (1<<5)
359#define HDSP_inp_freq1 (1<<6)
360#define HDSP_inp_freq2 (1<<7)
361#define HDSP_SelSyncRef0 (1<<8)
362#define HDSP_SelSyncRef1 (1<<9)
363#define HDSP_SelSyncRef2 (1<<10)
364
365#define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)
366
367#define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
368#define HDSP_systemFrequency32 (HDSP_inp_freq0)
369#define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
370#define HDSP_systemFrequency48 (HDSP_inp_freq0|HDSP_inp_freq1)
371#define HDSP_systemFrequency64 (HDSP_inp_freq2)
372#define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
373#define HDSP_systemFrequency96 (HDSP_inp_freq1|HDSP_inp_freq2)
374
375
376#define HDSP_SelSyncRefMask (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
377#define HDSP_SelSyncRef_ADAT1 0
378#define HDSP_SelSyncRef_ADAT2 (HDSP_SelSyncRef0)
379#define HDSP_SelSyncRef_ADAT3 (HDSP_SelSyncRef1)
380#define HDSP_SelSyncRef_SPDIF (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
381#define HDSP_SelSyncRef_WORD (HDSP_SelSyncRef2)
382#define HDSP_SelSyncRef_ADAT_SYNC (HDSP_SelSyncRef0|HDSP_SelSyncRef2)
383
384
385
386#define HDSP_InitializationComplete (1<<0)
387#define HDSP_FirmwareLoaded (1<<1)
388#define HDSP_FirmwareCached (1<<2)
389
390
391
392#define HDSP_LONG_WAIT 5000
393#define HDSP_SHORT_WAIT 30
394
395#define UNITY_GAIN 32768
396#define MINUS_INFINITY_GAIN 0
397
398
399
400#define HDSP_CHANNEL_BUFFER_SAMPLES (16*1024)
401#define HDSP_CHANNEL_BUFFER_BYTES (4*HDSP_CHANNEL_BUFFER_SAMPLES)
402
403
404
405
406
407
408
409
410
411
412#define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
413#define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)
414
415#define HDSP_FIRMWARE_SIZE (24413 * 4)
416
417struct hdsp_9632_meters {
418 u32 input_peak[16];
419 u32 playback_peak[16];
420 u32 output_peak[16];
421 u32 xxx_peak[16];
422 u32 padding[64];
423 u32 input_rms_low[16];
424 u32 playback_rms_low[16];
425 u32 output_rms_low[16];
426 u32 xxx_rms_low[16];
427 u32 input_rms_high[16];
428 u32 playback_rms_high[16];
429 u32 output_rms_high[16];
430 u32 xxx_rms_high[16];
431};
432
433struct hdsp_midi {
434 struct hdsp *hdsp;
435 int id;
436 struct snd_rawmidi *rmidi;
437 struct snd_rawmidi_substream *input;
438 struct snd_rawmidi_substream *output;
439 char istimer;
440 struct timer_list timer;
441 spinlock_t lock;
442 int pending;
443};
444
445struct hdsp {
446 spinlock_t lock;
447 struct snd_pcm_substream *capture_substream;
448 struct snd_pcm_substream *playback_substream;
449 struct hdsp_midi midi[2];
450 struct tasklet_struct midi_tasklet;
451 int use_midi_tasklet;
452 int precise_ptr;
453 u32 control_register;
454 u32 control2_register;
455 u32 creg_spdif;
456 u32 creg_spdif_stream;
457 int clock_source_locked;
458 char *card_name;
459 enum HDSP_IO_Type io_type;
460 unsigned short firmware_rev;
461 unsigned short state;
462 const struct firmware *firmware;
463 u32 *fw_uploaded;
464 size_t period_bytes;
465 unsigned char max_channels;
466 unsigned char qs_in_channels;
467 unsigned char ds_in_channels;
468 unsigned char ss_in_channels;
469 unsigned char qs_out_channels;
470 unsigned char ds_out_channels;
471 unsigned char ss_out_channels;
472
473 struct snd_dma_buffer capture_dma_buf;
474 struct snd_dma_buffer playback_dma_buf;
475 unsigned char *capture_buffer;
476 unsigned char *playback_buffer;
477
478 pid_t capture_pid;
479 pid_t playback_pid;
480 int running;
481 int system_sample_rate;
482 const char *channel_map;
483 int dev;
484 int irq;
485 unsigned long port;
486 void __iomem *iobase;
487 struct snd_card *card;
488 struct snd_pcm *pcm;
489 struct snd_hwdep *hwdep;
490 struct pci_dev *pci;
491 struct snd_kcontrol *spdif_ctl;
492 unsigned short mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
493 unsigned int dds_value;
494};
495
496
497
498
499
500
501
502
503
504static const char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
505 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
506 18, 19, 20, 21, 22, 23, 24, 25
507};
508
509static const char channel_map_mf_ss[HDSP_MAX_CHANNELS] = {
510
511 0, 1, 2, 3, 4, 5, 6, 7,
512
513 16, 17, 18, 19, 20, 21, 22, 23,
514
515 24, 25,
516 -1, -1, -1, -1, -1, -1, -1, -1
517};
518
519static const char channel_map_ds[HDSP_MAX_CHANNELS] = {
520
521 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
522
523 24, 25,
524
525 -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
526};
527
528static const char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
529
530 0, 1, 2, 3, 4, 5, 6, 7,
531
532 8, 9,
533
534 10, 11,
535
536 12, 13, 14, 15,
537
538 -1, -1, -1, -1, -1, -1, -1, -1,
539 -1, -1
540};
541
542static const char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
543
544 1, 3, 5, 7,
545
546 8, 9,
547
548 10, 11,
549
550 12, 13, 14, 15,
551
552 -1, -1, -1, -1, -1, -1, -1, -1,
553 -1, -1, -1, -1, -1, -1
554};
555
556static const char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
557
558
559 8, 9,
560
561 10, 11,
562
563 12, 13, 14, 15,
564
565 -1, -1, -1, -1, -1, -1, -1, -1,
566 -1, -1, -1, -1, -1, -1, -1, -1,
567 -1, -1
568};
569
570static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
571{
572 return snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, size, dmab);
573}
574
575static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
576{
577 if (dmab->area)
578 snd_dma_free_pages(dmab);
579}
580
581
582static const struct pci_device_id snd_hdsp_ids[] = {
583 {
584 .vendor = PCI_VENDOR_ID_XILINX,
585 .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
586 .subvendor = PCI_ANY_ID,
587 .subdevice = PCI_ANY_ID,
588 },
589 { 0, },
590};
591
592MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);
593
594
595static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
596static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
597static int snd_hdsp_enable_io (struct hdsp *hdsp);
598static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
599static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
600static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
601static int hdsp_autosync_ref(struct hdsp *hdsp);
602static int snd_hdsp_set_defaults(struct hdsp *hdsp);
603static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);
604
605static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
606{
607 switch (hdsp->io_type) {
608 case Multiface:
609 case Digiface:
610 case RPM:
611 default:
612 if (hdsp->firmware_rev == 0xa)
613 return (64 * out) + (32 + (in));
614 else
615 return (52 * out) + (26 + (in));
616 case H9632:
617 return (32 * out) + (16 + (in));
618 case H9652:
619 return (52 * out) + (26 + (in));
620 }
621}
622
623static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
624{
625 switch (hdsp->io_type) {
626 case Multiface:
627 case Digiface:
628 case RPM:
629 default:
630 if (hdsp->firmware_rev == 0xa)
631 return (64 * out) + in;
632 else
633 return (52 * out) + in;
634 case H9632:
635 return (32 * out) + in;
636 case H9652:
637 return (52 * out) + in;
638 }
639}
640
641static void hdsp_write(struct hdsp *hdsp, int reg, int val)
642{
643 writel(val, hdsp->iobase + reg);
644}
645
646static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
647{
648 return readl (hdsp->iobase + reg);
649}
650
651static int hdsp_check_for_iobox (struct hdsp *hdsp)
652{
653 int i;
654
655 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
656 for (i = 0; i < 500; i++) {
657 if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
658 HDSP_ConfigError)) {
659 if (i) {
660 dev_dbg(hdsp->card->dev,
661 "IO box found after %d ms\n",
662 (20 * i));
663 }
664 return 0;
665 }
666 msleep(20);
667 }
668 dev_err(hdsp->card->dev, "no IO box connected!\n");
669 hdsp->state &= ~HDSP_FirmwareLoaded;
670 return -EIO;
671}
672
673static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
674 unsigned int delay)
675{
676 unsigned int i;
677
678 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
679 return 0;
680
681 for (i = 0; i != loops; ++i) {
682 if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
683 msleep(delay);
684 else {
685 dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
686 i * delay);
687 return 0;
688 }
689 }
690
691 dev_info(hdsp->card->dev, "no IO box connected!\n");
692 hdsp->state &= ~HDSP_FirmwareLoaded;
693 return -EIO;
694}
695
696static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {
697
698 int i;
699 unsigned long flags;
700 const u32 *cache;
701
702 if (hdsp->fw_uploaded)
703 cache = hdsp->fw_uploaded;
704 else {
705 if (!hdsp->firmware)
706 return -ENODEV;
707 cache = (u32 *)hdsp->firmware->data;
708 if (!cache)
709 return -ENODEV;
710 }
711
712 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
713
714 dev_info(hdsp->card->dev, "loading firmware\n");
715
716 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
717 hdsp_write (hdsp, HDSP_fifoData, 0);
718
719 if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
720 dev_info(hdsp->card->dev,
721 "timeout waiting for download preparation\n");
722 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
723 return -EIO;
724 }
725
726 hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);
727
728 for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
729 hdsp_write(hdsp, HDSP_fifoData, cache[i]);
730 if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
731 dev_info(hdsp->card->dev,
732 "timeout during firmware loading\n");
733 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
734 return -EIO;
735 }
736 }
737
738 hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
739 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
740
741 ssleep(3);
742#ifdef SNDRV_BIG_ENDIAN
743 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
744#else
745 hdsp->control2_register = 0;
746#endif
747 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
748 dev_info(hdsp->card->dev, "finished firmware loading\n");
749
750 }
751 if (hdsp->state & HDSP_InitializationComplete) {
752 dev_info(hdsp->card->dev,
753 "firmware loaded from cache, restoring defaults\n");
754 spin_lock_irqsave(&hdsp->lock, flags);
755 snd_hdsp_set_defaults(hdsp);
756 spin_unlock_irqrestore(&hdsp->lock, flags);
757 }
758
759 hdsp->state |= HDSP_FirmwareLoaded;
760
761 return 0;
762}
763
764static int hdsp_get_iobox_version (struct hdsp *hdsp)
765{
766 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
767
768 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
769 hdsp_write(hdsp, HDSP_fifoData, 0);
770
771 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
772 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
773 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
774 }
775
776 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
777 hdsp_write (hdsp, HDSP_fifoData, 0);
778 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
779 goto set_multi;
780
781 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
782 hdsp_write(hdsp, HDSP_fifoData, 0);
783 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
784 hdsp->io_type = Digiface;
785 dev_info(hdsp->card->dev, "Digiface found\n");
786 return 0;
787 }
788
789 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
790 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
791 hdsp_write(hdsp, HDSP_fifoData, 0);
792 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
793 goto set_multi;
794
795 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
796 hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
797 hdsp_write(hdsp, HDSP_fifoData, 0);
798 if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
799 goto set_multi;
800
801 hdsp->io_type = RPM;
802 dev_info(hdsp->card->dev, "RPM found\n");
803 return 0;
804 } else {
805
806 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
807 hdsp->io_type = RPM;
808 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
809 hdsp->io_type = Multiface;
810 else
811 hdsp->io_type = Digiface;
812 }
813 return 0;
814
815set_multi:
816 hdsp->io_type = Multiface;
817 dev_info(hdsp->card->dev, "Multiface found\n");
818 return 0;
819}
820
821
822static int hdsp_request_fw_loader(struct hdsp *hdsp);
823
824static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
825{
826 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
827 return 0;
828 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
829 hdsp->state &= ~HDSP_FirmwareLoaded;
830 if (! load_on_demand)
831 return -EIO;
832 dev_err(hdsp->card->dev, "firmware not present.\n");
833
834 if (! (hdsp->state & HDSP_FirmwareCached)) {
835 if (! hdsp_request_fw_loader(hdsp))
836 return 0;
837 dev_err(hdsp->card->dev,
838 "No firmware loaded nor cached, please upload firmware.\n");
839 return -EIO;
840 }
841 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
842 dev_err(hdsp->card->dev,
843 "Firmware loading from cache failed, please upload manually.\n");
844 return -EIO;
845 }
846 }
847 return 0;
848}
849
850
851static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
852{
853 int i;
854
855
856
857
858
859 for (i = 0; i < timeout; i++) {
860
861 if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
862 return 0;
863
864
865
866
867
868 udelay (100);
869 }
870
871 dev_warn(hdsp->card->dev,
872 "wait for FIFO status <= %d failed after %d iterations\n",
873 count, timeout);
874 return -1;
875}
876
877static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
878{
879 if (addr >= HDSP_MATRIX_MIXER_SIZE)
880 return 0;
881
882 return hdsp->mixer_matrix[addr];
883}
884
885static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
886{
887 unsigned int ad;
888
889 if (addr >= HDSP_MATRIX_MIXER_SIZE)
890 return -1;
891
892 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {
893
894
895
896
897
898
899
900
901
902
903
904
905
906 if (hdsp->io_type == H9632 && addr >= 512)
907 return 0;
908
909 if (hdsp->io_type == H9652 && addr >= 1352)
910 return 0;
911
912 hdsp->mixer_matrix[addr] = data;
913
914
915
916
917
918
919
920
921
922 ad = addr/2;
923
924 hdsp_write (hdsp, 4096 + (ad*4),
925 (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
926 hdsp->mixer_matrix[addr&0x7fe]);
927
928 return 0;
929
930 } else {
931
932 ad = (addr << 16) + data;
933
934 if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
935 return -1;
936
937 hdsp_write (hdsp, HDSP_fifoData, ad);
938 hdsp->mixer_matrix[addr] = data;
939
940 }
941
942 return 0;
943}
944
945static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
946{
947 unsigned long flags;
948 int ret = 1;
949
950 spin_lock_irqsave(&hdsp->lock, flags);
951 if ((hdsp->playback_pid != hdsp->capture_pid) &&
952 (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
953 ret = 0;
954 spin_unlock_irqrestore(&hdsp->lock, flags);
955 return ret;
956}
957
958static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
959{
960 unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
961 unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);
962
963
964 if (hdsp->io_type == H9632)
965 rate_bits = (status & HDSP_spdifFrequencyMask_9632);
966
967 if (status & HDSP_SPDIFErrorFlag)
968 return 0;
969
970 switch (rate_bits) {
971 case HDSP_spdifFrequency32KHz: return 32000;
972 case HDSP_spdifFrequency44_1KHz: return 44100;
973 case HDSP_spdifFrequency48KHz: return 48000;
974 case HDSP_spdifFrequency64KHz: return 64000;
975 case HDSP_spdifFrequency88_2KHz: return 88200;
976 case HDSP_spdifFrequency96KHz: return 96000;
977 case HDSP_spdifFrequency128KHz:
978 if (hdsp->io_type == H9632) return 128000;
979 break;
980 case HDSP_spdifFrequency176_4KHz:
981 if (hdsp->io_type == H9632) return 176400;
982 break;
983 case HDSP_spdifFrequency192KHz:
984 if (hdsp->io_type == H9632) return 192000;
985 break;
986 default:
987 break;
988 }
989 dev_warn(hdsp->card->dev,
990 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
991 rate_bits, status);
992 return 0;
993}
994
995static int hdsp_external_sample_rate(struct hdsp *hdsp)
996{
997 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
998 unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;
999
1000
1001
1002
1003
1004 if (hdsp->io_type == H9632 &&
1005 hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
1006 return hdsp_spdif_sample_rate(hdsp);
1007
1008 switch (rate_bits) {
1009 case HDSP_systemFrequency32: return 32000;
1010 case HDSP_systemFrequency44_1: return 44100;
1011 case HDSP_systemFrequency48: return 48000;
1012 case HDSP_systemFrequency64: return 64000;
1013 case HDSP_systemFrequency88_2: return 88200;
1014 case HDSP_systemFrequency96: return 96000;
1015 default:
1016 return 0;
1017 }
1018}
1019
1020static void hdsp_compute_period_size(struct hdsp *hdsp)
1021{
1022 hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
1023}
1024
1025static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
1026{
1027 int position;
1028
1029 position = hdsp_read(hdsp, HDSP_statusRegister);
1030
1031 if (!hdsp->precise_ptr)
1032 return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;
1033
1034 position &= HDSP_BufferPositionMask;
1035 position /= 4;
1036 position &= (hdsp->period_bytes/2) - 1;
1037 return position;
1038}
1039
1040static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
1041{
1042 hdsp_write (hdsp, HDSP_resetPointer, 0);
1043 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1044
1045
1046
1047 hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
1048}
1049
1050static void hdsp_start_audio(struct hdsp *s)
1051{
1052 s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
1053 hdsp_write(s, HDSP_controlRegister, s->control_register);
1054}
1055
1056static void hdsp_stop_audio(struct hdsp *s)
1057{
1058 s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
1059 hdsp_write(s, HDSP_controlRegister, s->control_register);
1060}
1061
1062static void hdsp_silence_playback(struct hdsp *hdsp)
1063{
1064 memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
1065}
1066
1067static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
1068{
1069 int n;
1070
1071 spin_lock_irq(&s->lock);
1072
1073 frames >>= 7;
1074 n = 0;
1075 while (frames) {
1076 n++;
1077 frames >>= 1;
1078 }
1079
1080 s->control_register &= ~HDSP_LatencyMask;
1081 s->control_register |= hdsp_encode_latency(n);
1082
1083 hdsp_write(s, HDSP_controlRegister, s->control_register);
1084
1085 hdsp_compute_period_size(s);
1086
1087 spin_unlock_irq(&s->lock);
1088
1089 return 0;
1090}
1091
1092static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
1093{
1094 u64 n;
1095
1096 if (rate >= 112000)
1097 rate /= 4;
1098 else if (rate >= 56000)
1099 rate /= 2;
1100
1101 n = DDS_NUMERATOR;
1102 n = div_u64(n, rate);
1103
1104 snd_BUG_ON(n >> 32);
1105
1106
1107 hdsp->dds_value = n;
1108 hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
1109}
1110
1111static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
1112{
1113 int reject_if_open = 0;
1114 int current_rate;
1115 int rate_bits;
1116
1117
1118
1119
1120
1121
1122 if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
1123 if (called_internally) {
1124
1125 dev_err(hdsp->card->dev,
1126 "device is not running as a clock master: cannot set sample rate.\n");
1127 return -1;
1128 } else {
1129
1130 int external_freq = hdsp_external_sample_rate(hdsp);
1131 int spdif_freq = hdsp_spdif_sample_rate(hdsp);
1132
1133 if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1134 dev_info(hdsp->card->dev,
1135 "Detected ADAT in double speed mode\n");
1136 else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
1137 dev_info(hdsp->card->dev,
1138 "Detected ADAT in quad speed mode\n");
1139 else if (rate != external_freq) {
1140 dev_info(hdsp->card->dev,
1141 "No AutoSync source for requested rate\n");
1142 return -1;
1143 }
1144 }
1145 }
1146
1147 current_rate = hdsp->system_sample_rate;
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159 if (rate > 96000 && hdsp->io_type != H9632)
1160 return -EINVAL;
1161
1162 switch (rate) {
1163 case 32000:
1164 if (current_rate > 48000)
1165 reject_if_open = 1;
1166 rate_bits = HDSP_Frequency32KHz;
1167 break;
1168 case 44100:
1169 if (current_rate > 48000)
1170 reject_if_open = 1;
1171 rate_bits = HDSP_Frequency44_1KHz;
1172 break;
1173 case 48000:
1174 if (current_rate > 48000)
1175 reject_if_open = 1;
1176 rate_bits = HDSP_Frequency48KHz;
1177 break;
1178 case 64000:
1179 if (current_rate <= 48000 || current_rate > 96000)
1180 reject_if_open = 1;
1181 rate_bits = HDSP_Frequency64KHz;
1182 break;
1183 case 88200:
1184 if (current_rate <= 48000 || current_rate > 96000)
1185 reject_if_open = 1;
1186 rate_bits = HDSP_Frequency88_2KHz;
1187 break;
1188 case 96000:
1189 if (current_rate <= 48000 || current_rate > 96000)
1190 reject_if_open = 1;
1191 rate_bits = HDSP_Frequency96KHz;
1192 break;
1193 case 128000:
1194 if (current_rate < 128000)
1195 reject_if_open = 1;
1196 rate_bits = HDSP_Frequency128KHz;
1197 break;
1198 case 176400:
1199 if (current_rate < 128000)
1200 reject_if_open = 1;
1201 rate_bits = HDSP_Frequency176_4KHz;
1202 break;
1203 case 192000:
1204 if (current_rate < 128000)
1205 reject_if_open = 1;
1206 rate_bits = HDSP_Frequency192KHz;
1207 break;
1208 default:
1209 return -EINVAL;
1210 }
1211
1212 if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
1213 dev_warn(hdsp->card->dev,
1214 "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
1215 hdsp->capture_pid,
1216 hdsp->playback_pid);
1217 return -EBUSY;
1218 }
1219
1220 hdsp->control_register &= ~HDSP_FrequencyMask;
1221 hdsp->control_register |= rate_bits;
1222 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1223
1224
1225 if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
1226 hdsp_set_dds_value(hdsp, rate);
1227
1228 if (rate >= 128000) {
1229 hdsp->channel_map = channel_map_H9632_qs;
1230 } else if (rate > 48000) {
1231 if (hdsp->io_type == H9632)
1232 hdsp->channel_map = channel_map_H9632_ds;
1233 else
1234 hdsp->channel_map = channel_map_ds;
1235 } else {
1236 switch (hdsp->io_type) {
1237 case RPM:
1238 case Multiface:
1239 hdsp->channel_map = channel_map_mf_ss;
1240 break;
1241 case Digiface:
1242 case H9652:
1243 hdsp->channel_map = channel_map_df_ss;
1244 break;
1245 case H9632:
1246 hdsp->channel_map = channel_map_H9632_ss;
1247 break;
1248 default:
1249
1250 break;
1251 }
1252 }
1253
1254 hdsp->system_sample_rate = rate;
1255
1256 return 0;
1257}
1258
1259
1260
1261
1262
1263static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
1264{
1265
1266 if (id)
1267 return hdsp_read(hdsp, HDSP_midiDataIn1);
1268 else
1269 return hdsp_read(hdsp, HDSP_midiDataIn0);
1270}
1271
1272static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
1273{
1274
1275 if (id)
1276 hdsp_write(hdsp, HDSP_midiDataOut1, val);
1277 else
1278 hdsp_write(hdsp, HDSP_midiDataOut0, val);
1279}
1280
1281static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
1282{
1283 if (id)
1284 return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
1285 else
1286 return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
1287}
1288
1289static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
1290{
1291 int fifo_bytes_used;
1292
1293 if (id)
1294 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
1295 else
1296 fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;
1297
1298 if (fifo_bytes_used < 128)
1299 return 128 - fifo_bytes_used;
1300 else
1301 return 0;
1302}
1303
1304static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
1305{
1306 while (snd_hdsp_midi_input_available (hdsp, id))
1307 snd_hdsp_midi_read_byte (hdsp, id);
1308}
1309
1310static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
1311{
1312 unsigned long flags;
1313 int n_pending;
1314 int to_write;
1315 int i;
1316 unsigned char buf[128];
1317
1318
1319
1320 spin_lock_irqsave (&hmidi->lock, flags);
1321 if (hmidi->output) {
1322 if (!snd_rawmidi_transmit_empty (hmidi->output)) {
1323 if ((n_pending = snd_hdsp_midi_output_possible (hmidi->hdsp, hmidi->id)) > 0) {
1324 if (n_pending > (int)sizeof (buf))
1325 n_pending = sizeof (buf);
1326
1327 if ((to_write = snd_rawmidi_transmit (hmidi->output, buf, n_pending)) > 0) {
1328 for (i = 0; i < to_write; ++i)
1329 snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
1330 }
1331 }
1332 }
1333 }
1334 spin_unlock_irqrestore (&hmidi->lock, flags);
1335 return 0;
1336}
1337
1338static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
1339{
1340 unsigned char buf[128];
1341 unsigned long flags;
1342 int n_pending;
1343 int i;
1344
1345 spin_lock_irqsave (&hmidi->lock, flags);
1346 if ((n_pending = snd_hdsp_midi_input_available (hmidi->hdsp, hmidi->id)) > 0) {
1347 if (hmidi->input) {
1348 if (n_pending > (int)sizeof (buf))
1349 n_pending = sizeof (buf);
1350 for (i = 0; i < n_pending; ++i)
1351 buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1352 if (n_pending)
1353 snd_rawmidi_receive (hmidi->input, buf, n_pending);
1354 } else {
1355
1356 while (--n_pending)
1357 snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
1358 }
1359 }
1360 hmidi->pending = 0;
1361 if (hmidi->id)
1362 hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
1363 else
1364 hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
1365 hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
1366 spin_unlock_irqrestore (&hmidi->lock, flags);
1367 return snd_hdsp_midi_output_write (hmidi);
1368}
1369
1370static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
1371{
1372 struct hdsp *hdsp;
1373 struct hdsp_midi *hmidi;
1374 unsigned long flags;
1375 u32 ie;
1376
1377 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1378 hdsp = hmidi->hdsp;
1379 ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
1380 spin_lock_irqsave (&hdsp->lock, flags);
1381 if (up) {
1382 if (!(hdsp->control_register & ie)) {
1383 snd_hdsp_flush_midi_input (hdsp, hmidi->id);
1384 hdsp->control_register |= ie;
1385 }
1386 } else {
1387 hdsp->control_register &= ~ie;
1388 tasklet_kill(&hdsp->midi_tasklet);
1389 }
1390
1391 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1392 spin_unlock_irqrestore (&hdsp->lock, flags);
1393}
1394
1395static void snd_hdsp_midi_output_timer(struct timer_list *t)
1396{
1397 struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
1398 unsigned long flags;
1399
1400 snd_hdsp_midi_output_write(hmidi);
1401 spin_lock_irqsave (&hmidi->lock, flags);
1402
1403
1404
1405
1406
1407
1408
1409 if (hmidi->istimer)
1410 mod_timer(&hmidi->timer, 1 + jiffies);
1411
1412 spin_unlock_irqrestore (&hmidi->lock, flags);
1413}
1414
1415static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
1416{
1417 struct hdsp_midi *hmidi;
1418 unsigned long flags;
1419
1420 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1421 spin_lock_irqsave (&hmidi->lock, flags);
1422 if (up) {
1423 if (!hmidi->istimer) {
1424 timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
1425 0);
1426 mod_timer(&hmidi->timer, 1 + jiffies);
1427 hmidi->istimer++;
1428 }
1429 } else {
1430 if (hmidi->istimer && --hmidi->istimer <= 0)
1431 del_timer (&hmidi->timer);
1432 }
1433 spin_unlock_irqrestore (&hmidi->lock, flags);
1434 if (up)
1435 snd_hdsp_midi_output_write(hmidi);
1436}
1437
1438static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
1439{
1440 struct hdsp_midi *hmidi;
1441
1442 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1443 spin_lock_irq (&hmidi->lock);
1444 snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
1445 hmidi->input = substream;
1446 spin_unlock_irq (&hmidi->lock);
1447
1448 return 0;
1449}
1450
1451static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
1452{
1453 struct hdsp_midi *hmidi;
1454
1455 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1456 spin_lock_irq (&hmidi->lock);
1457 hmidi->output = substream;
1458 spin_unlock_irq (&hmidi->lock);
1459
1460 return 0;
1461}
1462
1463static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
1464{
1465 struct hdsp_midi *hmidi;
1466
1467 snd_hdsp_midi_input_trigger (substream, 0);
1468
1469 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1470 spin_lock_irq (&hmidi->lock);
1471 hmidi->input = NULL;
1472 spin_unlock_irq (&hmidi->lock);
1473
1474 return 0;
1475}
1476
1477static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
1478{
1479 struct hdsp_midi *hmidi;
1480
1481 snd_hdsp_midi_output_trigger (substream, 0);
1482
1483 hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
1484 spin_lock_irq (&hmidi->lock);
1485 hmidi->output = NULL;
1486 spin_unlock_irq (&hmidi->lock);
1487
1488 return 0;
1489}
1490
1491static const struct snd_rawmidi_ops snd_hdsp_midi_output =
1492{
1493 .open = snd_hdsp_midi_output_open,
1494 .close = snd_hdsp_midi_output_close,
1495 .trigger = snd_hdsp_midi_output_trigger,
1496};
1497
1498static const struct snd_rawmidi_ops snd_hdsp_midi_input =
1499{
1500 .open = snd_hdsp_midi_input_open,
1501 .close = snd_hdsp_midi_input_close,
1502 .trigger = snd_hdsp_midi_input_trigger,
1503};
1504
1505static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
1506{
1507 char buf[40];
1508
1509 hdsp->midi[id].id = id;
1510 hdsp->midi[id].rmidi = NULL;
1511 hdsp->midi[id].input = NULL;
1512 hdsp->midi[id].output = NULL;
1513 hdsp->midi[id].hdsp = hdsp;
1514 hdsp->midi[id].istimer = 0;
1515 hdsp->midi[id].pending = 0;
1516 spin_lock_init (&hdsp->midi[id].lock);
1517
1518 snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
1519 if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
1520 return -1;
1521
1522 sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
1523 hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];
1524
1525 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
1526 snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);
1527
1528 hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
1529 SNDRV_RAWMIDI_INFO_INPUT |
1530 SNDRV_RAWMIDI_INFO_DUPLEX;
1531
1532 return 0;
1533}
1534
1535
1536
1537
1538
1539static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
1540{
1541 u32 val = 0;
1542 val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
1543 val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
1544 if (val & HDSP_SPDIFProfessional)
1545 val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1546 else
1547 val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
1548 return val;
1549}
1550
1551static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
1552{
1553 aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
1554 ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
1555 if (val & HDSP_SPDIFProfessional)
1556 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
1557 else
1558 aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
1559}
1560
1561static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1562{
1563 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1564 uinfo->count = 1;
1565 return 0;
1566}
1567
1568static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1569{
1570 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1571
1572 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
1573 return 0;
1574}
1575
1576static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1577{
1578 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1579 int change;
1580 u32 val;
1581
1582 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1583 spin_lock_irq(&hdsp->lock);
1584 change = val != hdsp->creg_spdif;
1585 hdsp->creg_spdif = val;
1586 spin_unlock_irq(&hdsp->lock);
1587 return change;
1588}
1589
1590static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1591{
1592 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1593 uinfo->count = 1;
1594 return 0;
1595}
1596
1597static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1598{
1599 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1600
1601 snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
1602 return 0;
1603}
1604
1605static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1606{
1607 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1608 int change;
1609 u32 val;
1610
1611 val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
1612 spin_lock_irq(&hdsp->lock);
1613 change = val != hdsp->creg_spdif_stream;
1614 hdsp->creg_spdif_stream = val;
1615 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
1616 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
1617 spin_unlock_irq(&hdsp->lock);
1618 return change;
1619}
1620
1621static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1622{
1623 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1624 uinfo->count = 1;
1625 return 0;
1626}
1627
1628static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1629{
1630 ucontrol->value.iec958.status[0] = kcontrol->private_value;
1631 return 0;
1632}
1633
1634#define HDSP_SPDIF_IN(xname, xindex) \
1635{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1636 .name = xname, \
1637 .index = xindex, \
1638 .info = snd_hdsp_info_spdif_in, \
1639 .get = snd_hdsp_get_spdif_in, \
1640 .put = snd_hdsp_put_spdif_in }
1641
1642static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
1643{
1644 return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
1645}
1646
1647static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
1648{
1649 hdsp->control_register &= ~HDSP_SPDIFInputMask;
1650 hdsp->control_register |= hdsp_encode_spdif_in(in);
1651 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1652 return 0;
1653}
1654
1655static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1656{
1657 static const char * const texts[4] = {
1658 "Optical", "Coaxial", "Internal", "AES"
1659 };
1660 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1661
1662 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
1663 texts);
1664}
1665
1666static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1667{
1668 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1669
1670 ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
1671 return 0;
1672}
1673
1674static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1675{
1676 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1677 int change;
1678 unsigned int val;
1679
1680 if (!snd_hdsp_use_is_exclusive(hdsp))
1681 return -EBUSY;
1682 val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
1683 spin_lock_irq(&hdsp->lock);
1684 change = val != hdsp_spdif_in(hdsp);
1685 if (change)
1686 hdsp_set_spdif_input(hdsp, val);
1687 spin_unlock_irq(&hdsp->lock);
1688 return change;
1689}
1690
1691#define HDSP_TOGGLE_SETTING(xname, xindex) \
1692{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1693 .name = xname, \
1694 .private_value = xindex, \
1695 .info = snd_hdsp_info_toggle_setting, \
1696 .get = snd_hdsp_get_toggle_setting, \
1697 .put = snd_hdsp_put_toggle_setting \
1698}
1699
1700static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
1701{
1702 return (hdsp->control_register & regmask) ? 1 : 0;
1703}
1704
1705static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
1706{
1707 if (out)
1708 hdsp->control_register |= regmask;
1709 else
1710 hdsp->control_register &= ~regmask;
1711 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1712
1713 return 0;
1714}
1715
1716#define snd_hdsp_info_toggle_setting snd_ctl_boolean_mono_info
1717
1718static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
1719 struct snd_ctl_elem_value *ucontrol)
1720{
1721 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1722 u32 regmask = kcontrol->private_value;
1723
1724 spin_lock_irq(&hdsp->lock);
1725 ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
1726 spin_unlock_irq(&hdsp->lock);
1727 return 0;
1728}
1729
1730static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
1731 struct snd_ctl_elem_value *ucontrol)
1732{
1733 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1734 u32 regmask = kcontrol->private_value;
1735 int change;
1736 unsigned int val;
1737
1738 if (!snd_hdsp_use_is_exclusive(hdsp))
1739 return -EBUSY;
1740 val = ucontrol->value.integer.value[0] & 1;
1741 spin_lock_irq(&hdsp->lock);
1742 change = (int) val != hdsp_toggle_setting(hdsp, regmask);
1743 if (change)
1744 hdsp_set_toggle_setting(hdsp, regmask, val);
1745 spin_unlock_irq(&hdsp->lock);
1746 return change;
1747}
1748
1749#define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
1750{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1751 .name = xname, \
1752 .index = xindex, \
1753 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1754 .info = snd_hdsp_info_spdif_sample_rate, \
1755 .get = snd_hdsp_get_spdif_sample_rate \
1756}
1757
1758static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1759{
1760 static const char * const texts[] = {
1761 "32000", "44100", "48000", "64000", "88200", "96000",
1762 "None", "128000", "176400", "192000"
1763 };
1764 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1765
1766 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1767 texts);
1768}
1769
1770static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1771{
1772 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1773
1774 switch (hdsp_spdif_sample_rate(hdsp)) {
1775 case 32000:
1776 ucontrol->value.enumerated.item[0] = 0;
1777 break;
1778 case 44100:
1779 ucontrol->value.enumerated.item[0] = 1;
1780 break;
1781 case 48000:
1782 ucontrol->value.enumerated.item[0] = 2;
1783 break;
1784 case 64000:
1785 ucontrol->value.enumerated.item[0] = 3;
1786 break;
1787 case 88200:
1788 ucontrol->value.enumerated.item[0] = 4;
1789 break;
1790 case 96000:
1791 ucontrol->value.enumerated.item[0] = 5;
1792 break;
1793 case 128000:
1794 ucontrol->value.enumerated.item[0] = 7;
1795 break;
1796 case 176400:
1797 ucontrol->value.enumerated.item[0] = 8;
1798 break;
1799 case 192000:
1800 ucontrol->value.enumerated.item[0] = 9;
1801 break;
1802 default:
1803 ucontrol->value.enumerated.item[0] = 6;
1804 }
1805 return 0;
1806}
1807
1808#define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
1809{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1810 .name = xname, \
1811 .index = xindex, \
1812 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1813 .info = snd_hdsp_info_system_sample_rate, \
1814 .get = snd_hdsp_get_system_sample_rate \
1815}
1816
1817static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1818{
1819 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
1820 uinfo->count = 1;
1821 return 0;
1822}
1823
1824static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1825{
1826 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1827
1828 ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
1829 return 0;
1830}
1831
1832#define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
1833{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1834 .name = xname, \
1835 .index = xindex, \
1836 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1837 .info = snd_hdsp_info_autosync_sample_rate, \
1838 .get = snd_hdsp_get_autosync_sample_rate \
1839}
1840
1841static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1842{
1843 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1844 static const char * const texts[] = {
1845 "32000", "44100", "48000", "64000", "88200", "96000",
1846 "None", "128000", "176400", "192000"
1847 };
1848
1849 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
1850 texts);
1851}
1852
1853static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1854{
1855 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1856
1857 switch (hdsp_external_sample_rate(hdsp)) {
1858 case 32000:
1859 ucontrol->value.enumerated.item[0] = 0;
1860 break;
1861 case 44100:
1862 ucontrol->value.enumerated.item[0] = 1;
1863 break;
1864 case 48000:
1865 ucontrol->value.enumerated.item[0] = 2;
1866 break;
1867 case 64000:
1868 ucontrol->value.enumerated.item[0] = 3;
1869 break;
1870 case 88200:
1871 ucontrol->value.enumerated.item[0] = 4;
1872 break;
1873 case 96000:
1874 ucontrol->value.enumerated.item[0] = 5;
1875 break;
1876 case 128000:
1877 ucontrol->value.enumerated.item[0] = 7;
1878 break;
1879 case 176400:
1880 ucontrol->value.enumerated.item[0] = 8;
1881 break;
1882 case 192000:
1883 ucontrol->value.enumerated.item[0] = 9;
1884 break;
1885 default:
1886 ucontrol->value.enumerated.item[0] = 6;
1887 }
1888 return 0;
1889}
1890
1891#define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
1892{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1893 .name = xname, \
1894 .index = xindex, \
1895 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
1896 .info = snd_hdsp_info_system_clock_mode, \
1897 .get = snd_hdsp_get_system_clock_mode \
1898}
1899
1900static int hdsp_system_clock_mode(struct hdsp *hdsp)
1901{
1902 if (hdsp->control_register & HDSP_ClockModeMaster)
1903 return 0;
1904 else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
1905 return 0;
1906 return 1;
1907}
1908
1909static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
1910{
1911 static const char * const texts[] = {"Master", "Slave" };
1912
1913 return snd_ctl_enum_info(uinfo, 1, 2, texts);
1914}
1915
1916static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
1917{
1918 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
1919
1920 ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
1921 return 0;
1922}
1923
1924#define HDSP_CLOCK_SOURCE(xname, xindex) \
1925{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
1926 .name = xname, \
1927 .index = xindex, \
1928 .info = snd_hdsp_info_clock_source, \
1929 .get = snd_hdsp_get_clock_source, \
1930 .put = snd_hdsp_put_clock_source \
1931}
1932
1933static int hdsp_clock_source(struct hdsp *hdsp)
1934{
1935 if (hdsp->control_register & HDSP_ClockModeMaster) {
1936 switch (hdsp->system_sample_rate) {
1937 case 32000:
1938 return 1;
1939 case 44100:
1940 return 2;
1941 case 48000:
1942 return 3;
1943 case 64000:
1944 return 4;
1945 case 88200:
1946 return 5;
1947 case 96000:
1948 return 6;
1949 case 128000:
1950 return 7;
1951 case 176400:
1952 return 8;
1953 case 192000:
1954 return 9;
1955 default:
1956 return 3;
1957 }
1958 } else {
1959 return 0;
1960 }
1961}
1962
1963static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
1964{
1965 int rate;
1966 switch (mode) {
1967 case HDSP_CLOCK_SOURCE_AUTOSYNC:
1968 if (hdsp_external_sample_rate(hdsp) != 0) {
1969 if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
1970 hdsp->control_register &= ~HDSP_ClockModeMaster;
1971 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
1972 return 0;
1973 }
1974 }
1975 return -1;
1976 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
1977 rate = 32000;
1978 break;
1979 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
1980 rate = 44100;
1981 break;
1982 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
1983 rate = 48000;
1984 break;
1985 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
1986 rate = 64000;
1987 break;
1988 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
1989 rate = 88200;
1990 break;
1991 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
1992 rate = 96000;
1993 break;
1994 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
1995 rate = 128000;
1996 break;
1997 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
1998 rate = 176400;
1999 break;
2000 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
2001 rate = 192000;
2002 break;
2003 default:
2004 rate = 48000;
2005 }
2006 hdsp->control_register |= HDSP_ClockModeMaster;
2007 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2008 hdsp_set_rate(hdsp, rate, 1);
2009 return 0;
2010}
2011
2012static int snd_hdsp_info_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2013{
2014 static const char * const texts[] = {
2015 "AutoSync", "Internal 32.0 kHz", "Internal 44.1 kHz",
2016 "Internal 48.0 kHz", "Internal 64.0 kHz", "Internal 88.2 kHz",
2017 "Internal 96.0 kHz", "Internal 128 kHz", "Internal 176.4 kHz",
2018 "Internal 192.0 KHz"
2019 };
2020 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2021
2022 return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
2023 texts);
2024}
2025
2026static int snd_hdsp_get_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2027{
2028 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2029
2030 ucontrol->value.enumerated.item[0] = hdsp_clock_source(hdsp);
2031 return 0;
2032}
2033
2034static int snd_hdsp_put_clock_source(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2035{
2036 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2037 int change;
2038 int val;
2039
2040 if (!snd_hdsp_use_is_exclusive(hdsp))
2041 return -EBUSY;
2042 val = ucontrol->value.enumerated.item[0];
2043 if (val < 0) val = 0;
2044 if (hdsp->io_type == H9632) {
2045 if (val > 9)
2046 val = 9;
2047 } else {
2048 if (val > 6)
2049 val = 6;
2050 }
2051 spin_lock_irq(&hdsp->lock);
2052 if (val != hdsp_clock_source(hdsp))
2053 change = (hdsp_set_clock_source(hdsp, val) == 0) ? 1 : 0;
2054 else
2055 change = 0;
2056 spin_unlock_irq(&hdsp->lock);
2057 return change;
2058}
2059
2060#define snd_hdsp_info_clock_source_lock snd_ctl_boolean_mono_info
2061
2062static int snd_hdsp_get_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2063{
2064 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2065
2066 ucontrol->value.integer.value[0] = hdsp->clock_source_locked;
2067 return 0;
2068}
2069
2070static int snd_hdsp_put_clock_source_lock(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2071{
2072 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2073 int change;
2074
2075 change = (int)ucontrol->value.integer.value[0] != hdsp->clock_source_locked;
2076 if (change)
2077 hdsp->clock_source_locked = !!ucontrol->value.integer.value[0];
2078 return change;
2079}
2080
2081#define HDSP_DA_GAIN(xname, xindex) \
2082{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2083 .name = xname, \
2084 .index = xindex, \
2085 .info = snd_hdsp_info_da_gain, \
2086 .get = snd_hdsp_get_da_gain, \
2087 .put = snd_hdsp_put_da_gain \
2088}
2089
2090static int hdsp_da_gain(struct hdsp *hdsp)
2091{
2092 switch (hdsp->control_register & HDSP_DAGainMask) {
2093 case HDSP_DAGainHighGain:
2094 return 0;
2095 case HDSP_DAGainPlus4dBu:
2096 return 1;
2097 case HDSP_DAGainMinus10dBV:
2098 return 2;
2099 default:
2100 return 1;
2101 }
2102}
2103
2104static int hdsp_set_da_gain(struct hdsp *hdsp, int mode)
2105{
2106 hdsp->control_register &= ~HDSP_DAGainMask;
2107 switch (mode) {
2108 case 0:
2109 hdsp->control_register |= HDSP_DAGainHighGain;
2110 break;
2111 case 1:
2112 hdsp->control_register |= HDSP_DAGainPlus4dBu;
2113 break;
2114 case 2:
2115 hdsp->control_register |= HDSP_DAGainMinus10dBV;
2116 break;
2117 default:
2118 return -1;
2119
2120 }
2121 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2122 return 0;
2123}
2124
2125static int snd_hdsp_info_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2126{
2127 static const char * const texts[] = {"Hi Gain", "+4 dBu", "-10 dbV"};
2128
2129 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2130}
2131
2132static int snd_hdsp_get_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2133{
2134 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2135
2136 ucontrol->value.enumerated.item[0] = hdsp_da_gain(hdsp);
2137 return 0;
2138}
2139
2140static int snd_hdsp_put_da_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2141{
2142 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2143 int change;
2144 int val;
2145
2146 if (!snd_hdsp_use_is_exclusive(hdsp))
2147 return -EBUSY;
2148 val = ucontrol->value.enumerated.item[0];
2149 if (val < 0) val = 0;
2150 if (val > 2) val = 2;
2151 spin_lock_irq(&hdsp->lock);
2152 if (val != hdsp_da_gain(hdsp))
2153 change = (hdsp_set_da_gain(hdsp, val) == 0) ? 1 : 0;
2154 else
2155 change = 0;
2156 spin_unlock_irq(&hdsp->lock);
2157 return change;
2158}
2159
2160#define HDSP_AD_GAIN(xname, xindex) \
2161{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2162 .name = xname, \
2163 .index = xindex, \
2164 .info = snd_hdsp_info_ad_gain, \
2165 .get = snd_hdsp_get_ad_gain, \
2166 .put = snd_hdsp_put_ad_gain \
2167}
2168
2169static int hdsp_ad_gain(struct hdsp *hdsp)
2170{
2171 switch (hdsp->control_register & HDSP_ADGainMask) {
2172 case HDSP_ADGainMinus10dBV:
2173 return 0;
2174 case HDSP_ADGainPlus4dBu:
2175 return 1;
2176 case HDSP_ADGainLowGain:
2177 return 2;
2178 default:
2179 return 1;
2180 }
2181}
2182
2183static int hdsp_set_ad_gain(struct hdsp *hdsp, int mode)
2184{
2185 hdsp->control_register &= ~HDSP_ADGainMask;
2186 switch (mode) {
2187 case 0:
2188 hdsp->control_register |= HDSP_ADGainMinus10dBV;
2189 break;
2190 case 1:
2191 hdsp->control_register |= HDSP_ADGainPlus4dBu;
2192 break;
2193 case 2:
2194 hdsp->control_register |= HDSP_ADGainLowGain;
2195 break;
2196 default:
2197 return -1;
2198
2199 }
2200 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2201 return 0;
2202}
2203
2204static int snd_hdsp_info_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2205{
2206 static const char * const texts[] = {"-10 dBV", "+4 dBu", "Lo Gain"};
2207
2208 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2209}
2210
2211static int snd_hdsp_get_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2212{
2213 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2214
2215 ucontrol->value.enumerated.item[0] = hdsp_ad_gain(hdsp);
2216 return 0;
2217}
2218
2219static int snd_hdsp_put_ad_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2220{
2221 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2222 int change;
2223 int val;
2224
2225 if (!snd_hdsp_use_is_exclusive(hdsp))
2226 return -EBUSY;
2227 val = ucontrol->value.enumerated.item[0];
2228 if (val < 0) val = 0;
2229 if (val > 2) val = 2;
2230 spin_lock_irq(&hdsp->lock);
2231 if (val != hdsp_ad_gain(hdsp))
2232 change = (hdsp_set_ad_gain(hdsp, val) == 0) ? 1 : 0;
2233 else
2234 change = 0;
2235 spin_unlock_irq(&hdsp->lock);
2236 return change;
2237}
2238
2239#define HDSP_PHONE_GAIN(xname, xindex) \
2240{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2241 .name = xname, \
2242 .index = xindex, \
2243 .info = snd_hdsp_info_phone_gain, \
2244 .get = snd_hdsp_get_phone_gain, \
2245 .put = snd_hdsp_put_phone_gain \
2246}
2247
2248static int hdsp_phone_gain(struct hdsp *hdsp)
2249{
2250 switch (hdsp->control_register & HDSP_PhoneGainMask) {
2251 case HDSP_PhoneGain0dB:
2252 return 0;
2253 case HDSP_PhoneGainMinus6dB:
2254 return 1;
2255 case HDSP_PhoneGainMinus12dB:
2256 return 2;
2257 default:
2258 return 0;
2259 }
2260}
2261
2262static int hdsp_set_phone_gain(struct hdsp *hdsp, int mode)
2263{
2264 hdsp->control_register &= ~HDSP_PhoneGainMask;
2265 switch (mode) {
2266 case 0:
2267 hdsp->control_register |= HDSP_PhoneGain0dB;
2268 break;
2269 case 1:
2270 hdsp->control_register |= HDSP_PhoneGainMinus6dB;
2271 break;
2272 case 2:
2273 hdsp->control_register |= HDSP_PhoneGainMinus12dB;
2274 break;
2275 default:
2276 return -1;
2277
2278 }
2279 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2280 return 0;
2281}
2282
2283static int snd_hdsp_info_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2284{
2285 static const char * const texts[] = {"0 dB", "-6 dB", "-12 dB"};
2286
2287 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2288}
2289
2290static int snd_hdsp_get_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2291{
2292 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2293
2294 ucontrol->value.enumerated.item[0] = hdsp_phone_gain(hdsp);
2295 return 0;
2296}
2297
2298static int snd_hdsp_put_phone_gain(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2299{
2300 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2301 int change;
2302 int val;
2303
2304 if (!snd_hdsp_use_is_exclusive(hdsp))
2305 return -EBUSY;
2306 val = ucontrol->value.enumerated.item[0];
2307 if (val < 0) val = 0;
2308 if (val > 2) val = 2;
2309 spin_lock_irq(&hdsp->lock);
2310 if (val != hdsp_phone_gain(hdsp))
2311 change = (hdsp_set_phone_gain(hdsp, val) == 0) ? 1 : 0;
2312 else
2313 change = 0;
2314 spin_unlock_irq(&hdsp->lock);
2315 return change;
2316}
2317
2318#define HDSP_PREF_SYNC_REF(xname, xindex) \
2319{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2320 .name = xname, \
2321 .index = xindex, \
2322 .info = snd_hdsp_info_pref_sync_ref, \
2323 .get = snd_hdsp_get_pref_sync_ref, \
2324 .put = snd_hdsp_put_pref_sync_ref \
2325}
2326
2327static int hdsp_pref_sync_ref(struct hdsp *hdsp)
2328{
2329
2330
2331
2332
2333 switch (hdsp->control_register & HDSP_SyncRefMask) {
2334 case HDSP_SyncRef_ADAT1:
2335 return HDSP_SYNC_FROM_ADAT1;
2336 case HDSP_SyncRef_ADAT2:
2337 return HDSP_SYNC_FROM_ADAT2;
2338 case HDSP_SyncRef_ADAT3:
2339 return HDSP_SYNC_FROM_ADAT3;
2340 case HDSP_SyncRef_SPDIF:
2341 return HDSP_SYNC_FROM_SPDIF;
2342 case HDSP_SyncRef_WORD:
2343 return HDSP_SYNC_FROM_WORD;
2344 case HDSP_SyncRef_ADAT_SYNC:
2345 return HDSP_SYNC_FROM_ADAT_SYNC;
2346 default:
2347 return HDSP_SYNC_FROM_WORD;
2348 }
2349 return 0;
2350}
2351
2352static int hdsp_set_pref_sync_ref(struct hdsp *hdsp, int pref)
2353{
2354 hdsp->control_register &= ~HDSP_SyncRefMask;
2355 switch (pref) {
2356 case HDSP_SYNC_FROM_ADAT1:
2357 hdsp->control_register &= ~HDSP_SyncRefMask;
2358 break;
2359 case HDSP_SYNC_FROM_ADAT2:
2360 hdsp->control_register |= HDSP_SyncRef_ADAT2;
2361 break;
2362 case HDSP_SYNC_FROM_ADAT3:
2363 hdsp->control_register |= HDSP_SyncRef_ADAT3;
2364 break;
2365 case HDSP_SYNC_FROM_SPDIF:
2366 hdsp->control_register |= HDSP_SyncRef_SPDIF;
2367 break;
2368 case HDSP_SYNC_FROM_WORD:
2369 hdsp->control_register |= HDSP_SyncRef_WORD;
2370 break;
2371 case HDSP_SYNC_FROM_ADAT_SYNC:
2372 hdsp->control_register |= HDSP_SyncRef_ADAT_SYNC;
2373 break;
2374 default:
2375 return -1;
2376 }
2377 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
2378 return 0;
2379}
2380
2381static int snd_hdsp_info_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2382{
2383 static const char * const texts[] = {
2384 "Word", "IEC958", "ADAT1", "ADAT Sync", "ADAT2", "ADAT3"
2385 };
2386 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2387 int num_items;
2388
2389 switch (hdsp->io_type) {
2390 case Digiface:
2391 case H9652:
2392 num_items = 6;
2393 break;
2394 case Multiface:
2395 num_items = 4;
2396 break;
2397 case H9632:
2398 num_items = 3;
2399 break;
2400 default:
2401 return -EINVAL;
2402 }
2403
2404 return snd_ctl_enum_info(uinfo, 1, num_items, texts);
2405}
2406
2407static int snd_hdsp_get_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2408{
2409 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2410
2411 ucontrol->value.enumerated.item[0] = hdsp_pref_sync_ref(hdsp);
2412 return 0;
2413}
2414
2415static int snd_hdsp_put_pref_sync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2416{
2417 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2418 int change, max;
2419 unsigned int val;
2420
2421 if (!snd_hdsp_use_is_exclusive(hdsp))
2422 return -EBUSY;
2423
2424 switch (hdsp->io_type) {
2425 case Digiface:
2426 case H9652:
2427 max = 6;
2428 break;
2429 case Multiface:
2430 max = 4;
2431 break;
2432 case H9632:
2433 max = 3;
2434 break;
2435 default:
2436 return -EIO;
2437 }
2438
2439 val = ucontrol->value.enumerated.item[0] % max;
2440 spin_lock_irq(&hdsp->lock);
2441 change = (int)val != hdsp_pref_sync_ref(hdsp);
2442 hdsp_set_pref_sync_ref(hdsp, val);
2443 spin_unlock_irq(&hdsp->lock);
2444 return change;
2445}
2446
2447#define HDSP_AUTOSYNC_REF(xname, xindex) \
2448{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2449 .name = xname, \
2450 .index = xindex, \
2451 .access = SNDRV_CTL_ELEM_ACCESS_READ, \
2452 .info = snd_hdsp_info_autosync_ref, \
2453 .get = snd_hdsp_get_autosync_ref, \
2454}
2455
2456static int hdsp_autosync_ref(struct hdsp *hdsp)
2457{
2458
2459 unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
2460
2461 switch (status2 & HDSP_SelSyncRefMask) {
2462 case HDSP_SelSyncRef_WORD:
2463 return HDSP_AUTOSYNC_FROM_WORD;
2464 case HDSP_SelSyncRef_ADAT_SYNC:
2465 return HDSP_AUTOSYNC_FROM_ADAT_SYNC;
2466 case HDSP_SelSyncRef_SPDIF:
2467 return HDSP_AUTOSYNC_FROM_SPDIF;
2468 case HDSP_SelSyncRefMask:
2469 return HDSP_AUTOSYNC_FROM_NONE;
2470 case HDSP_SelSyncRef_ADAT1:
2471 return HDSP_AUTOSYNC_FROM_ADAT1;
2472 case HDSP_SelSyncRef_ADAT2:
2473 return HDSP_AUTOSYNC_FROM_ADAT2;
2474 case HDSP_SelSyncRef_ADAT3:
2475 return HDSP_AUTOSYNC_FROM_ADAT3;
2476 default:
2477 return HDSP_AUTOSYNC_FROM_WORD;
2478 }
2479 return 0;
2480}
2481
2482static int snd_hdsp_info_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2483{
2484 static const char * const texts[] = {
2485 "Word", "ADAT Sync", "IEC958", "None", "ADAT1", "ADAT2", "ADAT3"
2486 };
2487
2488 return snd_ctl_enum_info(uinfo, 1, 7, texts);
2489}
2490
2491static int snd_hdsp_get_autosync_ref(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2492{
2493 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2494
2495 ucontrol->value.enumerated.item[0] = hdsp_autosync_ref(hdsp);
2496 return 0;
2497}
2498
2499#define HDSP_PRECISE_POINTER(xname, xindex) \
2500{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2501 .name = xname, \
2502 .index = xindex, \
2503 .info = snd_hdsp_info_precise_pointer, \
2504 .get = snd_hdsp_get_precise_pointer, \
2505 .put = snd_hdsp_put_precise_pointer \
2506}
2507
2508static int hdsp_set_precise_pointer(struct hdsp *hdsp, int precise)
2509{
2510 if (precise)
2511 hdsp->precise_ptr = 1;
2512 else
2513 hdsp->precise_ptr = 0;
2514 return 0;
2515}
2516
2517#define snd_hdsp_info_precise_pointer snd_ctl_boolean_mono_info
2518
2519static int snd_hdsp_get_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2520{
2521 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2522
2523 spin_lock_irq(&hdsp->lock);
2524 ucontrol->value.integer.value[0] = hdsp->precise_ptr;
2525 spin_unlock_irq(&hdsp->lock);
2526 return 0;
2527}
2528
2529static int snd_hdsp_put_precise_pointer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2530{
2531 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2532 int change;
2533 unsigned int val;
2534
2535 if (!snd_hdsp_use_is_exclusive(hdsp))
2536 return -EBUSY;
2537 val = ucontrol->value.integer.value[0] & 1;
2538 spin_lock_irq(&hdsp->lock);
2539 change = (int)val != hdsp->precise_ptr;
2540 hdsp_set_precise_pointer(hdsp, val);
2541 spin_unlock_irq(&hdsp->lock);
2542 return change;
2543}
2544
2545#define HDSP_USE_MIDI_TASKLET(xname, xindex) \
2546{ .iface = SNDRV_CTL_ELEM_IFACE_CARD, \
2547 .name = xname, \
2548 .index = xindex, \
2549 .info = snd_hdsp_info_use_midi_tasklet, \
2550 .get = snd_hdsp_get_use_midi_tasklet, \
2551 .put = snd_hdsp_put_use_midi_tasklet \
2552}
2553
2554static int hdsp_set_use_midi_tasklet(struct hdsp *hdsp, int use_tasklet)
2555{
2556 if (use_tasklet)
2557 hdsp->use_midi_tasklet = 1;
2558 else
2559 hdsp->use_midi_tasklet = 0;
2560 return 0;
2561}
2562
2563#define snd_hdsp_info_use_midi_tasklet snd_ctl_boolean_mono_info
2564
2565static int snd_hdsp_get_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2566{
2567 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2568
2569 spin_lock_irq(&hdsp->lock);
2570 ucontrol->value.integer.value[0] = hdsp->use_midi_tasklet;
2571 spin_unlock_irq(&hdsp->lock);
2572 return 0;
2573}
2574
2575static int snd_hdsp_put_use_midi_tasklet(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2576{
2577 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2578 int change;
2579 unsigned int val;
2580
2581 if (!snd_hdsp_use_is_exclusive(hdsp))
2582 return -EBUSY;
2583 val = ucontrol->value.integer.value[0] & 1;
2584 spin_lock_irq(&hdsp->lock);
2585 change = (int)val != hdsp->use_midi_tasklet;
2586 hdsp_set_use_midi_tasklet(hdsp, val);
2587 spin_unlock_irq(&hdsp->lock);
2588 return change;
2589}
2590
2591#define HDSP_MIXER(xname, xindex) \
2592{ .iface = SNDRV_CTL_ELEM_IFACE_HWDEP, \
2593 .name = xname, \
2594 .index = xindex, \
2595 .device = 0, \
2596 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | \
2597 SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2598 .info = snd_hdsp_info_mixer, \
2599 .get = snd_hdsp_get_mixer, \
2600 .put = snd_hdsp_put_mixer \
2601}
2602
2603static int snd_hdsp_info_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2604{
2605 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2606 uinfo->count = 3;
2607 uinfo->value.integer.min = 0;
2608 uinfo->value.integer.max = 65536;
2609 uinfo->value.integer.step = 1;
2610 return 0;
2611}
2612
2613static int snd_hdsp_get_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2614{
2615 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2616 int source;
2617 int destination;
2618 int addr;
2619
2620 source = ucontrol->value.integer.value[0];
2621 destination = ucontrol->value.integer.value[1];
2622
2623 if (source >= hdsp->max_channels)
2624 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels,destination);
2625 else
2626 addr = hdsp_input_to_output_key(hdsp,source, destination);
2627
2628 spin_lock_irq(&hdsp->lock);
2629 ucontrol->value.integer.value[2] = hdsp_read_gain (hdsp, addr);
2630 spin_unlock_irq(&hdsp->lock);
2631 return 0;
2632}
2633
2634static int snd_hdsp_put_mixer(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2635{
2636 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2637 int change;
2638 int source;
2639 int destination;
2640 int gain;
2641 int addr;
2642
2643 if (!snd_hdsp_use_is_exclusive(hdsp))
2644 return -EBUSY;
2645
2646 source = ucontrol->value.integer.value[0];
2647 destination = ucontrol->value.integer.value[1];
2648
2649 if (source >= hdsp->max_channels)
2650 addr = hdsp_playback_to_output_key(hdsp,source-hdsp->max_channels, destination);
2651 else
2652 addr = hdsp_input_to_output_key(hdsp,source, destination);
2653
2654 gain = ucontrol->value.integer.value[2];
2655
2656 spin_lock_irq(&hdsp->lock);
2657 change = gain != hdsp_read_gain(hdsp, addr);
2658 if (change)
2659 hdsp_write_gain(hdsp, addr, gain);
2660 spin_unlock_irq(&hdsp->lock);
2661 return change;
2662}
2663
2664#define HDSP_WC_SYNC_CHECK(xname, xindex) \
2665{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2666 .name = xname, \
2667 .index = xindex, \
2668 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2669 .info = snd_hdsp_info_sync_check, \
2670 .get = snd_hdsp_get_wc_sync_check \
2671}
2672
2673static int snd_hdsp_info_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2674{
2675 static const char * const texts[] = {"No Lock", "Lock", "Sync" };
2676
2677 return snd_ctl_enum_info(uinfo, 1, 3, texts);
2678}
2679
2680static int hdsp_wc_sync_check(struct hdsp *hdsp)
2681{
2682 int status2 = hdsp_read(hdsp, HDSP_status2Register);
2683 if (status2 & HDSP_wc_lock) {
2684 if (status2 & HDSP_wc_sync)
2685 return 2;
2686 else
2687 return 1;
2688 } else
2689 return 0;
2690 return 0;
2691}
2692
2693static int snd_hdsp_get_wc_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2694{
2695 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2696
2697 ucontrol->value.enumerated.item[0] = hdsp_wc_sync_check(hdsp);
2698 return 0;
2699}
2700
2701#define HDSP_SPDIF_SYNC_CHECK(xname, xindex) \
2702{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2703 .name = xname, \
2704 .index = xindex, \
2705 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2706 .info = snd_hdsp_info_sync_check, \
2707 .get = snd_hdsp_get_spdif_sync_check \
2708}
2709
2710static int hdsp_spdif_sync_check(struct hdsp *hdsp)
2711{
2712 int status = hdsp_read(hdsp, HDSP_statusRegister);
2713 if (status & HDSP_SPDIFErrorFlag)
2714 return 0;
2715 else {
2716 if (status & HDSP_SPDIFSync)
2717 return 2;
2718 else
2719 return 1;
2720 }
2721 return 0;
2722}
2723
2724static int snd_hdsp_get_spdif_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2725{
2726 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2727
2728 ucontrol->value.enumerated.item[0] = hdsp_spdif_sync_check(hdsp);
2729 return 0;
2730}
2731
2732#define HDSP_ADATSYNC_SYNC_CHECK(xname, xindex) \
2733{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2734 .name = xname, \
2735 .index = xindex, \
2736 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2737 .info = snd_hdsp_info_sync_check, \
2738 .get = snd_hdsp_get_adatsync_sync_check \
2739}
2740
2741static int hdsp_adatsync_sync_check(struct hdsp *hdsp)
2742{
2743 int status = hdsp_read(hdsp, HDSP_statusRegister);
2744 if (status & HDSP_TimecodeLock) {
2745 if (status & HDSP_TimecodeSync)
2746 return 2;
2747 else
2748 return 1;
2749 } else
2750 return 0;
2751}
2752
2753static int snd_hdsp_get_adatsync_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2754{
2755 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2756
2757 ucontrol->value.enumerated.item[0] = hdsp_adatsync_sync_check(hdsp);
2758 return 0;
2759}
2760
2761#define HDSP_ADAT_SYNC_CHECK \
2762{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2763 .access = SNDRV_CTL_ELEM_ACCESS_READ | SNDRV_CTL_ELEM_ACCESS_VOLATILE, \
2764 .info = snd_hdsp_info_sync_check, \
2765 .get = snd_hdsp_get_adat_sync_check \
2766}
2767
2768static int hdsp_adat_sync_check(struct hdsp *hdsp, int idx)
2769{
2770 int status = hdsp_read(hdsp, HDSP_statusRegister);
2771
2772 if (status & (HDSP_Lock0>>idx)) {
2773 if (status & (HDSP_Sync0>>idx))
2774 return 2;
2775 else
2776 return 1;
2777 } else
2778 return 0;
2779}
2780
2781static int snd_hdsp_get_adat_sync_check(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2782{
2783 int offset;
2784 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2785
2786 offset = ucontrol->id.index - 1;
2787 if (snd_BUG_ON(offset < 0))
2788 return -EINVAL;
2789
2790 switch (hdsp->io_type) {
2791 case Digiface:
2792 case H9652:
2793 if (offset >= 3)
2794 return -EINVAL;
2795 break;
2796 case Multiface:
2797 case H9632:
2798 if (offset >= 1)
2799 return -EINVAL;
2800 break;
2801 default:
2802 return -EIO;
2803 }
2804
2805 ucontrol->value.enumerated.item[0] = hdsp_adat_sync_check(hdsp, offset);
2806 return 0;
2807}
2808
2809#define HDSP_DDS_OFFSET(xname, xindex) \
2810{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
2811 .name = xname, \
2812 .index = xindex, \
2813 .info = snd_hdsp_info_dds_offset, \
2814 .get = snd_hdsp_get_dds_offset, \
2815 .put = snd_hdsp_put_dds_offset \
2816}
2817
2818static int hdsp_dds_offset(struct hdsp *hdsp)
2819{
2820 u64 n;
2821 unsigned int dds_value = hdsp->dds_value;
2822 int system_sample_rate = hdsp->system_sample_rate;
2823
2824 if (!dds_value)
2825 return 0;
2826
2827 n = DDS_NUMERATOR;
2828
2829
2830
2831
2832 n = div_u64(n, dds_value);
2833 if (system_sample_rate >= 112000)
2834 n *= 4;
2835 else if (system_sample_rate >= 56000)
2836 n *= 2;
2837 return ((int)n) - system_sample_rate;
2838}
2839
2840static int hdsp_set_dds_offset(struct hdsp *hdsp, int offset_hz)
2841{
2842 int rate = hdsp->system_sample_rate + offset_hz;
2843 hdsp_set_dds_value(hdsp, rate);
2844 return 0;
2845}
2846
2847static int snd_hdsp_info_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
2848{
2849 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2850 uinfo->count = 1;
2851 uinfo->value.integer.min = -5000;
2852 uinfo->value.integer.max = 5000;
2853 return 0;
2854}
2855
2856static int snd_hdsp_get_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2857{
2858 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2859
2860 ucontrol->value.integer.value[0] = hdsp_dds_offset(hdsp);
2861 return 0;
2862}
2863
2864static int snd_hdsp_put_dds_offset(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2865{
2866 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2867 int change;
2868 int val;
2869
2870 if (!snd_hdsp_use_is_exclusive(hdsp))
2871 return -EBUSY;
2872 val = ucontrol->value.integer.value[0];
2873 spin_lock_irq(&hdsp->lock);
2874 if (val != hdsp_dds_offset(hdsp))
2875 change = (hdsp_set_dds_offset(hdsp, val) == 0) ? 1 : 0;
2876 else
2877 change = 0;
2878 spin_unlock_irq(&hdsp->lock);
2879 return change;
2880}
2881
2882static const struct snd_kcontrol_new snd_hdsp_9632_controls[] = {
2883HDSP_DA_GAIN("DA Gain", 0),
2884HDSP_AD_GAIN("AD Gain", 0),
2885HDSP_PHONE_GAIN("Phones Gain", 0),
2886HDSP_TOGGLE_SETTING("XLR Breakout Cable", HDSP_XLRBreakoutCable),
2887HDSP_DDS_OFFSET("DDS Sample Rate Offset", 0)
2888};
2889
2890static const struct snd_kcontrol_new snd_hdsp_controls[] = {
2891{
2892 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2893 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,DEFAULT),
2894 .info = snd_hdsp_control_spdif_info,
2895 .get = snd_hdsp_control_spdif_get,
2896 .put = snd_hdsp_control_spdif_put,
2897},
2898{
2899 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_INACTIVE,
2900 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2901 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PCM_STREAM),
2902 .info = snd_hdsp_control_spdif_stream_info,
2903 .get = snd_hdsp_control_spdif_stream_get,
2904 .put = snd_hdsp_control_spdif_stream_put,
2905},
2906{
2907 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2908 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2909 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,CON_MASK),
2910 .info = snd_hdsp_control_spdif_mask_info,
2911 .get = snd_hdsp_control_spdif_mask_get,
2912 .private_value = IEC958_AES0_NONAUDIO |
2913 IEC958_AES0_PROFESSIONAL |
2914 IEC958_AES0_CON_EMPHASIS,
2915},
2916{
2917 .access = SNDRV_CTL_ELEM_ACCESS_READ,
2918 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
2919 .name = SNDRV_CTL_NAME_IEC958("",PLAYBACK,PRO_MASK),
2920 .info = snd_hdsp_control_spdif_mask_info,
2921 .get = snd_hdsp_control_spdif_mask_get,
2922 .private_value = IEC958_AES0_NONAUDIO |
2923 IEC958_AES0_PROFESSIONAL |
2924 IEC958_AES0_PRO_EMPHASIS,
2925},
2926HDSP_MIXER("Mixer", 0),
2927HDSP_SPDIF_IN("IEC958 Input Connector", 0),
2928HDSP_TOGGLE_SETTING("IEC958 Output also on ADAT1", HDSP_SPDIFOpticalOut),
2929HDSP_TOGGLE_SETTING("IEC958 Professional Bit", HDSP_SPDIFProfessional),
2930HDSP_TOGGLE_SETTING("IEC958 Emphasis Bit", HDSP_SPDIFEmphasis),
2931HDSP_TOGGLE_SETTING("IEC958 Non-audio Bit", HDSP_SPDIFNonAudio),
2932
2933HDSP_CLOCK_SOURCE("Sample Clock Source", 0),
2934{
2935 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2936 .name = "Sample Clock Source Locking",
2937 .info = snd_hdsp_info_clock_source_lock,
2938 .get = snd_hdsp_get_clock_source_lock,
2939 .put = snd_hdsp_put_clock_source_lock,
2940},
2941HDSP_SYSTEM_CLOCK_MODE("System Clock Mode", 0),
2942HDSP_PREF_SYNC_REF("Preferred Sync Reference", 0),
2943HDSP_AUTOSYNC_REF("AutoSync Reference", 0),
2944HDSP_SPDIF_SAMPLE_RATE("SPDIF Sample Rate", 0),
2945HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
2946
2947HDSP_AUTOSYNC_SAMPLE_RATE("External Rate", 0),
2948HDSP_WC_SYNC_CHECK("Word Clock Lock Status", 0),
2949HDSP_SPDIF_SYNC_CHECK("SPDIF Lock Status", 0),
2950HDSP_ADATSYNC_SYNC_CHECK("ADAT Sync Lock Status", 0),
2951HDSP_TOGGLE_SETTING("Line Out", HDSP_LineOut),
2952HDSP_PRECISE_POINTER("Precise Pointer", 0),
2953HDSP_USE_MIDI_TASKLET("Use Midi Tasklet", 0),
2954};
2955
2956
2957static int hdsp_rpm_input12(struct hdsp *hdsp)
2958{
2959 switch (hdsp->control_register & HDSP_RPM_Inp12) {
2960 case HDSP_RPM_Inp12_Phon_6dB:
2961 return 0;
2962 case HDSP_RPM_Inp12_Phon_n6dB:
2963 return 2;
2964 case HDSP_RPM_Inp12_Line_0dB:
2965 return 3;
2966 case HDSP_RPM_Inp12_Line_n6dB:
2967 return 4;
2968 }
2969 return 1;
2970}
2971
2972
2973static int snd_hdsp_get_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
2974{
2975 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
2976
2977 ucontrol->value.enumerated.item[0] = hdsp_rpm_input12(hdsp);
2978 return 0;
2979}
2980
2981
2982static int hdsp_set_rpm_input12(struct hdsp *hdsp, int mode)
2983{
2984 hdsp->control_register &= ~HDSP_RPM_Inp12;
2985 switch (mode) {
2986 case 0:
2987 hdsp->control_register |= HDSP_RPM_Inp12_Phon_6dB;
2988 break;
2989 case 1:
2990 break;
2991 case 2:
2992 hdsp->control_register |= HDSP_RPM_Inp12_Phon_n6dB;
2993 break;
2994 case 3:
2995 hdsp->control_register |= HDSP_RPM_Inp12_Line_0dB;
2996 break;
2997 case 4:
2998 hdsp->control_register |= HDSP_RPM_Inp12_Line_n6dB;
2999 break;
3000 default:
3001 return -1;
3002 }
3003
3004 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3005 return 0;
3006}
3007
3008
3009static int snd_hdsp_put_rpm_input12(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3010{
3011 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3012 int change;
3013 int val;
3014
3015 if (!snd_hdsp_use_is_exclusive(hdsp))
3016 return -EBUSY;
3017 val = ucontrol->value.enumerated.item[0];
3018 if (val < 0)
3019 val = 0;
3020 if (val > 4)
3021 val = 4;
3022 spin_lock_irq(&hdsp->lock);
3023 if (val != hdsp_rpm_input12(hdsp))
3024 change = (hdsp_set_rpm_input12(hdsp, val) == 0) ? 1 : 0;
3025 else
3026 change = 0;
3027 spin_unlock_irq(&hdsp->lock);
3028 return change;
3029}
3030
3031
3032static int snd_hdsp_info_rpm_input(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3033{
3034 static const char * const texts[] = {
3035 "Phono +6dB", "Phono 0dB", "Phono -6dB", "Line 0dB", "Line -6dB"
3036 };
3037
3038 return snd_ctl_enum_info(uinfo, 1, 5, texts);
3039}
3040
3041
3042static int hdsp_rpm_input34(struct hdsp *hdsp)
3043{
3044 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3045 case HDSP_RPM_Inp34_Phon_6dB:
3046 return 0;
3047 case HDSP_RPM_Inp34_Phon_n6dB:
3048 return 2;
3049 case HDSP_RPM_Inp34_Line_0dB:
3050 return 3;
3051 case HDSP_RPM_Inp34_Line_n6dB:
3052 return 4;
3053 }
3054 return 1;
3055}
3056
3057
3058static int snd_hdsp_get_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3059{
3060 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3061
3062 ucontrol->value.enumerated.item[0] = hdsp_rpm_input34(hdsp);
3063 return 0;
3064}
3065
3066
3067static int hdsp_set_rpm_input34(struct hdsp *hdsp, int mode)
3068{
3069 hdsp->control_register &= ~HDSP_RPM_Inp34;
3070 switch (mode) {
3071 case 0:
3072 hdsp->control_register |= HDSP_RPM_Inp34_Phon_6dB;
3073 break;
3074 case 1:
3075 break;
3076 case 2:
3077 hdsp->control_register |= HDSP_RPM_Inp34_Phon_n6dB;
3078 break;
3079 case 3:
3080 hdsp->control_register |= HDSP_RPM_Inp34_Line_0dB;
3081 break;
3082 case 4:
3083 hdsp->control_register |= HDSP_RPM_Inp34_Line_n6dB;
3084 break;
3085 default:
3086 return -1;
3087 }
3088
3089 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3090 return 0;
3091}
3092
3093
3094static int snd_hdsp_put_rpm_input34(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3095{
3096 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3097 int change;
3098 int val;
3099
3100 if (!snd_hdsp_use_is_exclusive(hdsp))
3101 return -EBUSY;
3102 val = ucontrol->value.enumerated.item[0];
3103 if (val < 0)
3104 val = 0;
3105 if (val > 4)
3106 val = 4;
3107 spin_lock_irq(&hdsp->lock);
3108 if (val != hdsp_rpm_input34(hdsp))
3109 change = (hdsp_set_rpm_input34(hdsp, val) == 0) ? 1 : 0;
3110 else
3111 change = 0;
3112 spin_unlock_irq(&hdsp->lock);
3113 return change;
3114}
3115
3116
3117
3118static int hdsp_rpm_bypass(struct hdsp *hdsp)
3119{
3120 return (hdsp->control_register & HDSP_RPM_Bypass) ? 1 : 0;
3121}
3122
3123
3124static int snd_hdsp_get_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3125{
3126 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3127
3128 ucontrol->value.integer.value[0] = hdsp_rpm_bypass(hdsp);
3129 return 0;
3130}
3131
3132
3133static int hdsp_set_rpm_bypass(struct hdsp *hdsp, int on)
3134{
3135 if (on)
3136 hdsp->control_register |= HDSP_RPM_Bypass;
3137 else
3138 hdsp->control_register &= ~HDSP_RPM_Bypass;
3139 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3140 return 0;
3141}
3142
3143
3144static int snd_hdsp_put_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3145{
3146 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3147 int change;
3148 unsigned int val;
3149
3150 if (!snd_hdsp_use_is_exclusive(hdsp))
3151 return -EBUSY;
3152 val = ucontrol->value.integer.value[0] & 1;
3153 spin_lock_irq(&hdsp->lock);
3154 change = (int)val != hdsp_rpm_bypass(hdsp);
3155 hdsp_set_rpm_bypass(hdsp, val);
3156 spin_unlock_irq(&hdsp->lock);
3157 return change;
3158}
3159
3160
3161static int snd_hdsp_info_rpm_bypass(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3162{
3163 static const char * const texts[] = {"On", "Off"};
3164
3165 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3166}
3167
3168
3169
3170static int hdsp_rpm_disconnect(struct hdsp *hdsp)
3171{
3172 return (hdsp->control_register & HDSP_RPM_Disconnect) ? 1 : 0;
3173}
3174
3175
3176static int snd_hdsp_get_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3177{
3178 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3179
3180 ucontrol->value.integer.value[0] = hdsp_rpm_disconnect(hdsp);
3181 return 0;
3182}
3183
3184
3185static int hdsp_set_rpm_disconnect(struct hdsp *hdsp, int on)
3186{
3187 if (on)
3188 hdsp->control_register |= HDSP_RPM_Disconnect;
3189 else
3190 hdsp->control_register &= ~HDSP_RPM_Disconnect;
3191 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3192 return 0;
3193}
3194
3195
3196static int snd_hdsp_put_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
3197{
3198 struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
3199 int change;
3200 unsigned int val;
3201
3202 if (!snd_hdsp_use_is_exclusive(hdsp))
3203 return -EBUSY;
3204 val = ucontrol->value.integer.value[0] & 1;
3205 spin_lock_irq(&hdsp->lock);
3206 change = (int)val != hdsp_rpm_disconnect(hdsp);
3207 hdsp_set_rpm_disconnect(hdsp, val);
3208 spin_unlock_irq(&hdsp->lock);
3209 return change;
3210}
3211
3212static int snd_hdsp_info_rpm_disconnect(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
3213{
3214 static const char * const texts[] = {"On", "Off"};
3215
3216 return snd_ctl_enum_info(uinfo, 1, 2, texts);
3217}
3218
3219static const struct snd_kcontrol_new snd_hdsp_rpm_controls[] = {
3220 {
3221 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3222 .name = "RPM Bypass",
3223 .get = snd_hdsp_get_rpm_bypass,
3224 .put = snd_hdsp_put_rpm_bypass,
3225 .info = snd_hdsp_info_rpm_bypass
3226 },
3227 {
3228 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3229 .name = "RPM Disconnect",
3230 .get = snd_hdsp_get_rpm_disconnect,
3231 .put = snd_hdsp_put_rpm_disconnect,
3232 .info = snd_hdsp_info_rpm_disconnect
3233 },
3234 {
3235 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3236 .name = "Input 1/2",
3237 .get = snd_hdsp_get_rpm_input12,
3238 .put = snd_hdsp_put_rpm_input12,
3239 .info = snd_hdsp_info_rpm_input
3240 },
3241 {
3242 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
3243 .name = "Input 3/4",
3244 .get = snd_hdsp_get_rpm_input34,
3245 .put = snd_hdsp_put_rpm_input34,
3246 .info = snd_hdsp_info_rpm_input
3247 },
3248 HDSP_SYSTEM_SAMPLE_RATE("System Sample Rate", 0),
3249 HDSP_MIXER("Mixer", 0)
3250};
3251
3252static const struct snd_kcontrol_new snd_hdsp_96xx_aeb =
3253 HDSP_TOGGLE_SETTING("Analog Extension Board",
3254 HDSP_AnalogExtensionBoard);
3255static struct snd_kcontrol_new snd_hdsp_adat_sync_check = HDSP_ADAT_SYNC_CHECK;
3256
3257static int snd_hdsp_create_controls(struct snd_card *card, struct hdsp *hdsp)
3258{
3259 unsigned int idx;
3260 int err;
3261 struct snd_kcontrol *kctl;
3262
3263 if (hdsp->io_type == RPM) {
3264
3265 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_rpm_controls); idx++) {
3266 err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_rpm_controls[idx], hdsp));
3267 if (err < 0)
3268 return err;
3269 }
3270 return 0;
3271 }
3272
3273 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_controls); idx++) {
3274 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_controls[idx], hdsp))) < 0)
3275 return err;
3276 if (idx == 1)
3277 hdsp->spdif_ctl = kctl;
3278 }
3279
3280
3281 snd_hdsp_adat_sync_check.name = "ADAT Lock Status";
3282 snd_hdsp_adat_sync_check.index = 1;
3283 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3284 return err;
3285 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
3286 for (idx = 1; idx < 3; ++idx) {
3287 snd_hdsp_adat_sync_check.index = idx+1;
3288 if ((err = snd_ctl_add (card, kctl = snd_ctl_new1(&snd_hdsp_adat_sync_check, hdsp))))
3289 return err;
3290 }
3291 }
3292
3293
3294 if (hdsp->io_type == H9632) {
3295 for (idx = 0; idx < ARRAY_SIZE(snd_hdsp_9632_controls); idx++) {
3296 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_9632_controls[idx], hdsp))) < 0)
3297 return err;
3298 }
3299 }
3300
3301
3302 if (hdsp->io_type == H9632 || hdsp->io_type == H9652) {
3303 if ((err = snd_ctl_add(card, kctl = snd_ctl_new1(&snd_hdsp_96xx_aeb, hdsp))) < 0)
3304 return err;
3305 }
3306
3307 return 0;
3308}
3309
3310
3311
3312
3313
3314static void
3315snd_hdsp_proc_read(struct snd_info_entry *entry, struct snd_info_buffer *buffer)
3316{
3317 struct hdsp *hdsp = entry->private_data;
3318 unsigned int status;
3319 unsigned int status2;
3320 char *pref_sync_ref;
3321 char *autosync_ref;
3322 char *system_clock_mode;
3323 char *clock_source;
3324 int x;
3325
3326 status = hdsp_read(hdsp, HDSP_statusRegister);
3327 status2 = hdsp_read(hdsp, HDSP_status2Register);
3328
3329 snd_iprintf(buffer, "%s (Card #%d)\n", hdsp->card_name,
3330 hdsp->card->number + 1);
3331 snd_iprintf(buffer, "Buffers: capture %p playback %p\n",
3332 hdsp->capture_buffer, hdsp->playback_buffer);
3333 snd_iprintf(buffer, "IRQ: %d Registers bus: 0x%lx VM: 0x%lx\n",
3334 hdsp->irq, hdsp->port, (unsigned long)hdsp->iobase);
3335 snd_iprintf(buffer, "Control register: 0x%x\n", hdsp->control_register);
3336 snd_iprintf(buffer, "Control2 register: 0x%x\n",
3337 hdsp->control2_register);
3338 snd_iprintf(buffer, "Status register: 0x%x\n", status);
3339 snd_iprintf(buffer, "Status2 register: 0x%x\n", status2);
3340
3341 if (hdsp_check_for_iobox(hdsp)) {
3342 snd_iprintf(buffer, "No I/O box connected.\n"
3343 "Please connect one and upload firmware.\n");
3344 return;
3345 }
3346
3347 if (hdsp_check_for_firmware(hdsp, 0)) {
3348 if (hdsp->state & HDSP_FirmwareCached) {
3349 if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
3350 snd_iprintf(buffer, "Firmware loading from "
3351 "cache failed, "
3352 "please upload manually.\n");
3353 return;
3354 }
3355 } else {
3356 int err;
3357
3358 err = hdsp_request_fw_loader(hdsp);
3359 if (err < 0) {
3360 snd_iprintf(buffer,
3361 "No firmware loaded nor cached, "
3362 "please upload firmware.\n");
3363 return;
3364 }
3365 }
3366 }
3367
3368 snd_iprintf(buffer, "FIFO status: %d\n", hdsp_read(hdsp, HDSP_fifoStatus) & 0xff);
3369 snd_iprintf(buffer, "MIDI1 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut0));
3370 snd_iprintf(buffer, "MIDI1 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn0));
3371 snd_iprintf(buffer, "MIDI2 Output status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusOut1));
3372 snd_iprintf(buffer, "MIDI2 Input status: 0x%x\n", hdsp_read(hdsp, HDSP_midiStatusIn1));
3373 snd_iprintf(buffer, "Use Midi Tasklet: %s\n", hdsp->use_midi_tasklet ? "on" : "off");
3374
3375 snd_iprintf(buffer, "\n");
3376
3377 x = 1 << (6 + hdsp_decode_latency(hdsp->control_register & HDSP_LatencyMask));
3378
3379 snd_iprintf(buffer, "Buffer Size (Latency): %d samples (2 periods of %lu bytes)\n", x, (unsigned long) hdsp->period_bytes);
3380 snd_iprintf(buffer, "Hardware pointer (frames): %ld\n", hdsp_hw_pointer(hdsp));
3381 snd_iprintf(buffer, "Precise pointer: %s\n", hdsp->precise_ptr ? "on" : "off");
3382 snd_iprintf(buffer, "Line out: %s\n", (hdsp->control_register & HDSP_LineOut) ? "on" : "off");
3383
3384 snd_iprintf(buffer, "Firmware version: %d\n", (status2&HDSP_version0)|(status2&HDSP_version1)<<1|(status2&HDSP_version2)<<2);
3385
3386 snd_iprintf(buffer, "\n");
3387
3388 switch (hdsp_clock_source(hdsp)) {
3389 case HDSP_CLOCK_SOURCE_AUTOSYNC:
3390 clock_source = "AutoSync";
3391 break;
3392 case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
3393 clock_source = "Internal 32 kHz";
3394 break;
3395 case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
3396 clock_source = "Internal 44.1 kHz";
3397 break;
3398 case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
3399 clock_source = "Internal 48 kHz";
3400 break;
3401 case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
3402 clock_source = "Internal 64 kHz";
3403 break;
3404 case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
3405 clock_source = "Internal 88.2 kHz";
3406 break;
3407 case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
3408 clock_source = "Internal 96 kHz";
3409 break;
3410 case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
3411 clock_source = "Internal 128 kHz";
3412 break;
3413 case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
3414 clock_source = "Internal 176.4 kHz";
3415 break;
3416 case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ:
3417 clock_source = "Internal 192 kHz";
3418 break;
3419 default:
3420 clock_source = "Error";
3421 }
3422 snd_iprintf (buffer, "Sample Clock Source: %s\n", clock_source);
3423
3424 if (hdsp_system_clock_mode(hdsp))
3425 system_clock_mode = "Slave";
3426 else
3427 system_clock_mode = "Master";
3428
3429 switch (hdsp_pref_sync_ref (hdsp)) {
3430 case HDSP_SYNC_FROM_WORD:
3431 pref_sync_ref = "Word Clock";
3432 break;
3433 case HDSP_SYNC_FROM_ADAT_SYNC:
3434 pref_sync_ref = "ADAT Sync";
3435 break;
3436 case HDSP_SYNC_FROM_SPDIF:
3437 pref_sync_ref = "SPDIF";
3438 break;
3439 case HDSP_SYNC_FROM_ADAT1:
3440 pref_sync_ref = "ADAT1";
3441 break;
3442 case HDSP_SYNC_FROM_ADAT2:
3443 pref_sync_ref = "ADAT2";
3444 break;
3445 case HDSP_SYNC_FROM_ADAT3:
3446 pref_sync_ref = "ADAT3";
3447 break;
3448 default:
3449 pref_sync_ref = "Word Clock";
3450 break;
3451 }
3452 snd_iprintf (buffer, "Preferred Sync Reference: %s\n", pref_sync_ref);
3453
3454 switch (hdsp_autosync_ref (hdsp)) {
3455 case HDSP_AUTOSYNC_FROM_WORD:
3456 autosync_ref = "Word Clock";
3457 break;
3458 case HDSP_AUTOSYNC_FROM_ADAT_SYNC:
3459 autosync_ref = "ADAT Sync";
3460 break;
3461 case HDSP_AUTOSYNC_FROM_SPDIF:
3462 autosync_ref = "SPDIF";
3463 break;
3464 case HDSP_AUTOSYNC_FROM_NONE:
3465 autosync_ref = "None";
3466 break;
3467 case HDSP_AUTOSYNC_FROM_ADAT1:
3468 autosync_ref = "ADAT1";
3469 break;
3470 case HDSP_AUTOSYNC_FROM_ADAT2:
3471 autosync_ref = "ADAT2";
3472 break;
3473 case HDSP_AUTOSYNC_FROM_ADAT3:
3474 autosync_ref = "ADAT3";
3475 break;
3476 default:
3477 autosync_ref = "---";
3478 break;
3479 }
3480 snd_iprintf (buffer, "AutoSync Reference: %s\n", autosync_ref);
3481
3482 snd_iprintf (buffer, "AutoSync Frequency: %d\n", hdsp_external_sample_rate(hdsp));
3483
3484 snd_iprintf (buffer, "System Clock Mode: %s\n", system_clock_mode);
3485
3486 snd_iprintf (buffer, "System Clock Frequency: %d\n", hdsp->system_sample_rate);
3487 snd_iprintf (buffer, "System Clock Locked: %s\n", hdsp->clock_source_locked ? "Yes" : "No");
3488
3489 snd_iprintf(buffer, "\n");
3490
3491 if (hdsp->io_type != RPM) {
3492 switch (hdsp_spdif_in(hdsp)) {
3493 case HDSP_SPDIFIN_OPTICAL:
3494 snd_iprintf(buffer, "IEC958 input: Optical\n");
3495 break;
3496 case HDSP_SPDIFIN_COAXIAL:
3497 snd_iprintf(buffer, "IEC958 input: Coaxial\n");
3498 break;
3499 case HDSP_SPDIFIN_INTERNAL:
3500 snd_iprintf(buffer, "IEC958 input: Internal\n");
3501 break;
3502 case HDSP_SPDIFIN_AES:
3503 snd_iprintf(buffer, "IEC958 input: AES\n");
3504 break;
3505 default:
3506 snd_iprintf(buffer, "IEC958 input: ???\n");
3507 break;
3508 }
3509 }
3510
3511 if (RPM == hdsp->io_type) {
3512 if (hdsp->control_register & HDSP_RPM_Bypass)
3513 snd_iprintf(buffer, "RPM Bypass: disabled\n");
3514 else
3515 snd_iprintf(buffer, "RPM Bypass: enabled\n");
3516 if (hdsp->control_register & HDSP_RPM_Disconnect)
3517 snd_iprintf(buffer, "RPM disconnected\n");
3518 else
3519 snd_iprintf(buffer, "RPM connected\n");
3520
3521 switch (hdsp->control_register & HDSP_RPM_Inp12) {
3522 case HDSP_RPM_Inp12_Phon_6dB:
3523 snd_iprintf(buffer, "Input 1/2: Phono, 6dB\n");
3524 break;
3525 case HDSP_RPM_Inp12_Phon_0dB:
3526 snd_iprintf(buffer, "Input 1/2: Phono, 0dB\n");
3527 break;
3528 case HDSP_RPM_Inp12_Phon_n6dB:
3529 snd_iprintf(buffer, "Input 1/2: Phono, -6dB\n");
3530 break;
3531 case HDSP_RPM_Inp12_Line_0dB:
3532 snd_iprintf(buffer, "Input 1/2: Line, 0dB\n");
3533 break;
3534 case HDSP_RPM_Inp12_Line_n6dB:
3535 snd_iprintf(buffer, "Input 1/2: Line, -6dB\n");
3536 break;
3537 default:
3538 snd_iprintf(buffer, "Input 1/2: ???\n");
3539 }
3540
3541 switch (hdsp->control_register & HDSP_RPM_Inp34) {
3542 case HDSP_RPM_Inp34_Phon_6dB:
3543 snd_iprintf(buffer, "Input 3/4: Phono, 6dB\n");
3544 break;
3545 case HDSP_RPM_Inp34_Phon_0dB:
3546 snd_iprintf(buffer, "Input 3/4: Phono, 0dB\n");
3547 break;
3548 case HDSP_RPM_Inp34_Phon_n6dB:
3549 snd_iprintf(buffer, "Input 3/4: Phono, -6dB\n");
3550 break;
3551 case HDSP_RPM_Inp34_Line_0dB:
3552 snd_iprintf(buffer, "Input 3/4: Line, 0dB\n");
3553 break;
3554 case HDSP_RPM_Inp34_Line_n6dB:
3555 snd_iprintf(buffer, "Input 3/4: Line, -6dB\n");
3556 break;
3557 default:
3558 snd_iprintf(buffer, "Input 3/4: ???\n");
3559 }
3560
3561 } else {
3562 if (hdsp->control_register & HDSP_SPDIFOpticalOut)
3563 snd_iprintf(buffer, "IEC958 output: Coaxial & ADAT1\n");
3564 else
3565 snd_iprintf(buffer, "IEC958 output: Coaxial only\n");
3566
3567 if (hdsp->control_register & HDSP_SPDIFProfessional)
3568 snd_iprintf(buffer, "IEC958 quality: Professional\n");
3569 else
3570 snd_iprintf(buffer, "IEC958 quality: Consumer\n");
3571
3572 if (hdsp->control_register & HDSP_SPDIFEmphasis)
3573 snd_iprintf(buffer, "IEC958 emphasis: on\n");
3574 else
3575 snd_iprintf(buffer, "IEC958 emphasis: off\n");
3576
3577 if (hdsp->control_register & HDSP_SPDIFNonAudio)
3578 snd_iprintf(buffer, "IEC958 NonAudio: on\n");
3579 else
3580 snd_iprintf(buffer, "IEC958 NonAudio: off\n");
3581 x = hdsp_spdif_sample_rate(hdsp);
3582 if (x != 0)
3583 snd_iprintf(buffer, "IEC958 sample rate: %d\n", x);
3584 else
3585 snd_iprintf(buffer, "IEC958 sample rate: Error flag set\n");
3586 }
3587 snd_iprintf(buffer, "\n");
3588
3589
3590 x = status & HDSP_Sync0;
3591 if (status & HDSP_Lock0)
3592 snd_iprintf(buffer, "ADAT1: %s\n", x ? "Sync" : "Lock");
3593 else
3594 snd_iprintf(buffer, "ADAT1: No Lock\n");
3595
3596 switch (hdsp->io_type) {
3597 case Digiface:
3598 case H9652:
3599 x = status & HDSP_Sync1;
3600 if (status & HDSP_Lock1)
3601 snd_iprintf(buffer, "ADAT2: %s\n", x ? "Sync" : "Lock");
3602 else
3603 snd_iprintf(buffer, "ADAT2: No Lock\n");
3604 x = status & HDSP_Sync2;
3605 if (status & HDSP_Lock2)
3606 snd_iprintf(buffer, "ADAT3: %s\n", x ? "Sync" : "Lock");
3607 else
3608 snd_iprintf(buffer, "ADAT3: No Lock\n");
3609 break;
3610 default:
3611
3612 break;
3613 }
3614
3615 x = status & HDSP_SPDIFSync;
3616 if (status & HDSP_SPDIFErrorFlag)
3617 snd_iprintf (buffer, "SPDIF: No Lock\n");
3618 else
3619 snd_iprintf (buffer, "SPDIF: %s\n", x ? "Sync" : "Lock");
3620
3621 x = status2 & HDSP_wc_sync;
3622 if (status2 & HDSP_wc_lock)
3623 snd_iprintf (buffer, "Word Clock: %s\n", x ? "Sync" : "Lock");
3624 else
3625 snd_iprintf (buffer, "Word Clock: No Lock\n");
3626
3627 x = status & HDSP_TimecodeSync;
3628 if (status & HDSP_TimecodeLock)
3629 snd_iprintf(buffer, "ADAT Sync: %s\n", x ? "Sync" : "Lock");
3630 else
3631 snd_iprintf(buffer, "ADAT Sync: No Lock\n");
3632
3633 snd_iprintf(buffer, "\n");
3634
3635
3636 if (hdsp->io_type == H9632) {
3637 char *tmp;
3638
3639 switch (hdsp_ad_gain(hdsp)) {
3640 case 0:
3641 tmp = "-10 dBV";
3642 break;
3643 case 1:
3644 tmp = "+4 dBu";
3645 break;
3646 default:
3647 tmp = "Lo Gain";
3648 break;
3649 }
3650 snd_iprintf(buffer, "AD Gain : %s\n", tmp);
3651
3652 switch (hdsp_da_gain(hdsp)) {
3653 case 0:
3654 tmp = "Hi Gain";
3655 break;
3656 case 1:
3657 tmp = "+4 dBu";
3658 break;
3659 default:
3660 tmp = "-10 dBV";
3661 break;
3662 }
3663 snd_iprintf(buffer, "DA Gain : %s\n", tmp);
3664
3665 switch (hdsp_phone_gain(hdsp)) {
3666 case 0:
3667 tmp = "0 dB";
3668 break;
3669 case 1:
3670 tmp = "-6 dB";
3671 break;
3672 default:
3673 tmp = "-12 dB";
3674 break;
3675 }
3676 snd_iprintf(buffer, "Phones Gain : %s\n", tmp);
3677
3678 snd_iprintf(buffer, "XLR Breakout Cable : %s\n",
3679 hdsp_toggle_setting(hdsp, HDSP_XLRBreakoutCable) ?
3680 "yes" : "no");
3681
3682 if (hdsp->control_register & HDSP_AnalogExtensionBoard)
3683 snd_iprintf(buffer, "AEB : on (ADAT1 internal)\n");
3684 else
3685 snd_iprintf(buffer, "AEB : off (ADAT1 external)\n");
3686 snd_iprintf(buffer, "\n");
3687 }
3688
3689}
3690
3691static void snd_hdsp_proc_init(struct hdsp *hdsp)
3692{
3693 snd_card_ro_proc_new(hdsp->card, "hdsp", hdsp, snd_hdsp_proc_read);
3694}
3695
3696static void snd_hdsp_free_buffers(struct hdsp *hdsp)
3697{
3698 snd_hammerfall_free_buffer(&hdsp->capture_dma_buf, hdsp->pci);
3699 snd_hammerfall_free_buffer(&hdsp->playback_dma_buf, hdsp->pci);
3700}
3701
3702static int snd_hdsp_initialize_memory(struct hdsp *hdsp)
3703{
3704 unsigned long pb_bus, cb_bus;
3705
3706 if (snd_hammerfall_get_buffer(hdsp->pci, &hdsp->capture_dma_buf, HDSP_DMA_AREA_BYTES) < 0 ||
3707 snd_hammerfall_get_buffer(hdsp->pci, &hdsp->playback_dma_buf, HDSP_DMA_AREA_BYTES) < 0) {
3708 if (hdsp->capture_dma_buf.area)
3709 snd_dma_free_pages(&hdsp->capture_dma_buf);
3710 dev_err(hdsp->card->dev,
3711 "%s: no buffers available\n", hdsp->card_name);
3712 return -ENOMEM;
3713 }
3714
3715
3716
3717 cb_bus = ALIGN(hdsp->capture_dma_buf.addr, 0x10000ul);
3718 pb_bus = ALIGN(hdsp->playback_dma_buf.addr, 0x10000ul);
3719
3720
3721
3722 hdsp_write(hdsp, HDSP_inputBufferAddress, cb_bus);
3723 hdsp_write(hdsp, HDSP_outputBufferAddress, pb_bus);
3724
3725 hdsp->capture_buffer = hdsp->capture_dma_buf.area + (cb_bus - hdsp->capture_dma_buf.addr);
3726 hdsp->playback_buffer = hdsp->playback_dma_buf.area + (pb_bus - hdsp->playback_dma_buf.addr);
3727
3728 return 0;
3729}
3730
3731static int snd_hdsp_set_defaults(struct hdsp *hdsp)
3732{
3733 unsigned int i;
3734
3735
3736
3737
3738
3739
3740
3741
3742
3743
3744
3745
3746
3747
3748
3749 hdsp->control_register = HDSP_ClockModeMaster |
3750 HDSP_SPDIFInputCoaxial |
3751 hdsp_encode_latency(7) |
3752 HDSP_LineOut;
3753
3754
3755 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3756
3757#ifdef SNDRV_BIG_ENDIAN
3758 hdsp->control2_register = HDSP_BIGENDIAN_MODE;
3759#else
3760 hdsp->control2_register = 0;
3761#endif
3762 if (hdsp->io_type == H9652)
3763 snd_hdsp_9652_enable_mixer (hdsp);
3764 else
3765 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
3766
3767 hdsp_reset_hw_pointer(hdsp);
3768 hdsp_compute_period_size(hdsp);
3769
3770
3771
3772 for (i = 0; i < HDSP_MATRIX_MIXER_SIZE; ++i)
3773 hdsp->mixer_matrix[i] = MINUS_INFINITY_GAIN;
3774
3775 for (i = 0; i < ((hdsp->io_type == H9652 || hdsp->io_type == H9632) ? 1352 : HDSP_MATRIX_MIXER_SIZE); ++i) {
3776 if (hdsp_write_gain (hdsp, i, MINUS_INFINITY_GAIN))
3777 return -EIO;
3778 }
3779
3780
3781 if (hdsp->io_type == H9632) {
3782 hdsp->control_register |= (HDSP_DAGainPlus4dBu | HDSP_ADGainPlus4dBu | HDSP_PhoneGain0dB);
3783 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3784 }
3785
3786
3787
3788
3789 hdsp_set_rate(hdsp, 48000, 1);
3790
3791 return 0;
3792}
3793
3794static void hdsp_midi_tasklet(struct tasklet_struct *t)
3795{
3796 struct hdsp *hdsp = from_tasklet(hdsp, t, midi_tasklet);
3797
3798 if (hdsp->midi[0].pending)
3799 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3800 if (hdsp->midi[1].pending)
3801 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3802}
3803
3804static irqreturn_t snd_hdsp_interrupt(int irq, void *dev_id)
3805{
3806 struct hdsp *hdsp = (struct hdsp *) dev_id;
3807 unsigned int status;
3808 int audio;
3809 int midi0;
3810 int midi1;
3811 unsigned int midi0status;
3812 unsigned int midi1status;
3813 int schedule = 0;
3814
3815 status = hdsp_read(hdsp, HDSP_statusRegister);
3816
3817 audio = status & HDSP_audioIRQPending;
3818 midi0 = status & HDSP_midi0IRQPending;
3819 midi1 = status & HDSP_midi1IRQPending;
3820
3821 if (!audio && !midi0 && !midi1)
3822 return IRQ_NONE;
3823
3824 hdsp_write(hdsp, HDSP_interruptConfirmation, 0);
3825
3826 midi0status = hdsp_read (hdsp, HDSP_midiStatusIn0) & 0xff;
3827 midi1status = hdsp_read (hdsp, HDSP_midiStatusIn1) & 0xff;
3828
3829 if (!(hdsp->state & HDSP_InitializationComplete))
3830 return IRQ_HANDLED;
3831
3832 if (audio) {
3833 if (hdsp->capture_substream)
3834 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream);
3835
3836 if (hdsp->playback_substream)
3837 snd_pcm_period_elapsed(hdsp->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK].substream);
3838 }
3839
3840 if (midi0 && midi0status) {
3841 if (hdsp->use_midi_tasklet) {
3842
3843 hdsp->control_register &= ~HDSP_Midi0InterruptEnable;
3844 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3845 hdsp->midi[0].pending = 1;
3846 schedule = 1;
3847 } else {
3848 snd_hdsp_midi_input_read (&hdsp->midi[0]);
3849 }
3850 }
3851 if (hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632 && midi1 && midi1status) {
3852 if (hdsp->use_midi_tasklet) {
3853
3854 hdsp->control_register &= ~HDSP_Midi1InterruptEnable;
3855 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
3856 hdsp->midi[1].pending = 1;
3857 schedule = 1;
3858 } else {
3859 snd_hdsp_midi_input_read (&hdsp->midi[1]);
3860 }
3861 }
3862 if (hdsp->use_midi_tasklet && schedule)
3863 tasklet_schedule(&hdsp->midi_tasklet);
3864 return IRQ_HANDLED;
3865}
3866
3867static snd_pcm_uframes_t snd_hdsp_hw_pointer(struct snd_pcm_substream *substream)
3868{
3869 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3870 return hdsp_hw_pointer(hdsp);
3871}
3872
3873static char *hdsp_channel_buffer_location(struct hdsp *hdsp,
3874 int stream,
3875 int channel)
3876
3877{
3878 int mapped_channel;
3879
3880 if (snd_BUG_ON(channel < 0 || channel >= hdsp->max_channels))
3881 return NULL;
3882
3883 if ((mapped_channel = hdsp->channel_map[channel]) < 0)
3884 return NULL;
3885
3886 if (stream == SNDRV_PCM_STREAM_CAPTURE)
3887 return hdsp->capture_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3888 else
3889 return hdsp->playback_buffer + (mapped_channel * HDSP_CHANNEL_BUFFER_BYTES);
3890}
3891
3892static int snd_hdsp_playback_copy(struct snd_pcm_substream *substream,
3893 int channel, unsigned long pos,
3894 void __user *src, unsigned long count)
3895{
3896 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3897 char *channel_buf;
3898
3899 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3900 return -EINVAL;
3901
3902 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3903 if (snd_BUG_ON(!channel_buf))
3904 return -EIO;
3905 if (copy_from_user(channel_buf + pos, src, count))
3906 return -EFAULT;
3907 return 0;
3908}
3909
3910static int snd_hdsp_playback_copy_kernel(struct snd_pcm_substream *substream,
3911 int channel, unsigned long pos,
3912 void *src, unsigned long count)
3913{
3914 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3915 char *channel_buf;
3916
3917 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3918 if (snd_BUG_ON(!channel_buf))
3919 return -EIO;
3920 memcpy(channel_buf + pos, src, count);
3921 return 0;
3922}
3923
3924static int snd_hdsp_capture_copy(struct snd_pcm_substream *substream,
3925 int channel, unsigned long pos,
3926 void __user *dst, unsigned long count)
3927{
3928 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3929 char *channel_buf;
3930
3931 if (snd_BUG_ON(pos + count > HDSP_CHANNEL_BUFFER_BYTES))
3932 return -EINVAL;
3933
3934 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3935 if (snd_BUG_ON(!channel_buf))
3936 return -EIO;
3937 if (copy_to_user(dst, channel_buf + pos, count))
3938 return -EFAULT;
3939 return 0;
3940}
3941
3942static int snd_hdsp_capture_copy_kernel(struct snd_pcm_substream *substream,
3943 int channel, unsigned long pos,
3944 void *dst, unsigned long count)
3945{
3946 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3947 char *channel_buf;
3948
3949 channel_buf = hdsp_channel_buffer_location(hdsp, substream->pstr->stream, channel);
3950 if (snd_BUG_ON(!channel_buf))
3951 return -EIO;
3952 memcpy(dst, channel_buf + pos, count);
3953 return 0;
3954}
3955
3956static int snd_hdsp_hw_silence(struct snd_pcm_substream *substream,
3957 int channel, unsigned long pos,
3958 unsigned long count)
3959{
3960 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3961 char *channel_buf;
3962
3963 channel_buf = hdsp_channel_buffer_location (hdsp, substream->pstr->stream, channel);
3964 if (snd_BUG_ON(!channel_buf))
3965 return -EIO;
3966 memset(channel_buf + pos, 0, count);
3967 return 0;
3968}
3969
3970static int snd_hdsp_reset(struct snd_pcm_substream *substream)
3971{
3972 struct snd_pcm_runtime *runtime = substream->runtime;
3973 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
3974 struct snd_pcm_substream *other;
3975 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
3976 other = hdsp->capture_substream;
3977 else
3978 other = hdsp->playback_substream;
3979 if (hdsp->running)
3980 runtime->status->hw_ptr = hdsp_hw_pointer(hdsp);
3981 else
3982 runtime->status->hw_ptr = 0;
3983 if (other) {
3984 struct snd_pcm_substream *s;
3985 struct snd_pcm_runtime *oruntime = other->runtime;
3986 snd_pcm_group_for_each_entry(s, substream) {
3987 if (s == other) {
3988 oruntime->status->hw_ptr = runtime->status->hw_ptr;
3989 break;
3990 }
3991 }
3992 }
3993 return 0;
3994}
3995
3996static int snd_hdsp_hw_params(struct snd_pcm_substream *substream,
3997 struct snd_pcm_hw_params *params)
3998{
3999 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4000 int err;
4001 pid_t this_pid;
4002 pid_t other_pid;
4003
4004 if (hdsp_check_for_iobox (hdsp))
4005 return -EIO;
4006
4007 if (hdsp_check_for_firmware(hdsp, 1))
4008 return -EIO;
4009
4010 spin_lock_irq(&hdsp->lock);
4011
4012 if (substream->pstr->stream == SNDRV_PCM_STREAM_PLAYBACK) {
4013 hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
4014 hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= hdsp->creg_spdif_stream);
4015 this_pid = hdsp->playback_pid;
4016 other_pid = hdsp->capture_pid;
4017 } else {
4018 this_pid = hdsp->capture_pid;
4019 other_pid = hdsp->playback_pid;
4020 }
4021
4022 if ((other_pid > 0) && (this_pid != other_pid)) {
4023
4024
4025
4026
4027
4028
4029 if (params_rate(params) != hdsp->system_sample_rate) {
4030 spin_unlock_irq(&hdsp->lock);
4031 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4032 return -EBUSY;
4033 }
4034
4035 if (params_period_size(params) != hdsp->period_bytes / 4) {
4036 spin_unlock_irq(&hdsp->lock);
4037 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4038 return -EBUSY;
4039 }
4040
4041
4042
4043 spin_unlock_irq(&hdsp->lock);
4044 return 0;
4045
4046 } else {
4047 spin_unlock_irq(&hdsp->lock);
4048 }
4049
4050
4051
4052
4053 spin_lock_irq(&hdsp->lock);
4054 if (! hdsp->clock_source_locked) {
4055 if ((err = hdsp_set_rate(hdsp, params_rate(params), 0)) < 0) {
4056 spin_unlock_irq(&hdsp->lock);
4057 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_RATE);
4058 return err;
4059 }
4060 }
4061 spin_unlock_irq(&hdsp->lock);
4062
4063 if ((err = hdsp_set_interrupt_interval(hdsp, params_period_size(params))) < 0) {
4064 _snd_pcm_hw_param_setempty(params, SNDRV_PCM_HW_PARAM_PERIOD_SIZE);
4065 return err;
4066 }
4067
4068 return 0;
4069}
4070
4071static int snd_hdsp_channel_info(struct snd_pcm_substream *substream,
4072 struct snd_pcm_channel_info *info)
4073{
4074 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4075 unsigned int channel = info->channel;
4076
4077 if (snd_BUG_ON(channel >= hdsp->max_channels))
4078 return -EINVAL;
4079 channel = array_index_nospec(channel, hdsp->max_channels);
4080
4081 if (hdsp->channel_map[channel] < 0)
4082 return -EINVAL;
4083
4084 info->offset = hdsp->channel_map[channel] * HDSP_CHANNEL_BUFFER_BYTES;
4085 info->first = 0;
4086 info->step = 32;
4087 return 0;
4088}
4089
4090static int snd_hdsp_ioctl(struct snd_pcm_substream *substream,
4091 unsigned int cmd, void *arg)
4092{
4093 switch (cmd) {
4094 case SNDRV_PCM_IOCTL1_RESET:
4095 return snd_hdsp_reset(substream);
4096 case SNDRV_PCM_IOCTL1_CHANNEL_INFO:
4097 return snd_hdsp_channel_info(substream, arg);
4098 default:
4099 break;
4100 }
4101
4102 return snd_pcm_lib_ioctl(substream, cmd, arg);
4103}
4104
4105static int snd_hdsp_trigger(struct snd_pcm_substream *substream, int cmd)
4106{
4107 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4108 struct snd_pcm_substream *other;
4109 int running;
4110
4111 if (hdsp_check_for_iobox (hdsp))
4112 return -EIO;
4113
4114 if (hdsp_check_for_firmware(hdsp, 0))
4115 return -EIO;
4116
4117 spin_lock(&hdsp->lock);
4118 running = hdsp->running;
4119 switch (cmd) {
4120 case SNDRV_PCM_TRIGGER_START:
4121 running |= 1 << substream->stream;
4122 break;
4123 case SNDRV_PCM_TRIGGER_STOP:
4124 running &= ~(1 << substream->stream);
4125 break;
4126 default:
4127 snd_BUG();
4128 spin_unlock(&hdsp->lock);
4129 return -EINVAL;
4130 }
4131 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4132 other = hdsp->capture_substream;
4133 else
4134 other = hdsp->playback_substream;
4135
4136 if (other) {
4137 struct snd_pcm_substream *s;
4138 snd_pcm_group_for_each_entry(s, substream) {
4139 if (s == other) {
4140 snd_pcm_trigger_done(s, substream);
4141 if (cmd == SNDRV_PCM_TRIGGER_START)
4142 running |= 1 << s->stream;
4143 else
4144 running &= ~(1 << s->stream);
4145 goto _ok;
4146 }
4147 }
4148 if (cmd == SNDRV_PCM_TRIGGER_START) {
4149 if (!(running & (1 << SNDRV_PCM_STREAM_PLAYBACK)) &&
4150 substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4151 hdsp_silence_playback(hdsp);
4152 } else {
4153 if (running &&
4154 substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
4155 hdsp_silence_playback(hdsp);
4156 }
4157 } else {
4158 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
4159 hdsp_silence_playback(hdsp);
4160 }
4161 _ok:
4162 snd_pcm_trigger_done(substream, substream);
4163 if (!hdsp->running && running)
4164 hdsp_start_audio(hdsp);
4165 else if (hdsp->running && !running)
4166 hdsp_stop_audio(hdsp);
4167 hdsp->running = running;
4168 spin_unlock(&hdsp->lock);
4169
4170 return 0;
4171}
4172
4173static int snd_hdsp_prepare(struct snd_pcm_substream *substream)
4174{
4175 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4176 int result = 0;
4177
4178 if (hdsp_check_for_iobox (hdsp))
4179 return -EIO;
4180
4181 if (hdsp_check_for_firmware(hdsp, 1))
4182 return -EIO;
4183
4184 spin_lock_irq(&hdsp->lock);
4185 if (!hdsp->running)
4186 hdsp_reset_hw_pointer(hdsp);
4187 spin_unlock_irq(&hdsp->lock);
4188 return result;
4189}
4190
4191static const struct snd_pcm_hardware snd_hdsp_playback_subinfo =
4192{
4193 .info = (SNDRV_PCM_INFO_MMAP |
4194 SNDRV_PCM_INFO_MMAP_VALID |
4195 SNDRV_PCM_INFO_NONINTERLEAVED |
4196 SNDRV_PCM_INFO_SYNC_START |
4197 SNDRV_PCM_INFO_DOUBLE),
4198#ifdef SNDRV_BIG_ENDIAN
4199 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4200#else
4201 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4202#endif
4203 .rates = (SNDRV_PCM_RATE_32000 |
4204 SNDRV_PCM_RATE_44100 |
4205 SNDRV_PCM_RATE_48000 |
4206 SNDRV_PCM_RATE_64000 |
4207 SNDRV_PCM_RATE_88200 |
4208 SNDRV_PCM_RATE_96000),
4209 .rate_min = 32000,
4210 .rate_max = 96000,
4211 .channels_min = 6,
4212 .channels_max = HDSP_MAX_CHANNELS,
4213 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4214 .period_bytes_min = (64 * 4) * 10,
4215 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4216 .periods_min = 2,
4217 .periods_max = 2,
4218 .fifo_size = 0
4219};
4220
4221static const struct snd_pcm_hardware snd_hdsp_capture_subinfo =
4222{
4223 .info = (SNDRV_PCM_INFO_MMAP |
4224 SNDRV_PCM_INFO_MMAP_VALID |
4225 SNDRV_PCM_INFO_NONINTERLEAVED |
4226 SNDRV_PCM_INFO_SYNC_START),
4227#ifdef SNDRV_BIG_ENDIAN
4228 .formats = SNDRV_PCM_FMTBIT_S32_BE,
4229#else
4230 .formats = SNDRV_PCM_FMTBIT_S32_LE,
4231#endif
4232 .rates = (SNDRV_PCM_RATE_32000 |
4233 SNDRV_PCM_RATE_44100 |
4234 SNDRV_PCM_RATE_48000 |
4235 SNDRV_PCM_RATE_64000 |
4236 SNDRV_PCM_RATE_88200 |
4237 SNDRV_PCM_RATE_96000),
4238 .rate_min = 32000,
4239 .rate_max = 96000,
4240 .channels_min = 5,
4241 .channels_max = HDSP_MAX_CHANNELS,
4242 .buffer_bytes_max = HDSP_CHANNEL_BUFFER_BYTES * HDSP_MAX_CHANNELS,
4243 .period_bytes_min = (64 * 4) * 10,
4244 .period_bytes_max = (8192 * 4) * HDSP_MAX_CHANNELS,
4245 .periods_min = 2,
4246 .periods_max = 2,
4247 .fifo_size = 0
4248};
4249
4250static const unsigned int hdsp_period_sizes[] = { 64, 128, 256, 512, 1024, 2048, 4096, 8192 };
4251
4252static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_period_sizes = {
4253 .count = ARRAY_SIZE(hdsp_period_sizes),
4254 .list = hdsp_period_sizes,
4255 .mask = 0
4256};
4257
4258static const unsigned int hdsp_9632_sample_rates[] = { 32000, 44100, 48000, 64000, 88200, 96000, 128000, 176400, 192000 };
4259
4260static const struct snd_pcm_hw_constraint_list hdsp_hw_constraints_9632_sample_rates = {
4261 .count = ARRAY_SIZE(hdsp_9632_sample_rates),
4262 .list = hdsp_9632_sample_rates,
4263 .mask = 0
4264};
4265
4266static int snd_hdsp_hw_rule_in_channels(struct snd_pcm_hw_params *params,
4267 struct snd_pcm_hw_rule *rule)
4268{
4269 struct hdsp *hdsp = rule->private;
4270 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4271 if (hdsp->io_type == H9632) {
4272 unsigned int list[3];
4273 list[0] = hdsp->qs_in_channels;
4274 list[1] = hdsp->ds_in_channels;
4275 list[2] = hdsp->ss_in_channels;
4276 return snd_interval_list(c, 3, list, 0);
4277 } else {
4278 unsigned int list[2];
4279 list[0] = hdsp->ds_in_channels;
4280 list[1] = hdsp->ss_in_channels;
4281 return snd_interval_list(c, 2, list, 0);
4282 }
4283}
4284
4285static int snd_hdsp_hw_rule_out_channels(struct snd_pcm_hw_params *params,
4286 struct snd_pcm_hw_rule *rule)
4287{
4288 unsigned int list[3];
4289 struct hdsp *hdsp = rule->private;
4290 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4291 if (hdsp->io_type == H9632) {
4292 list[0] = hdsp->qs_out_channels;
4293 list[1] = hdsp->ds_out_channels;
4294 list[2] = hdsp->ss_out_channels;
4295 return snd_interval_list(c, 3, list, 0);
4296 } else {
4297 list[0] = hdsp->ds_out_channels;
4298 list[1] = hdsp->ss_out_channels;
4299 }
4300 return snd_interval_list(c, 2, list, 0);
4301}
4302
4303static int snd_hdsp_hw_rule_in_channels_rate(struct snd_pcm_hw_params *params,
4304 struct snd_pcm_hw_rule *rule)
4305{
4306 struct hdsp *hdsp = rule->private;
4307 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4308 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4309 if (r->min > 96000 && hdsp->io_type == H9632) {
4310 struct snd_interval t = {
4311 .min = hdsp->qs_in_channels,
4312 .max = hdsp->qs_in_channels,
4313 .integer = 1,
4314 };
4315 return snd_interval_refine(c, &t);
4316 } else if (r->min > 48000 && r->max <= 96000) {
4317 struct snd_interval t = {
4318 .min = hdsp->ds_in_channels,
4319 .max = hdsp->ds_in_channels,
4320 .integer = 1,
4321 };
4322 return snd_interval_refine(c, &t);
4323 } else if (r->max < 64000) {
4324 struct snd_interval t = {
4325 .min = hdsp->ss_in_channels,
4326 .max = hdsp->ss_in_channels,
4327 .integer = 1,
4328 };
4329 return snd_interval_refine(c, &t);
4330 }
4331 return 0;
4332}
4333
4334static int snd_hdsp_hw_rule_out_channels_rate(struct snd_pcm_hw_params *params,
4335 struct snd_pcm_hw_rule *rule)
4336{
4337 struct hdsp *hdsp = rule->private;
4338 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4339 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4340 if (r->min > 96000 && hdsp->io_type == H9632) {
4341 struct snd_interval t = {
4342 .min = hdsp->qs_out_channels,
4343 .max = hdsp->qs_out_channels,
4344 .integer = 1,
4345 };
4346 return snd_interval_refine(c, &t);
4347 } else if (r->min > 48000 && r->max <= 96000) {
4348 struct snd_interval t = {
4349 .min = hdsp->ds_out_channels,
4350 .max = hdsp->ds_out_channels,
4351 .integer = 1,
4352 };
4353 return snd_interval_refine(c, &t);
4354 } else if (r->max < 64000) {
4355 struct snd_interval t = {
4356 .min = hdsp->ss_out_channels,
4357 .max = hdsp->ss_out_channels,
4358 .integer = 1,
4359 };
4360 return snd_interval_refine(c, &t);
4361 }
4362 return 0;
4363}
4364
4365static int snd_hdsp_hw_rule_rate_out_channels(struct snd_pcm_hw_params *params,
4366 struct snd_pcm_hw_rule *rule)
4367{
4368 struct hdsp *hdsp = rule->private;
4369 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4370 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4371 if (c->min >= hdsp->ss_out_channels) {
4372 struct snd_interval t = {
4373 .min = 32000,
4374 .max = 48000,
4375 .integer = 1,
4376 };
4377 return snd_interval_refine(r, &t);
4378 } else if (c->max <= hdsp->qs_out_channels && hdsp->io_type == H9632) {
4379 struct snd_interval t = {
4380 .min = 128000,
4381 .max = 192000,
4382 .integer = 1,
4383 };
4384 return snd_interval_refine(r, &t);
4385 } else if (c->max <= hdsp->ds_out_channels) {
4386 struct snd_interval t = {
4387 .min = 64000,
4388 .max = 96000,
4389 .integer = 1,
4390 };
4391 return snd_interval_refine(r, &t);
4392 }
4393 return 0;
4394}
4395
4396static int snd_hdsp_hw_rule_rate_in_channels(struct snd_pcm_hw_params *params,
4397 struct snd_pcm_hw_rule *rule)
4398{
4399 struct hdsp *hdsp = rule->private;
4400 struct snd_interval *c = hw_param_interval(params, SNDRV_PCM_HW_PARAM_CHANNELS);
4401 struct snd_interval *r = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
4402 if (c->min >= hdsp->ss_in_channels) {
4403 struct snd_interval t = {
4404 .min = 32000,
4405 .max = 48000,
4406 .integer = 1,
4407 };
4408 return snd_interval_refine(r, &t);
4409 } else if (c->max <= hdsp->qs_in_channels && hdsp->io_type == H9632) {
4410 struct snd_interval t = {
4411 .min = 128000,
4412 .max = 192000,
4413 .integer = 1,
4414 };
4415 return snd_interval_refine(r, &t);
4416 } else if (c->max <= hdsp->ds_in_channels) {
4417 struct snd_interval t = {
4418 .min = 64000,
4419 .max = 96000,
4420 .integer = 1,
4421 };
4422 return snd_interval_refine(r, &t);
4423 }
4424 return 0;
4425}
4426
4427static int snd_hdsp_playback_open(struct snd_pcm_substream *substream)
4428{
4429 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4430 struct snd_pcm_runtime *runtime = substream->runtime;
4431
4432 if (hdsp_check_for_iobox (hdsp))
4433 return -EIO;
4434
4435 if (hdsp_check_for_firmware(hdsp, 1))
4436 return -EIO;
4437
4438 spin_lock_irq(&hdsp->lock);
4439
4440 snd_pcm_set_sync(substream);
4441
4442 runtime->hw = snd_hdsp_playback_subinfo;
4443 runtime->dma_area = hdsp->playback_buffer;
4444 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4445
4446 hdsp->playback_pid = current->pid;
4447 hdsp->playback_substream = substream;
4448
4449 spin_unlock_irq(&hdsp->lock);
4450
4451 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4452 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4453 if (hdsp->clock_source_locked) {
4454 runtime->hw.rate_min = runtime->hw.rate_max = hdsp->system_sample_rate;
4455 } else if (hdsp->io_type == H9632) {
4456 runtime->hw.rate_max = 192000;
4457 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4458 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4459 }
4460 if (hdsp->io_type == H9632) {
4461 runtime->hw.channels_min = hdsp->qs_out_channels;
4462 runtime->hw.channels_max = hdsp->ss_out_channels;
4463 }
4464
4465 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4466 snd_hdsp_hw_rule_out_channels, hdsp,
4467 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4468 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4469 snd_hdsp_hw_rule_out_channels_rate, hdsp,
4470 SNDRV_PCM_HW_PARAM_RATE, -1);
4471 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4472 snd_hdsp_hw_rule_rate_out_channels, hdsp,
4473 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4474
4475 if (RPM != hdsp->io_type) {
4476 hdsp->creg_spdif_stream = hdsp->creg_spdif;
4477 hdsp->spdif_ctl->vd[0].access &= ~SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4478 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4479 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4480 }
4481 return 0;
4482}
4483
4484static int snd_hdsp_playback_release(struct snd_pcm_substream *substream)
4485{
4486 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4487
4488 spin_lock_irq(&hdsp->lock);
4489
4490 hdsp->playback_pid = -1;
4491 hdsp->playback_substream = NULL;
4492
4493 spin_unlock_irq(&hdsp->lock);
4494
4495 if (RPM != hdsp->io_type) {
4496 hdsp->spdif_ctl->vd[0].access |= SNDRV_CTL_ELEM_ACCESS_INACTIVE;
4497 snd_ctl_notify(hdsp->card, SNDRV_CTL_EVENT_MASK_VALUE |
4498 SNDRV_CTL_EVENT_MASK_INFO, &hdsp->spdif_ctl->id);
4499 }
4500 return 0;
4501}
4502
4503
4504static int snd_hdsp_capture_open(struct snd_pcm_substream *substream)
4505{
4506 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4507 struct snd_pcm_runtime *runtime = substream->runtime;
4508
4509 if (hdsp_check_for_iobox (hdsp))
4510 return -EIO;
4511
4512 if (hdsp_check_for_firmware(hdsp, 1))
4513 return -EIO;
4514
4515 spin_lock_irq(&hdsp->lock);
4516
4517 snd_pcm_set_sync(substream);
4518
4519 runtime->hw = snd_hdsp_capture_subinfo;
4520 runtime->dma_area = hdsp->capture_buffer;
4521 runtime->dma_bytes = HDSP_DMA_AREA_BYTES;
4522
4523 hdsp->capture_pid = current->pid;
4524 hdsp->capture_substream = substream;
4525
4526 spin_unlock_irq(&hdsp->lock);
4527
4528 snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
4529 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_SIZE, &hdsp_hw_constraints_period_sizes);
4530 if (hdsp->io_type == H9632) {
4531 runtime->hw.channels_min = hdsp->qs_in_channels;
4532 runtime->hw.channels_max = hdsp->ss_in_channels;
4533 runtime->hw.rate_max = 192000;
4534 runtime->hw.rates = SNDRV_PCM_RATE_KNOT;
4535 snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hdsp_hw_constraints_9632_sample_rates);
4536 }
4537 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4538 snd_hdsp_hw_rule_in_channels, hdsp,
4539 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4540 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
4541 snd_hdsp_hw_rule_in_channels_rate, hdsp,
4542 SNDRV_PCM_HW_PARAM_RATE, -1);
4543 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_RATE,
4544 snd_hdsp_hw_rule_rate_in_channels, hdsp,
4545 SNDRV_PCM_HW_PARAM_CHANNELS, -1);
4546 return 0;
4547}
4548
4549static int snd_hdsp_capture_release(struct snd_pcm_substream *substream)
4550{
4551 struct hdsp *hdsp = snd_pcm_substream_chip(substream);
4552
4553 spin_lock_irq(&hdsp->lock);
4554
4555 hdsp->capture_pid = -1;
4556 hdsp->capture_substream = NULL;
4557
4558 spin_unlock_irq(&hdsp->lock);
4559 return 0;
4560}
4561
4562
4563static inline int copy_u32_le(void __user *dest, void __iomem *src)
4564{
4565 u32 val = readl(src);
4566 return copy_to_user(dest, &val, 4);
4567}
4568
4569static inline int copy_u64_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4570{
4571 u32 rms_low, rms_high;
4572 u64 rms;
4573 rms_low = readl(src_low);
4574 rms_high = readl(src_high);
4575 rms = ((u64)rms_high << 32) | rms_low;
4576 return copy_to_user(dest, &rms, 8);
4577}
4578
4579static inline int copy_u48_le(void __user *dest, void __iomem *src_low, void __iomem *src_high)
4580{
4581 u32 rms_low, rms_high;
4582 u64 rms;
4583 rms_low = readl(src_low) & 0xffffff00;
4584 rms_high = readl(src_high) & 0xffffff00;
4585 rms = ((u64)rms_high << 32) | rms_low;
4586 return copy_to_user(dest, &rms, 8);
4587}
4588
4589static int hdsp_9652_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4590{
4591 int doublespeed = 0;
4592 int i, j, channels, ofs;
4593
4594 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4595 doublespeed = 1;
4596 channels = doublespeed ? 14 : 26;
4597 for (i = 0, j = 0; i < 26; ++i) {
4598 if (doublespeed && (i & 4))
4599 continue;
4600 ofs = HDSP_9652_peakBase - j * 4;
4601 if (copy_u32_le(&peak_rms->input_peaks[i], hdsp->iobase + ofs))
4602 return -EFAULT;
4603 ofs -= channels * 4;
4604 if (copy_u32_le(&peak_rms->playback_peaks[i], hdsp->iobase + ofs))
4605 return -EFAULT;
4606 ofs -= channels * 4;
4607 if (copy_u32_le(&peak_rms->output_peaks[i], hdsp->iobase + ofs))
4608 return -EFAULT;
4609 ofs = HDSP_9652_rmsBase + j * 8;
4610 if (copy_u48_le(&peak_rms->input_rms[i], hdsp->iobase + ofs,
4611 hdsp->iobase + ofs + 4))
4612 return -EFAULT;
4613 ofs += channels * 8;
4614 if (copy_u48_le(&peak_rms->playback_rms[i], hdsp->iobase + ofs,
4615 hdsp->iobase + ofs + 4))
4616 return -EFAULT;
4617 ofs += channels * 8;
4618 if (copy_u48_le(&peak_rms->output_rms[i], hdsp->iobase + ofs,
4619 hdsp->iobase + ofs + 4))
4620 return -EFAULT;
4621 j++;
4622 }
4623 return 0;
4624}
4625
4626static int hdsp_9632_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4627{
4628 int i, j;
4629 struct hdsp_9632_meters __iomem *m;
4630 int doublespeed = 0;
4631
4632 if (hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DoubleSpeedStatus)
4633 doublespeed = 1;
4634 m = (struct hdsp_9632_meters __iomem *)(hdsp->iobase+HDSP_9632_metersBase);
4635 for (i = 0, j = 0; i < 16; ++i, ++j) {
4636 if (copy_u32_le(&peak_rms->input_peaks[i], &m->input_peak[j]))
4637 return -EFAULT;
4638 if (copy_u32_le(&peak_rms->playback_peaks[i], &m->playback_peak[j]))
4639 return -EFAULT;
4640 if (copy_u32_le(&peak_rms->output_peaks[i], &m->output_peak[j]))
4641 return -EFAULT;
4642 if (copy_u64_le(&peak_rms->input_rms[i], &m->input_rms_low[j],
4643 &m->input_rms_high[j]))
4644 return -EFAULT;
4645 if (copy_u64_le(&peak_rms->playback_rms[i], &m->playback_rms_low[j],
4646 &m->playback_rms_high[j]))
4647 return -EFAULT;
4648 if (copy_u64_le(&peak_rms->output_rms[i], &m->output_rms_low[j],
4649 &m->output_rms_high[j]))
4650 return -EFAULT;
4651 if (doublespeed && i == 3) i += 4;
4652 }
4653 return 0;
4654}
4655
4656static int hdsp_get_peak(struct hdsp *hdsp, struct hdsp_peak_rms __user *peak_rms)
4657{
4658 int i;
4659
4660 for (i = 0; i < 26; i++) {
4661 if (copy_u32_le(&peak_rms->playback_peaks[i],
4662 hdsp->iobase + HDSP_playbackPeakLevel + i * 4))
4663 return -EFAULT;
4664 if (copy_u32_le(&peak_rms->input_peaks[i],
4665 hdsp->iobase + HDSP_inputPeakLevel + i * 4))
4666 return -EFAULT;
4667 }
4668 for (i = 0; i < 28; i++) {
4669 if (copy_u32_le(&peak_rms->output_peaks[i],
4670 hdsp->iobase + HDSP_outputPeakLevel + i * 4))
4671 return -EFAULT;
4672 }
4673 for (i = 0; i < 26; ++i) {
4674 if (copy_u64_le(&peak_rms->playback_rms[i],
4675 hdsp->iobase + HDSP_playbackRmsLevel + i * 8 + 4,
4676 hdsp->iobase + HDSP_playbackRmsLevel + i * 8))
4677 return -EFAULT;
4678 if (copy_u64_le(&peak_rms->input_rms[i],
4679 hdsp->iobase + HDSP_inputRmsLevel + i * 8 + 4,
4680 hdsp->iobase + HDSP_inputRmsLevel + i * 8))
4681 return -EFAULT;
4682 }
4683 return 0;
4684}
4685
4686static int snd_hdsp_hwdep_ioctl(struct snd_hwdep *hw, struct file *file, unsigned int cmd, unsigned long arg)
4687{
4688 struct hdsp *hdsp = hw->private_data;
4689 void __user *argp = (void __user *)arg;
4690 int err;
4691
4692 switch (cmd) {
4693 case SNDRV_HDSP_IOCTL_GET_PEAK_RMS: {
4694 struct hdsp_peak_rms __user *peak_rms = (struct hdsp_peak_rms __user *)arg;
4695
4696 err = hdsp_check_for_iobox(hdsp);
4697 if (err < 0)
4698 return err;
4699
4700 err = hdsp_check_for_firmware(hdsp, 1);
4701 if (err < 0)
4702 return err;
4703
4704 if (!(hdsp->state & HDSP_FirmwareLoaded)) {
4705 dev_err(hdsp->card->dev,
4706 "firmware needs to be uploaded to the card.\n");
4707 return -EINVAL;
4708 }
4709
4710 switch (hdsp->io_type) {
4711 case H9652:
4712 return hdsp_9652_get_peak(hdsp, peak_rms);
4713 case H9632:
4714 return hdsp_9632_get_peak(hdsp, peak_rms);
4715 default:
4716 return hdsp_get_peak(hdsp, peak_rms);
4717 }
4718 }
4719 case SNDRV_HDSP_IOCTL_GET_CONFIG_INFO: {
4720 struct hdsp_config_info info;
4721 unsigned long flags;
4722 int i;
4723
4724 err = hdsp_check_for_iobox(hdsp);
4725 if (err < 0)
4726 return err;
4727
4728 err = hdsp_check_for_firmware(hdsp, 1);
4729 if (err < 0)
4730 return err;
4731
4732 memset(&info, 0, sizeof(info));
4733 spin_lock_irqsave(&hdsp->lock, flags);
4734 info.pref_sync_ref = (unsigned char)hdsp_pref_sync_ref(hdsp);
4735 info.wordclock_sync_check = (unsigned char)hdsp_wc_sync_check(hdsp);
4736 if (hdsp->io_type != H9632)
4737 info.adatsync_sync_check = (unsigned char)hdsp_adatsync_sync_check(hdsp);
4738 info.spdif_sync_check = (unsigned char)hdsp_spdif_sync_check(hdsp);
4739 for (i = 0; i < ((hdsp->io_type != Multiface && hdsp->io_type != RPM && hdsp->io_type != H9632) ? 3 : 1); ++i)
4740 info.adat_sync_check[i] = (unsigned char)hdsp_adat_sync_check(hdsp, i);
4741 info.spdif_in = (unsigned char)hdsp_spdif_in(hdsp);
4742 info.spdif_out = (unsigned char)hdsp_toggle_setting(hdsp,
4743 HDSP_SPDIFOpticalOut);
4744 info.spdif_professional = (unsigned char)
4745 hdsp_toggle_setting(hdsp, HDSP_SPDIFProfessional);
4746 info.spdif_emphasis = (unsigned char)
4747 hdsp_toggle_setting(hdsp, HDSP_SPDIFEmphasis);
4748 info.spdif_nonaudio = (unsigned char)
4749 hdsp_toggle_setting(hdsp, HDSP_SPDIFNonAudio);
4750 info.spdif_sample_rate = hdsp_spdif_sample_rate(hdsp);
4751 info.system_sample_rate = hdsp->system_sample_rate;
4752 info.autosync_sample_rate = hdsp_external_sample_rate(hdsp);
4753 info.system_clock_mode = (unsigned char)hdsp_system_clock_mode(hdsp);
4754 info.clock_source = (unsigned char)hdsp_clock_source(hdsp);
4755 info.autosync_ref = (unsigned char)hdsp_autosync_ref(hdsp);
4756 info.line_out = (unsigned char)
4757 hdsp_toggle_setting(hdsp, HDSP_LineOut);
4758 if (hdsp->io_type == H9632) {
4759 info.da_gain = (unsigned char)hdsp_da_gain(hdsp);
4760 info.ad_gain = (unsigned char)hdsp_ad_gain(hdsp);
4761 info.phone_gain = (unsigned char)hdsp_phone_gain(hdsp);
4762 info.xlr_breakout_cable =
4763 (unsigned char)hdsp_toggle_setting(hdsp,
4764 HDSP_XLRBreakoutCable);
4765
4766 } else if (hdsp->io_type == RPM) {
4767 info.da_gain = (unsigned char) hdsp_rpm_input12(hdsp);
4768 info.ad_gain = (unsigned char) hdsp_rpm_input34(hdsp);
4769 }
4770 if (hdsp->io_type == H9632 || hdsp->io_type == H9652)
4771 info.analog_extension_board =
4772 (unsigned char)hdsp_toggle_setting(hdsp,
4773 HDSP_AnalogExtensionBoard);
4774 spin_unlock_irqrestore(&hdsp->lock, flags);
4775 if (copy_to_user(argp, &info, sizeof(info)))
4776 return -EFAULT;
4777 break;
4778 }
4779 case SNDRV_HDSP_IOCTL_GET_9632_AEB: {
4780 struct hdsp_9632_aeb h9632_aeb;
4781
4782 if (hdsp->io_type != H9632) return -EINVAL;
4783 h9632_aeb.aebi = hdsp->ss_in_channels - H9632_SS_CHANNELS;
4784 h9632_aeb.aebo = hdsp->ss_out_channels - H9632_SS_CHANNELS;
4785 if (copy_to_user(argp, &h9632_aeb, sizeof(h9632_aeb)))
4786 return -EFAULT;
4787 break;
4788 }
4789 case SNDRV_HDSP_IOCTL_GET_VERSION: {
4790 struct hdsp_version hdsp_version;
4791 int err;
4792
4793 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4794 if (hdsp->io_type == Undefined) {
4795 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
4796 return err;
4797 }
4798 memset(&hdsp_version, 0, sizeof(hdsp_version));
4799 hdsp_version.io_type = hdsp->io_type;
4800 hdsp_version.firmware_rev = hdsp->firmware_rev;
4801 if ((err = copy_to_user(argp, &hdsp_version, sizeof(hdsp_version))))
4802 return -EFAULT;
4803 break;
4804 }
4805 case SNDRV_HDSP_IOCTL_UPLOAD_FIRMWARE: {
4806 struct hdsp_firmware firmware;
4807 u32 __user *firmware_data;
4808 int err;
4809
4810 if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return -EINVAL;
4811
4812 if (hdsp->io_type == Undefined) return -EINVAL;
4813
4814 if (hdsp->state & (HDSP_FirmwareCached | HDSP_FirmwareLoaded))
4815 return -EBUSY;
4816
4817 dev_info(hdsp->card->dev,
4818 "initializing firmware upload\n");
4819 if (copy_from_user(&firmware, argp, sizeof(firmware)))
4820 return -EFAULT;
4821 firmware_data = (u32 __user *)firmware.firmware_data;
4822
4823 if (hdsp_check_for_iobox (hdsp))
4824 return -EIO;
4825
4826 if (!hdsp->fw_uploaded) {
4827 hdsp->fw_uploaded = vmalloc(HDSP_FIRMWARE_SIZE);
4828 if (!hdsp->fw_uploaded)
4829 return -ENOMEM;
4830 }
4831
4832 if (copy_from_user(hdsp->fw_uploaded, firmware_data,
4833 HDSP_FIRMWARE_SIZE)) {
4834 vfree(hdsp->fw_uploaded);
4835 hdsp->fw_uploaded = NULL;
4836 return -EFAULT;
4837 }
4838
4839 hdsp->state |= HDSP_FirmwareCached;
4840
4841 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
4842 return err;
4843
4844 if (!(hdsp->state & HDSP_InitializationComplete)) {
4845 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
4846 return err;
4847
4848 snd_hdsp_initialize_channels(hdsp);
4849 snd_hdsp_initialize_midi_flush(hdsp);
4850
4851 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
4852 dev_err(hdsp->card->dev,
4853 "error creating alsa devices\n");
4854 return err;
4855 }
4856 }
4857 break;
4858 }
4859 case SNDRV_HDSP_IOCTL_GET_MIXER: {
4860 struct hdsp_mixer __user *mixer = (struct hdsp_mixer __user *)argp;
4861 if (copy_to_user(mixer->matrix, hdsp->mixer_matrix, sizeof(unsigned short)*HDSP_MATRIX_MIXER_SIZE))
4862 return -EFAULT;
4863 break;
4864 }
4865 default:
4866 return -EINVAL;
4867 }
4868 return 0;
4869}
4870
4871static const struct snd_pcm_ops snd_hdsp_playback_ops = {
4872 .open = snd_hdsp_playback_open,
4873 .close = snd_hdsp_playback_release,
4874 .ioctl = snd_hdsp_ioctl,
4875 .hw_params = snd_hdsp_hw_params,
4876 .prepare = snd_hdsp_prepare,
4877 .trigger = snd_hdsp_trigger,
4878 .pointer = snd_hdsp_hw_pointer,
4879 .copy_user = snd_hdsp_playback_copy,
4880 .copy_kernel = snd_hdsp_playback_copy_kernel,
4881 .fill_silence = snd_hdsp_hw_silence,
4882};
4883
4884static const struct snd_pcm_ops snd_hdsp_capture_ops = {
4885 .open = snd_hdsp_capture_open,
4886 .close = snd_hdsp_capture_release,
4887 .ioctl = snd_hdsp_ioctl,
4888 .hw_params = snd_hdsp_hw_params,
4889 .prepare = snd_hdsp_prepare,
4890 .trigger = snd_hdsp_trigger,
4891 .pointer = snd_hdsp_hw_pointer,
4892 .copy_user = snd_hdsp_capture_copy,
4893 .copy_kernel = snd_hdsp_capture_copy_kernel,
4894};
4895
4896static int snd_hdsp_create_hwdep(struct snd_card *card, struct hdsp *hdsp)
4897{
4898 struct snd_hwdep *hw;
4899 int err;
4900
4901 if ((err = snd_hwdep_new(card, "HDSP hwdep", 0, &hw)) < 0)
4902 return err;
4903
4904 hdsp->hwdep = hw;
4905 hw->private_data = hdsp;
4906 strcpy(hw->name, "HDSP hwdep interface");
4907
4908 hw->ops.ioctl = snd_hdsp_hwdep_ioctl;
4909 hw->ops.ioctl_compat = snd_hdsp_hwdep_ioctl;
4910
4911 return 0;
4912}
4913
4914static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp)
4915{
4916 struct snd_pcm *pcm;
4917 int err;
4918
4919 if ((err = snd_pcm_new(card, hdsp->card_name, 0, 1, 1, &pcm)) < 0)
4920 return err;
4921
4922 hdsp->pcm = pcm;
4923 pcm->private_data = hdsp;
4924 strcpy(pcm->name, hdsp->card_name);
4925
4926 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_hdsp_playback_ops);
4927 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_hdsp_capture_ops);
4928
4929 pcm->info_flags = SNDRV_PCM_INFO_JOINT_DUPLEX;
4930
4931 return 0;
4932}
4933
4934static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp)
4935{
4936 hdsp->control2_register |= HDSP_9652_ENABLE_MIXER;
4937 hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
4938}
4939
4940static int snd_hdsp_enable_io (struct hdsp *hdsp)
4941{
4942 int i;
4943
4944 if (hdsp_fifo_wait (hdsp, 0, 100)) {
4945 dev_err(hdsp->card->dev,
4946 "enable_io fifo_wait failed\n");
4947 return -EIO;
4948 }
4949
4950 for (i = 0; i < hdsp->max_channels; ++i) {
4951 hdsp_write (hdsp, HDSP_inputEnable + (4 * i), 1);
4952 hdsp_write (hdsp, HDSP_outputEnable + (4 * i), 1);
4953 }
4954
4955 return 0;
4956}
4957
4958static void snd_hdsp_initialize_channels(struct hdsp *hdsp)
4959{
4960 int status, aebi_channels, aebo_channels;
4961
4962 switch (hdsp->io_type) {
4963 case Digiface:
4964 hdsp->card_name = "RME Hammerfall DSP + Digiface";
4965 hdsp->ss_in_channels = hdsp->ss_out_channels = DIGIFACE_SS_CHANNELS;
4966 hdsp->ds_in_channels = hdsp->ds_out_channels = DIGIFACE_DS_CHANNELS;
4967 break;
4968
4969 case H9652:
4970 hdsp->card_name = "RME Hammerfall HDSP 9652";
4971 hdsp->ss_in_channels = hdsp->ss_out_channels = H9652_SS_CHANNELS;
4972 hdsp->ds_in_channels = hdsp->ds_out_channels = H9652_DS_CHANNELS;
4973 break;
4974
4975 case H9632:
4976 status = hdsp_read(hdsp, HDSP_statusRegister);
4977
4978 aebi_channels = (status & HDSP_AEBI) ? 0 : 4;
4979 aebo_channels = (status & HDSP_AEBO) ? 0 : 4;
4980 hdsp->card_name = "RME Hammerfall HDSP 9632";
4981 hdsp->ss_in_channels = H9632_SS_CHANNELS+aebi_channels;
4982 hdsp->ds_in_channels = H9632_DS_CHANNELS+aebi_channels;
4983 hdsp->qs_in_channels = H9632_QS_CHANNELS+aebi_channels;
4984 hdsp->ss_out_channels = H9632_SS_CHANNELS+aebo_channels;
4985 hdsp->ds_out_channels = H9632_DS_CHANNELS+aebo_channels;
4986 hdsp->qs_out_channels = H9632_QS_CHANNELS+aebo_channels;
4987 break;
4988
4989 case Multiface:
4990 hdsp->card_name = "RME Hammerfall DSP + Multiface";
4991 hdsp->ss_in_channels = hdsp->ss_out_channels = MULTIFACE_SS_CHANNELS;
4992 hdsp->ds_in_channels = hdsp->ds_out_channels = MULTIFACE_DS_CHANNELS;
4993 break;
4994
4995 case RPM:
4996 hdsp->card_name = "RME Hammerfall DSP + RPM";
4997 hdsp->ss_in_channels = RPM_CHANNELS-1;
4998 hdsp->ss_out_channels = RPM_CHANNELS;
4999 hdsp->ds_in_channels = RPM_CHANNELS-1;
5000 hdsp->ds_out_channels = RPM_CHANNELS;
5001 break;
5002
5003 default:
5004
5005 break;
5006 }
5007}
5008
5009static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp)
5010{
5011 snd_hdsp_flush_midi_input (hdsp, 0);
5012 snd_hdsp_flush_midi_input (hdsp, 1);
5013}
5014
5015static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp)
5016{
5017 int err;
5018
5019 if ((err = snd_hdsp_create_pcm(card, hdsp)) < 0) {
5020 dev_err(card->dev,
5021 "Error creating pcm interface\n");
5022 return err;
5023 }
5024
5025
5026 if ((err = snd_hdsp_create_midi(card, hdsp, 0)) < 0) {
5027 dev_err(card->dev,
5028 "Error creating first midi interface\n");
5029 return err;
5030 }
5031
5032 if (hdsp->io_type == Digiface || hdsp->io_type == H9652) {
5033 if ((err = snd_hdsp_create_midi(card, hdsp, 1)) < 0) {
5034 dev_err(card->dev,
5035 "Error creating second midi interface\n");
5036 return err;
5037 }
5038 }
5039
5040 if ((err = snd_hdsp_create_controls(card, hdsp)) < 0) {
5041 dev_err(card->dev,
5042 "Error creating ctl interface\n");
5043 return err;
5044 }
5045
5046 snd_hdsp_proc_init(hdsp);
5047
5048 hdsp->system_sample_rate = -1;
5049 hdsp->playback_pid = -1;
5050 hdsp->capture_pid = -1;
5051 hdsp->capture_substream = NULL;
5052 hdsp->playback_substream = NULL;
5053
5054 if ((err = snd_hdsp_set_defaults(hdsp)) < 0) {
5055 dev_err(card->dev,
5056 "Error setting default values\n");
5057 return err;
5058 }
5059
5060 if (!(hdsp->state & HDSP_InitializationComplete)) {
5061 strcpy(card->shortname, "Hammerfall DSP");
5062 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5063 hdsp->port, hdsp->irq);
5064
5065 if ((err = snd_card_register(card)) < 0) {
5066 dev_err(card->dev,
5067 "error registering card\n");
5068 return err;
5069 }
5070 hdsp->state |= HDSP_InitializationComplete;
5071 }
5072
5073 return 0;
5074}
5075
5076
5077static int hdsp_request_fw_loader(struct hdsp *hdsp)
5078{
5079 const char *fwfile;
5080 const struct firmware *fw;
5081 int err;
5082
5083 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5084 return 0;
5085 if (hdsp->io_type == Undefined) {
5086 if ((err = hdsp_get_iobox_version(hdsp)) < 0)
5087 return err;
5088 if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
5089 return 0;
5090 }
5091
5092
5093 switch (hdsp->io_type) {
5094 case RPM:
5095 fwfile = "rpm_firmware.bin";
5096 break;
5097 case Multiface:
5098 if (hdsp->firmware_rev == 0xa)
5099 fwfile = "multiface_firmware.bin";
5100 else
5101 fwfile = "multiface_firmware_rev11.bin";
5102 break;
5103 case Digiface:
5104 if (hdsp->firmware_rev == 0xa)
5105 fwfile = "digiface_firmware.bin";
5106 else
5107 fwfile = "digiface_firmware_rev11.bin";
5108 break;
5109 default:
5110 dev_err(hdsp->card->dev,
5111 "invalid io_type %d\n", hdsp->io_type);
5112 return -EINVAL;
5113 }
5114
5115 if (request_firmware(&fw, fwfile, &hdsp->pci->dev)) {
5116 dev_err(hdsp->card->dev,
5117 "cannot load firmware %s\n", fwfile);
5118 return -ENOENT;
5119 }
5120 if (fw->size < HDSP_FIRMWARE_SIZE) {
5121 dev_err(hdsp->card->dev,
5122 "too short firmware size %d (expected %d)\n",
5123 (int)fw->size, HDSP_FIRMWARE_SIZE);
5124 release_firmware(fw);
5125 return -EINVAL;
5126 }
5127
5128 hdsp->firmware = fw;
5129
5130 hdsp->state |= HDSP_FirmwareCached;
5131
5132 if ((err = snd_hdsp_load_firmware_from_cache(hdsp)) < 0)
5133 return err;
5134
5135 if (!(hdsp->state & HDSP_InitializationComplete)) {
5136 if ((err = snd_hdsp_enable_io(hdsp)) < 0)
5137 return err;
5138
5139 if ((err = snd_hdsp_create_hwdep(hdsp->card, hdsp)) < 0) {
5140 dev_err(hdsp->card->dev,
5141 "error creating hwdep device\n");
5142 return err;
5143 }
5144 snd_hdsp_initialize_channels(hdsp);
5145 snd_hdsp_initialize_midi_flush(hdsp);
5146 if ((err = snd_hdsp_create_alsa_devices(hdsp->card, hdsp)) < 0) {
5147 dev_err(hdsp->card->dev,
5148 "error creating alsa devices\n");
5149 return err;
5150 }
5151 }
5152 return 0;
5153}
5154
5155static int snd_hdsp_create(struct snd_card *card,
5156 struct hdsp *hdsp)
5157{
5158 struct pci_dev *pci = hdsp->pci;
5159 int err;
5160 int is_9652 = 0;
5161 int is_9632 = 0;
5162
5163 hdsp->irq = -1;
5164 hdsp->state = 0;
5165 hdsp->midi[0].rmidi = NULL;
5166 hdsp->midi[1].rmidi = NULL;
5167 hdsp->midi[0].input = NULL;
5168 hdsp->midi[1].input = NULL;
5169 hdsp->midi[0].output = NULL;
5170 hdsp->midi[1].output = NULL;
5171 hdsp->midi[0].pending = 0;
5172 hdsp->midi[1].pending = 0;
5173 spin_lock_init(&hdsp->midi[0].lock);
5174 spin_lock_init(&hdsp->midi[1].lock);
5175 hdsp->iobase = NULL;
5176 hdsp->control_register = 0;
5177 hdsp->control2_register = 0;
5178 hdsp->io_type = Undefined;
5179 hdsp->max_channels = 26;
5180
5181 hdsp->card = card;
5182
5183 spin_lock_init(&hdsp->lock);
5184
5185 tasklet_setup(&hdsp->midi_tasklet, hdsp_midi_tasklet);
5186
5187 pci_read_config_word(hdsp->pci, PCI_CLASS_REVISION, &hdsp->firmware_rev);
5188 hdsp->firmware_rev &= 0xff;
5189
5190
5191
5192
5193
5194
5195
5196
5197 pci_write_config_byte(hdsp->pci, PCI_LATENCY_TIMER, 0xFF);
5198
5199 strcpy(card->driver, "H-DSP");
5200 strcpy(card->mixername, "Xilinx FPGA");
5201
5202 if (hdsp->firmware_rev < 0xa)
5203 return -ENODEV;
5204 else if (hdsp->firmware_rev < 0x64)
5205 hdsp->card_name = "RME Hammerfall DSP";
5206 else if (hdsp->firmware_rev < 0x96) {
5207 hdsp->card_name = "RME HDSP 9652";
5208 is_9652 = 1;
5209 } else {
5210 hdsp->card_name = "RME HDSP 9632";
5211 hdsp->max_channels = 16;
5212 is_9632 = 1;
5213 }
5214
5215 if ((err = pci_enable_device(pci)) < 0)
5216 return err;
5217
5218 pci_set_master(hdsp->pci);
5219
5220 if ((err = pci_request_regions(pci, "hdsp")) < 0)
5221 return err;
5222 hdsp->port = pci_resource_start(pci, 0);
5223 if ((hdsp->iobase = ioremap(hdsp->port, HDSP_IO_EXTENT)) == NULL) {
5224 dev_err(hdsp->card->dev, "unable to remap region 0x%lx-0x%lx\n",
5225 hdsp->port, hdsp->port + HDSP_IO_EXTENT - 1);
5226 return -EBUSY;
5227 }
5228
5229 if (request_irq(pci->irq, snd_hdsp_interrupt, IRQF_SHARED,
5230 KBUILD_MODNAME, hdsp)) {
5231 dev_err(hdsp->card->dev, "unable to use IRQ %d\n", pci->irq);
5232 return -EBUSY;
5233 }
5234
5235 hdsp->irq = pci->irq;
5236 card->sync_irq = hdsp->irq;
5237 hdsp->precise_ptr = 0;
5238 hdsp->use_midi_tasklet = 1;
5239 hdsp->dds_value = 0;
5240
5241 if ((err = snd_hdsp_initialize_memory(hdsp)) < 0)
5242 return err;
5243
5244 if (!is_9652 && !is_9632) {
5245
5246
5247 err = hdsp_wait_for_iobox(hdsp, 1000, 10);
5248
5249 if (err < 0)
5250 return err;
5251
5252 if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
5253 if ((err = hdsp_request_fw_loader(hdsp)) < 0)
5254
5255
5256
5257
5258 dev_err(hdsp->card->dev,
5259 "couldn't get firmware from userspace. try using hdsploader\n");
5260 else
5261
5262 return 0;
5263
5264 dev_info(hdsp->card->dev,
5265 "card initialization pending : waiting for firmware\n");
5266 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5267 return err;
5268 return 0;
5269 } else {
5270 dev_info(hdsp->card->dev,
5271 "Firmware already present, initializing card.\n");
5272 if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
5273 hdsp->io_type = RPM;
5274 else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
5275 hdsp->io_type = Multiface;
5276 else
5277 hdsp->io_type = Digiface;
5278 }
5279 }
5280
5281 if ((err = snd_hdsp_enable_io(hdsp)) != 0)
5282 return err;
5283
5284 if (is_9652)
5285 hdsp->io_type = H9652;
5286
5287 if (is_9632)
5288 hdsp->io_type = H9632;
5289
5290 if ((err = snd_hdsp_create_hwdep(card, hdsp)) < 0)
5291 return err;
5292
5293 snd_hdsp_initialize_channels(hdsp);
5294 snd_hdsp_initialize_midi_flush(hdsp);
5295
5296 hdsp->state |= HDSP_FirmwareLoaded;
5297
5298 if ((err = snd_hdsp_create_alsa_devices(card, hdsp)) < 0)
5299 return err;
5300
5301 return 0;
5302}
5303
5304static int snd_hdsp_free(struct hdsp *hdsp)
5305{
5306 if (hdsp->port) {
5307
5308 tasklet_kill(&hdsp->midi_tasklet);
5309 hdsp->control_register &= ~(HDSP_Start|HDSP_AudioInterruptEnable|HDSP_Midi0InterruptEnable|HDSP_Midi1InterruptEnable);
5310 hdsp_write (hdsp, HDSP_controlRegister, hdsp->control_register);
5311 }
5312
5313 if (hdsp->irq >= 0)
5314 free_irq(hdsp->irq, (void *)hdsp);
5315
5316 snd_hdsp_free_buffers(hdsp);
5317
5318 release_firmware(hdsp->firmware);
5319 vfree(hdsp->fw_uploaded);
5320 iounmap(hdsp->iobase);
5321
5322 if (hdsp->port)
5323 pci_release_regions(hdsp->pci);
5324
5325 pci_disable_device(hdsp->pci);
5326 return 0;
5327}
5328
5329static void snd_hdsp_card_free(struct snd_card *card)
5330{
5331 struct hdsp *hdsp = card->private_data;
5332
5333 if (hdsp)
5334 snd_hdsp_free(hdsp);
5335}
5336
5337static int snd_hdsp_probe(struct pci_dev *pci,
5338 const struct pci_device_id *pci_id)
5339{
5340 static int dev;
5341 struct hdsp *hdsp;
5342 struct snd_card *card;
5343 int err;
5344
5345 if (dev >= SNDRV_CARDS)
5346 return -ENODEV;
5347 if (!enable[dev]) {
5348 dev++;
5349 return -ENOENT;
5350 }
5351
5352 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
5353 sizeof(struct hdsp), &card);
5354 if (err < 0)
5355 return err;
5356
5357 hdsp = card->private_data;
5358 card->private_free = snd_hdsp_card_free;
5359 hdsp->dev = dev;
5360 hdsp->pci = pci;
5361 err = snd_hdsp_create(card, hdsp);
5362 if (err)
5363 goto free_card;
5364
5365 strcpy(card->shortname, "Hammerfall DSP");
5366 sprintf(card->longname, "%s at 0x%lx, irq %d", hdsp->card_name,
5367 hdsp->port, hdsp->irq);
5368 err = snd_card_register(card);
5369 if (err) {
5370free_card:
5371 snd_card_free(card);
5372 return err;
5373 }
5374 pci_set_drvdata(pci, card);
5375 dev++;
5376 return 0;
5377}
5378
5379static void snd_hdsp_remove(struct pci_dev *pci)
5380{
5381 snd_card_free(pci_get_drvdata(pci));
5382}
5383
5384static struct pci_driver hdsp_driver = {
5385 .name = KBUILD_MODNAME,
5386 .id_table = snd_hdsp_ids,
5387 .probe = snd_hdsp_probe,
5388 .remove = snd_hdsp_remove,
5389};
5390
5391module_pci_driver(hdsp_driver);
5392