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11#include <linux/acpi.h>
12#include <linux/delay.h>
13#include <linux/firmware.h>
14#include <linux/fs.h>
15#include <linux/gpio.h>
16#include <linux/i2c.h>
17#include <linux/init.h>
18#include <linux/module.h>
19#include <linux/moduleparam.h>
20#include <linux/platform_device.h>
21#include <linux/pm.h>
22#include <linux/regmap.h>
23#include <sound/core.h>
24#include <sound/initval.h>
25#include <sound/pcm.h>
26#include <sound/pcm_params.h>
27#include <sound/soc-dapm.h>
28#include <sound/soc.h>
29#include <sound/tlv.h>
30
31#include "rl6231.h"
32#include "rt1015.h"
33
34static const struct reg_default rt1015_reg[] = {
35 { 0x0000, 0x0000 },
36 { 0x0004, 0xa000 },
37 { 0x0006, 0x0003 },
38 { 0x000a, 0x081e },
39 { 0x000c, 0x0006 },
40 { 0x000e, 0x0000 },
41 { 0x0010, 0x0000 },
42 { 0x0012, 0x0000 },
43 { 0x0014, 0x0000 },
44 { 0x0016, 0x0000 },
45 { 0x0018, 0x0000 },
46 { 0x0020, 0x8000 },
47 { 0x0022, 0x8043 },
48 { 0x0076, 0x0000 },
49 { 0x0078, 0x0000 },
50 { 0x007a, 0x0002 },
51 { 0x007c, 0x10ec },
52 { 0x007d, 0x1015 },
53 { 0x00f0, 0x5000 },
54 { 0x00f2, 0x004c },
55 { 0x00f3, 0xecfe },
56 { 0x00f4, 0x0000 },
57 { 0x00f6, 0x0400 },
58 { 0x0100, 0x0028 },
59 { 0x0102, 0xff02 },
60 { 0x0104, 0xa213 },
61 { 0x0106, 0x200c },
62 { 0x010c, 0x0000 },
63 { 0x010e, 0x0058 },
64 { 0x0111, 0x0200 },
65 { 0x0112, 0x0400 },
66 { 0x0114, 0x0022 },
67 { 0x0116, 0x0000 },
68 { 0x0118, 0x0000 },
69 { 0x011a, 0x0123 },
70 { 0x011c, 0x4567 },
71 { 0x0300, 0x203d },
72 { 0x0302, 0x001e },
73 { 0x0311, 0x0000 },
74 { 0x0313, 0x6014 },
75 { 0x0314, 0x00a2 },
76 { 0x031a, 0x00a0 },
77 { 0x031c, 0x001f },
78 { 0x031d, 0xffff },
79 { 0x031e, 0x0000 },
80 { 0x031f, 0x0000 },
81 { 0x0320, 0x0000 },
82 { 0x0321, 0x0000 },
83 { 0x0322, 0xd7df },
84 { 0x0328, 0x10b2 },
85 { 0x0329, 0x0175 },
86 { 0x032a, 0x36ad },
87 { 0x032b, 0x7e55 },
88 { 0x032c, 0x0520 },
89 { 0x032d, 0xaa00 },
90 { 0x032e, 0x570e },
91 { 0x0330, 0xe180 },
92 { 0x0332, 0x0034 },
93 { 0x0334, 0x0001 },
94 { 0x0336, 0x0010 },
95 { 0x0338, 0x0000 },
96 { 0x04fa, 0x0030 },
97 { 0x04fc, 0x35c8 },
98 { 0x04fe, 0x0800 },
99 { 0x0500, 0x0400 },
100 { 0x0502, 0x1000 },
101 { 0x0504, 0x0000 },
102 { 0x0506, 0x04ff },
103 { 0x0508, 0x0010 },
104 { 0x050a, 0x001a },
105 { 0x0519, 0x1c68 },
106 { 0x051a, 0x0ccc },
107 { 0x051b, 0x0666 },
108 { 0x051d, 0x0000 },
109 { 0x051f, 0x0000 },
110 { 0x0536, 0x061c },
111 { 0x0538, 0x0000 },
112 { 0x053a, 0x0000 },
113 { 0x053c, 0x0000 },
114 { 0x053d, 0x0000 },
115 { 0x053e, 0x0000 },
116 { 0x053f, 0x0000 },
117 { 0x0540, 0x0000 },
118 { 0x0541, 0x0000 },
119 { 0x0542, 0x0000 },
120 { 0x0543, 0x0000 },
121 { 0x0544, 0x0000 },
122 { 0x0568, 0x0000 },
123 { 0x056a, 0x0000 },
124 { 0x1000, 0x0040 },
125 { 0x1002, 0x5405 },
126 { 0x1006, 0x5515 },
127 { 0x1007, 0x05f7 },
128 { 0x1009, 0x0b0a },
129 { 0x100a, 0x00ef },
130 { 0x100d, 0x0003 },
131 { 0x1010, 0xa433 },
132 { 0x1020, 0x0000 },
133 { 0x1200, 0x5a01 },
134 { 0x1202, 0x6524 },
135 { 0x1204, 0x1f00 },
136 { 0x1206, 0x0000 },
137 { 0x1208, 0x0000 },
138 { 0x120a, 0x0000 },
139 { 0x120c, 0x0000 },
140 { 0x120e, 0x0000 },
141 { 0x1210, 0x0000 },
142 { 0x1212, 0x0000 },
143 { 0x1300, 0x10a1 },
144 { 0x1302, 0x12ff },
145 { 0x1304, 0x0400 },
146 { 0x1305, 0x0844 },
147 { 0x1306, 0x4611 },
148 { 0x1308, 0x555e },
149 { 0x130a, 0x0000 },
150 { 0x130c, 0x2000 },
151 { 0x130e, 0x0100 },
152 { 0x130f, 0x0001 },
153 { 0x1310, 0x0000 },
154 { 0x1312, 0x0000 },
155 { 0x1314, 0x0000 },
156 { 0x1316, 0x0000 },
157 { 0x1318, 0x0000 },
158 { 0x131a, 0x0000 },
159 { 0x1322, 0x0029 },
160 { 0x1323, 0x4a52 },
161 { 0x1324, 0x002c },
162 { 0x1325, 0x0b02 },
163 { 0x1326, 0x002d },
164 { 0x1327, 0x6b5a },
165 { 0x1328, 0x002e },
166 { 0x1329, 0xcbb2 },
167 { 0x132a, 0x0030 },
168 { 0x132b, 0x2c0b },
169 { 0x1330, 0x0031 },
170 { 0x1331, 0x8c63 },
171 { 0x1332, 0x0032 },
172 { 0x1333, 0xecbb },
173 { 0x1334, 0x0034 },
174 { 0x1335, 0x4d13 },
175 { 0x1336, 0x0037 },
176 { 0x1337, 0x0dc3 },
177 { 0x1338, 0x003d },
178 { 0x1339, 0xef7b },
179 { 0x133a, 0x0044 },
180 { 0x133b, 0xd134 },
181 { 0x133c, 0x0047 },
182 { 0x133d, 0x91e4 },
183 { 0x133e, 0x004d },
184 { 0x133f, 0xc370 },
185 { 0x1340, 0x0053 },
186 { 0x1341, 0xf4fd },
187 { 0x1342, 0x0060 },
188 { 0x1343, 0x5816 },
189 { 0x1344, 0x006c },
190 { 0x1345, 0xbb2e },
191 { 0x1346, 0x0072 },
192 { 0x1347, 0xecbb },
193 { 0x1348, 0x0076 },
194 { 0x1349, 0x5d97 },
195};
196
197static bool rt1015_volatile_register(struct device *dev, unsigned int reg)
198{
199 switch (reg) {
200 case RT1015_RESET:
201 case RT1015_CLK_DET:
202 case RT1015_SIL_DET:
203 case RT1015_VER_ID:
204 case RT1015_VENDOR_ID:
205 case RT1015_DEVICE_ID:
206 case RT1015_PRO_ALT:
207 case RT1015_DAC3:
208 case RT1015_VBAT_TEST_OUT1:
209 case RT1015_VBAT_TEST_OUT2:
210 case RT1015_VBAT_PROT_ATT:
211 case RT1015_VBAT_DET_CODE:
212 case RT1015_SMART_BST_CTRL1:
213 case RT1015_SPK_DC_DETECT1:
214 case RT1015_SPK_DC_DETECT4:
215 case RT1015_SPK_DC_DETECT5:
216 case RT1015_DC_CALIB_CLSD1:
217 case RT1015_DC_CALIB_CLSD5:
218 case RT1015_DC_CALIB_CLSD6:
219 case RT1015_DC_CALIB_CLSD7:
220 case RT1015_DC_CALIB_CLSD8:
221 case RT1015_S_BST_TIMING_INTER1:
222 case RT1015_OSCK_STA:
223 case RT1015_MONO_DYNA_CTRL1:
224 case RT1015_MONO_DYNA_CTRL5:
225 return true;
226
227 default:
228 return false;
229 }
230}
231
232static bool rt1015_readable_register(struct device *dev, unsigned int reg)
233{
234 switch (reg) {
235 case RT1015_RESET:
236 case RT1015_CLK2:
237 case RT1015_CLK3:
238 case RT1015_PLL1:
239 case RT1015_PLL2:
240 case RT1015_DUM_RW1:
241 case RT1015_DUM_RW2:
242 case RT1015_DUM_RW3:
243 case RT1015_DUM_RW4:
244 case RT1015_DUM_RW5:
245 case RT1015_DUM_RW6:
246 case RT1015_CLK_DET:
247 case RT1015_SIL_DET:
248 case RT1015_CUSTOMER_ID:
249 case RT1015_PCODE_FWVER:
250 case RT1015_VER_ID:
251 case RT1015_VENDOR_ID:
252 case RT1015_DEVICE_ID:
253 case RT1015_PAD_DRV1:
254 case RT1015_PAD_DRV2:
255 case RT1015_GAT_BOOST:
256 case RT1015_PRO_ALT:
257 case RT1015_OSCK_STA:
258 case RT1015_MAN_I2C:
259 case RT1015_DAC1:
260 case RT1015_DAC2:
261 case RT1015_DAC3:
262 case RT1015_ADC1:
263 case RT1015_ADC2:
264 case RT1015_TDM_MASTER:
265 case RT1015_TDM_TCON:
266 case RT1015_TDM1_1:
267 case RT1015_TDM1_2:
268 case RT1015_TDM1_3:
269 case RT1015_TDM1_4:
270 case RT1015_TDM1_5:
271 case RT1015_MIXER1:
272 case RT1015_MIXER2:
273 case RT1015_ANA_PROTECT1:
274 case RT1015_ANA_CTRL_SEQ1:
275 case RT1015_ANA_CTRL_SEQ2:
276 case RT1015_VBAT_DET_DEB:
277 case RT1015_VBAT_VOLT_DET1:
278 case RT1015_VBAT_VOLT_DET2:
279 case RT1015_VBAT_TEST_OUT1:
280 case RT1015_VBAT_TEST_OUT2:
281 case RT1015_VBAT_PROT_ATT:
282 case RT1015_VBAT_DET_CODE:
283 case RT1015_PWR1:
284 case RT1015_PWR4:
285 case RT1015_PWR5:
286 case RT1015_PWR6:
287 case RT1015_PWR7:
288 case RT1015_PWR8:
289 case RT1015_PWR9:
290 case RT1015_CLASSD_SEQ:
291 case RT1015_SMART_BST_CTRL1:
292 case RT1015_SMART_BST_CTRL2:
293 case RT1015_ANA_CTRL1:
294 case RT1015_ANA_CTRL2:
295 case RT1015_PWR_STATE_CTRL:
296 case RT1015_MONO_DYNA_CTRL:
297 case RT1015_MONO_DYNA_CTRL1:
298 case RT1015_MONO_DYNA_CTRL2:
299 case RT1015_MONO_DYNA_CTRL3:
300 case RT1015_MONO_DYNA_CTRL4:
301 case RT1015_MONO_DYNA_CTRL5:
302 case RT1015_SPK_VOL:
303 case RT1015_SHORT_DETTOP1:
304 case RT1015_SHORT_DETTOP2:
305 case RT1015_SPK_DC_DETECT1:
306 case RT1015_SPK_DC_DETECT2:
307 case RT1015_SPK_DC_DETECT3:
308 case RT1015_SPK_DC_DETECT4:
309 case RT1015_SPK_DC_DETECT5:
310 case RT1015_BAT_RPO_STEP1:
311 case RT1015_BAT_RPO_STEP2:
312 case RT1015_BAT_RPO_STEP3:
313 case RT1015_BAT_RPO_STEP4:
314 case RT1015_BAT_RPO_STEP5:
315 case RT1015_BAT_RPO_STEP6:
316 case RT1015_BAT_RPO_STEP7:
317 case RT1015_BAT_RPO_STEP8:
318 case RT1015_BAT_RPO_STEP9:
319 case RT1015_BAT_RPO_STEP10:
320 case RT1015_BAT_RPO_STEP11:
321 case RT1015_BAT_RPO_STEP12:
322 case RT1015_SPREAD_SPEC1:
323 case RT1015_SPREAD_SPEC2:
324 case RT1015_PAD_STATUS:
325 case RT1015_PADS_PULLING_CTRL1:
326 case RT1015_PADS_DRIVING:
327 case RT1015_SYS_RST1:
328 case RT1015_SYS_RST2:
329 case RT1015_SYS_GATING1:
330 case RT1015_TEST_MODE1:
331 case RT1015_TEST_MODE2:
332 case RT1015_TIMING_CTRL1:
333 case RT1015_PLL_INT:
334 case RT1015_TEST_OUT1:
335 case RT1015_DC_CALIB_CLSD1:
336 case RT1015_DC_CALIB_CLSD2:
337 case RT1015_DC_CALIB_CLSD3:
338 case RT1015_DC_CALIB_CLSD4:
339 case RT1015_DC_CALIB_CLSD5:
340 case RT1015_DC_CALIB_CLSD6:
341 case RT1015_DC_CALIB_CLSD7:
342 case RT1015_DC_CALIB_CLSD8:
343 case RT1015_DC_CALIB_CLSD9:
344 case RT1015_DC_CALIB_CLSD10:
345 case RT1015_CLSD_INTERNAL1:
346 case RT1015_CLSD_INTERNAL2:
347 case RT1015_CLSD_INTERNAL3:
348 case RT1015_CLSD_INTERNAL4:
349 case RT1015_CLSD_INTERNAL5:
350 case RT1015_CLSD_INTERNAL6:
351 case RT1015_CLSD_INTERNAL7:
352 case RT1015_CLSD_INTERNAL8:
353 case RT1015_CLSD_INTERNAL9:
354 case RT1015_CLSD_OCP_CTRL:
355 case RT1015_VREF_LV:
356 case RT1015_MBIAS1:
357 case RT1015_MBIAS2:
358 case RT1015_MBIAS3:
359 case RT1015_MBIAS4:
360 case RT1015_VREF_LV1:
361 case RT1015_S_BST_TIMING_INTER1:
362 case RT1015_S_BST_TIMING_INTER2:
363 case RT1015_S_BST_TIMING_INTER3:
364 case RT1015_S_BST_TIMING_INTER4:
365 case RT1015_S_BST_TIMING_INTER5:
366 case RT1015_S_BST_TIMING_INTER6:
367 case RT1015_S_BST_TIMING_INTER7:
368 case RT1015_S_BST_TIMING_INTER8:
369 case RT1015_S_BST_TIMING_INTER9:
370 case RT1015_S_BST_TIMING_INTER10:
371 case RT1015_S_BST_TIMING_INTER11:
372 case RT1015_S_BST_TIMING_INTER12:
373 case RT1015_S_BST_TIMING_INTER13:
374 case RT1015_S_BST_TIMING_INTER14:
375 case RT1015_S_BST_TIMING_INTER15:
376 case RT1015_S_BST_TIMING_INTER16:
377 case RT1015_S_BST_TIMING_INTER17:
378 case RT1015_S_BST_TIMING_INTER18:
379 case RT1015_S_BST_TIMING_INTER19:
380 case RT1015_S_BST_TIMING_INTER20:
381 case RT1015_S_BST_TIMING_INTER21:
382 case RT1015_S_BST_TIMING_INTER22:
383 case RT1015_S_BST_TIMING_INTER23:
384 case RT1015_S_BST_TIMING_INTER24:
385 case RT1015_S_BST_TIMING_INTER25:
386 case RT1015_S_BST_TIMING_INTER26:
387 case RT1015_S_BST_TIMING_INTER27:
388 case RT1015_S_BST_TIMING_INTER28:
389 case RT1015_S_BST_TIMING_INTER29:
390 case RT1015_S_BST_TIMING_INTER30:
391 case RT1015_S_BST_TIMING_INTER31:
392 case RT1015_S_BST_TIMING_INTER32:
393 case RT1015_S_BST_TIMING_INTER33:
394 case RT1015_S_BST_TIMING_INTER34:
395 case RT1015_S_BST_TIMING_INTER35:
396 case RT1015_S_BST_TIMING_INTER36:
397 return true;
398
399 default:
400 return false;
401 }
402}
403
404static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -9525, 75, 0);
405
406static const char * const rt1015_din_source_select[] = {
407 "Left",
408 "Right",
409 "Left + Right average",
410};
411
412static SOC_ENUM_SINGLE_DECL(rt1015_mono_lr_sel, RT1015_PAD_DRV2, 4,
413 rt1015_din_source_select);
414
415static const char * const rt1015_boost_mode[] = {
416 "Bypass", "Adaptive", "Fixed Adaptive"
417};
418
419static SOC_ENUM_SINGLE_DECL(rt1015_boost_mode_enum, 0, 0,
420 rt1015_boost_mode);
421
422static int rt1015_boost_mode_get(struct snd_kcontrol *kcontrol,
423 struct snd_ctl_elem_value *ucontrol)
424{
425 struct snd_soc_component *component =
426 snd_soc_kcontrol_component(kcontrol);
427 struct rt1015_priv *rt1015 =
428 snd_soc_component_get_drvdata(component);
429
430 ucontrol->value.integer.value[0] = rt1015->boost_mode;
431
432 return 0;
433}
434
435static int rt1015_boost_mode_put(struct snd_kcontrol *kcontrol,
436 struct snd_ctl_elem_value *ucontrol)
437{
438 struct snd_soc_component *component =
439 snd_soc_kcontrol_component(kcontrol);
440 struct rt1015_priv *rt1015 =
441 snd_soc_component_get_drvdata(component);
442
443 rt1015->boost_mode = ucontrol->value.integer.value[0];
444
445 switch (rt1015->boost_mode) {
446 case BYPASS:
447 snd_soc_component_update_bits(component,
448 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
449 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
450 RT1015_ABST_REG_MODE | RT1015_ABST_FIX_TGT_DIS |
451 RT1015_BYPASS_SWRREG_BYPASS);
452 break;
453 case ADAPTIVE:
454 snd_soc_component_update_bits(component,
455 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
456 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
457 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_DIS |
458 RT1015_BYPASS_SWRREG_PASS);
459 break;
460 case FIXED_ADAPTIVE:
461 snd_soc_component_update_bits(component,
462 RT1015_SMART_BST_CTRL1, RT1015_ABST_AUTO_EN_MASK |
463 RT1015_ABST_FIX_TGT_MASK | RT1015_BYPASS_SWR_REG_MASK,
464 RT1015_ABST_AUTO_MODE | RT1015_ABST_FIX_TGT_EN |
465 RT1015_BYPASS_SWRREG_PASS);
466 break;
467 default:
468 dev_err(component->dev, "Unknown boost control.\n");
469 }
470
471 return 0;
472}
473
474static int rt1015_bypass_boost_get(struct snd_kcontrol *kcontrol,
475 struct snd_ctl_elem_value *ucontrol)
476{
477 struct snd_soc_component *component =
478 snd_soc_kcontrol_component(kcontrol);
479 struct rt1015_priv *rt1015 =
480 snd_soc_component_get_drvdata(component);
481
482 ucontrol->value.integer.value[0] = rt1015->bypass_boost;
483
484 return 0;
485}
486
487static int rt1015_bypass_boost_put(struct snd_kcontrol *kcontrol,
488 struct snd_ctl_elem_value *ucontrol)
489{
490 struct snd_soc_component *component =
491 snd_soc_kcontrol_component(kcontrol);
492 struct rt1015_priv *rt1015 =
493 snd_soc_component_get_drvdata(component);
494
495 if (!rt1015->dac_is_used) {
496 rt1015->bypass_boost = ucontrol->value.integer.value[0];
497 if (rt1015->bypass_boost == RT1015_Bypass_Boost) {
498 snd_soc_component_write(component,
499 RT1015_PWR4, 0x00b2);
500 snd_soc_component_write(component,
501 RT1015_CLSD_INTERNAL8, 0x2008);
502 snd_soc_component_write(component,
503 RT1015_CLSD_INTERNAL9, 0x0140);
504 snd_soc_component_write(component,
505 RT1015_GAT_BOOST, 0x0efe);
506 snd_soc_component_write(component,
507 RT1015_PWR_STATE_CTRL, 0x000d);
508 msleep(500);
509 snd_soc_component_write(component,
510 RT1015_PWR_STATE_CTRL, 0x000e);
511 }
512 } else
513 dev_err(component->dev, "DAC is being used!\n");
514
515 return 0;
516}
517
518static const struct snd_kcontrol_new rt1015_snd_controls[] = {
519 SOC_SINGLE_TLV("DAC Playback Volume", RT1015_DAC1, RT1015_DAC_VOL_SFT,
520 127, 0, dac_vol_tlv),
521 SOC_DOUBLE("DAC Playback Switch", RT1015_DAC3,
522 RT1015_DA_MUTE_SFT, RT1015_DVOL_MUTE_FLAG_SFT, 1, 1),
523 SOC_ENUM_EXT("Boost Mode", rt1015_boost_mode_enum,
524 rt1015_boost_mode_get, rt1015_boost_mode_put),
525 SOC_ENUM("Mono LR Select", rt1015_mono_lr_sel),
526 SOC_SINGLE_EXT("Bypass Boost", SND_SOC_NOPM, 0, 1, 0,
527 rt1015_bypass_boost_get, rt1015_bypass_boost_put),
528};
529
530static int rt1015_is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
531 struct snd_soc_dapm_widget *sink)
532{
533 struct snd_soc_component *component =
534 snd_soc_dapm_to_component(source->dapm);
535 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
536
537 if (rt1015->sysclk_src == RT1015_SCLK_S_PLL)
538 return 1;
539 else
540 return 0;
541}
542
543static int r1015_dac_event(struct snd_soc_dapm_widget *w,
544 struct snd_kcontrol *kcontrol, int event)
545{
546 struct snd_soc_component *component =
547 snd_soc_dapm_to_component(w->dapm);
548 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
549
550 switch (event) {
551 case SND_SOC_DAPM_PRE_PMU:
552 rt1015->dac_is_used = 1;
553 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
554 snd_soc_component_write(component,
555 RT1015_SYS_RST1, 0x05f7);
556 snd_soc_component_write(component,
557 RT1015_GAT_BOOST, 0xacfe);
558 snd_soc_component_write(component,
559 RT1015_PWR9, 0xaa00);
560 snd_soc_component_write(component,
561 RT1015_GAT_BOOST, 0xecfe);
562 } else {
563 snd_soc_component_write(component,
564 RT1015_SYS_RST1, 0x05f7);
565 snd_soc_component_write(component,
566 RT1015_PWR_STATE_CTRL, 0x026e);
567 }
568 break;
569
570 case SND_SOC_DAPM_POST_PMU:
571 if (rt1015->bypass_boost == RT1015_Bypass_Boost) {
572 regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x00a8);
573 regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x0597);
574 regmap_write(rt1015->regmap, RT1015_SYS_RST1, 0x05f7);
575 regmap_write(rt1015->regmap, RT1015_MAN_I2C, 0x0028);
576 }
577 break;
578
579 case SND_SOC_DAPM_POST_PMD:
580 if (rt1015->bypass_boost == RT1015_Enable_Boost) {
581 snd_soc_component_write(component,
582 RT1015_PWR9, 0xa800);
583 snd_soc_component_write(component,
584 RT1015_SYS_RST1, 0x05f5);
585 } else {
586 snd_soc_component_write(component,
587 RT1015_PWR_STATE_CTRL, 0x0268);
588 snd_soc_component_write(component,
589 RT1015_SYS_RST1, 0x05f5);
590 }
591 rt1015->dac_is_used = 0;
592 break;
593
594 default:
595 break;
596 }
597 return 0;
598}
599
600static const struct snd_soc_dapm_widget rt1015_dapm_widgets[] = {
601 SND_SOC_DAPM_SUPPLY("LDO2", RT1015_PWR1, RT1015_PWR_LDO2_BIT, 0,
602 NULL, 0),
603 SND_SOC_DAPM_SUPPLY("INT RC CLK", RT1015_PWR1, RT1015_PWR_INTCLK_BIT,
604 0, NULL, 0),
605 SND_SOC_DAPM_SUPPLY("ISENSE", RT1015_PWR1, RT1015_PWR_ISENSE_BIT, 0,
606 NULL, 0),
607 SND_SOC_DAPM_SUPPLY("VSENSE", RT1015_PWR1, RT1015_PWR_VSENSE_BIT, 0,
608 NULL, 0),
609 SND_SOC_DAPM_SUPPLY("PLL", RT1015_PWR1, RT1015_PWR_PLL_BIT, 0,
610 NULL, 0),
611 SND_SOC_DAPM_SUPPLY("BG1 BG2", RT1015_PWR1, RT1015_PWR_BG_1_2_BIT, 0,
612 NULL, 0),
613 SND_SOC_DAPM_SUPPLY("MBIAS BG", RT1015_PWR1, RT1015_PWR_MBIAS_BG_BIT, 0,
614 NULL, 0),
615 SND_SOC_DAPM_SUPPLY("VBAT", RT1015_PWR1, RT1015_PWR_VBAT_BIT, 0, NULL,
616 0),
617 SND_SOC_DAPM_SUPPLY("MBIAS", RT1015_PWR1, RT1015_PWR_MBIAS_BIT, 0,
618 NULL, 0),
619 SND_SOC_DAPM_SUPPLY("ADCV", RT1015_PWR1, RT1015_PWR_ADCV_BIT, 0, NULL,
620 0),
621 SND_SOC_DAPM_SUPPLY("MIXERV", RT1015_PWR1, RT1015_PWR_MIXERV_BIT, 0,
622 NULL, 0),
623 SND_SOC_DAPM_SUPPLY("SUMV", RT1015_PWR1, RT1015_PWR_SUMV_BIT, 0, NULL,
624 0),
625 SND_SOC_DAPM_SUPPLY("VREFLV", RT1015_PWR1, RT1015_PWR_VREFLV_BIT, 0,
626 NULL, 0),
627
628 SND_SOC_DAPM_AIF_IN("AIFRX", "AIF Playback", 0, SND_SOC_NOPM, 0, 0),
629 SND_SOC_DAPM_DAC_E("DAC", NULL, RT1015_PWR1, RT1015_PWR_DAC_BIT, 0,
630 r1015_dac_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
631 SND_SOC_DAPM_POST_PMD),
632
633 SND_SOC_DAPM_OUTPUT("SPO"),
634};
635
636static const struct snd_soc_dapm_route rt1015_dapm_routes[] = {
637 { "DAC", NULL, "AIFRX" },
638 { "DAC", NULL, "LDO2" },
639 { "DAC", NULL, "PLL", rt1015_is_sys_clk_from_pll},
640 { "DAC", NULL, "INT RC CLK" },
641 { "DAC", NULL, "ISENSE" },
642 { "DAC", NULL, "VSENSE" },
643 { "DAC", NULL, "BG1 BG2" },
644 { "DAC", NULL, "MBIAS BG" },
645 { "DAC", NULL, "VBAT" },
646 { "DAC", NULL, "MBIAS" },
647 { "DAC", NULL, "ADCV" },
648 { "DAC", NULL, "MIXERV" },
649 { "DAC", NULL, "SUMV" },
650 { "DAC", NULL, "VREFLV" },
651 { "SPO", NULL, "DAC" },
652};
653
654static int rt1015_hw_params(struct snd_pcm_substream *substream,
655 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
656{
657 struct snd_soc_component *component = dai->component;
658 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
659 int pre_div, bclk_ms, frame_size;
660 unsigned int val_len = 0;
661
662 rt1015->lrck = params_rate(params);
663 pre_div = rl6231_get_clk_info(rt1015->sysclk, rt1015->lrck);
664 if (pre_div < 0) {
665 dev_err(component->dev, "Unsupported clock rate\n");
666 return -EINVAL;
667 }
668
669 frame_size = snd_soc_params_to_frame_size(params);
670 if (frame_size < 0) {
671 dev_err(component->dev, "Unsupported frame size: %d\n",
672 frame_size);
673 return -EINVAL;
674 }
675
676 bclk_ms = frame_size > 32;
677 rt1015->bclk = rt1015->lrck * (32 << bclk_ms);
678
679 dev_dbg(component->dev, "bclk_ms is %d and pre_div is %d for iis %d\n",
680 bclk_ms, pre_div, dai->id);
681
682 dev_dbg(component->dev, "lrck is %dHz and pre_div is %d for iis %d\n",
683 rt1015->lrck, pre_div, dai->id);
684
685 switch (params_width(params)) {
686 case 16:
687 break;
688 case 20:
689 val_len = RT1015_I2S_DL_20;
690 break;
691 case 24:
692 val_len = RT1015_I2S_DL_24;
693 break;
694 case 8:
695 val_len = RT1015_I2S_DL_8;
696 break;
697 default:
698 return -EINVAL;
699 }
700
701 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
702 RT1015_I2S_DL_MASK, val_len);
703 snd_soc_component_update_bits(component, RT1015_CLK2,
704 RT1015_FS_PD_MASK, pre_div << RT1015_FS_PD_SFT);
705
706 return 0;
707}
708
709static int rt1015_set_dai_fmt(struct snd_soc_dai *dai, unsigned int fmt)
710{
711 struct snd_soc_component *component = dai->component;
712 unsigned int reg_val = 0, reg_val2 = 0;
713
714 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
715 case SND_SOC_DAIFMT_CBM_CFM:
716 reg_val |= RT1015_TCON_TDM_MS_M;
717 break;
718 case SND_SOC_DAIFMT_CBS_CFS:
719 reg_val |= RT1015_TCON_TDM_MS_S;
720 break;
721 default:
722 return -EINVAL;
723 }
724
725 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
726 case SND_SOC_DAIFMT_NB_NF:
727 break;
728 case SND_SOC_DAIFMT_IB_NF:
729 reg_val2 |= RT1015_TDM_INV_BCLK;
730 break;
731 default:
732 return -EINVAL;
733 }
734
735 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
736 case SND_SOC_DAIFMT_I2S:
737 break;
738
739 case SND_SOC_DAIFMT_LEFT_J:
740 reg_val |= RT1015_I2S_M_DF_LEFT;
741 break;
742
743 case SND_SOC_DAIFMT_DSP_A:
744 reg_val |= RT1015_I2S_M_DF_PCM_A;
745 break;
746
747 case SND_SOC_DAIFMT_DSP_B:
748 reg_val |= RT1015_I2S_M_DF_PCM_B;
749 break;
750
751 default:
752 return -EINVAL;
753 }
754
755 snd_soc_component_update_bits(component, RT1015_TDM_MASTER,
756 RT1015_TCON_TDM_MS_MASK | RT1015_I2S_M_DF_MASK,
757 reg_val);
758 snd_soc_component_update_bits(component, RT1015_TDM1_1,
759 RT1015_TDM_INV_BCLK_MASK, reg_val2);
760
761 return 0;
762}
763
764static int rt1015_set_component_sysclk(struct snd_soc_component *component,
765 int clk_id, int source, unsigned int freq, int dir)
766{
767 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
768 unsigned int reg_val = 0;
769
770 if (freq == rt1015->sysclk && clk_id == rt1015->sysclk_src)
771 return 0;
772
773 switch (clk_id) {
774 case RT1015_SCLK_S_MCLK:
775 reg_val |= RT1015_CLK_SYS_PRE_SEL_MCLK;
776 break;
777
778 case RT1015_SCLK_S_PLL:
779 reg_val |= RT1015_CLK_SYS_PRE_SEL_PLL;
780 break;
781
782 default:
783 dev_err(component->dev, "Invalid clock id (%d)\n", clk_id);
784 return -EINVAL;
785 }
786
787 rt1015->sysclk = freq;
788 rt1015->sysclk_src = clk_id;
789
790 dev_dbg(component->dev, "Sysclk is %dHz and clock id is %d\n",
791 freq, clk_id);
792
793 snd_soc_component_update_bits(component, RT1015_CLK2,
794 RT1015_CLK_SYS_PRE_SEL_MASK, reg_val);
795
796 return 0;
797}
798
799static int rt1015_set_component_pll(struct snd_soc_component *component,
800 int pll_id, int source, unsigned int freq_in,
801 unsigned int freq_out)
802{
803 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
804 struct rl6231_pll_code pll_code;
805 int ret;
806
807 if (!freq_in || !freq_out) {
808 dev_dbg(component->dev, "PLL disabled\n");
809
810 rt1015->pll_in = 0;
811 rt1015->pll_out = 0;
812
813 return 0;
814 }
815
816 if (source == rt1015->pll_src && freq_in == rt1015->pll_in &&
817 freq_out == rt1015->pll_out)
818 return 0;
819
820 if (source == RT1015_PLL_S_BCLK) {
821 if (rt1015->bclk_ratio == 0) {
822 dev_err(component->dev,
823 "Can not support bclk ratio as 0.\n");
824 return -EINVAL;
825 }
826 }
827
828 switch (source) {
829 case RT1015_PLL_S_MCLK:
830 snd_soc_component_update_bits(component, RT1015_CLK2,
831 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_PLL_SRC2);
832 break;
833
834 case RT1015_PLL_S_BCLK:
835 snd_soc_component_update_bits(component, RT1015_CLK2,
836 RT1015_PLL_SEL_MASK, RT1015_PLL_SEL_BCLK);
837 break;
838
839 default:
840 dev_err(component->dev, "Unknown PLL Source %d\n", source);
841 return -EINVAL;
842 }
843
844 ret = rl6231_pll_calc(freq_in, freq_out, &pll_code);
845 if (ret < 0) {
846 dev_err(component->dev, "Unsupport input clock %d\n", freq_in);
847 return ret;
848 }
849
850 dev_dbg(component->dev, "bypass=%d m=%d n=%d k=%d\n",
851 pll_code.m_bp, (pll_code.m_bp ? 0 : pll_code.m_code),
852 pll_code.n_code, pll_code.k_code);
853
854 snd_soc_component_write(component, RT1015_PLL1,
855 (pll_code.m_bp ? 0 : pll_code.m_code) << RT1015_PLL_M_SFT |
856 pll_code.m_bp << RT1015_PLL_M_BP_SFT | pll_code.n_code);
857 snd_soc_component_write(component, RT1015_PLL2,
858 pll_code.k_code);
859
860 rt1015->pll_in = freq_in;
861 rt1015->pll_out = freq_out;
862 rt1015->pll_src = source;
863
864 return 0;
865}
866
867static int rt1015_set_bclk_ratio(struct snd_soc_dai *dai, unsigned int ratio)
868{
869 struct snd_soc_component *component = dai->component;
870 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
871
872 dev_dbg(component->dev, "%s ratio=%d\n", __func__, ratio);
873
874 rt1015->bclk_ratio = ratio;
875
876 if (ratio == 50) {
877 dev_dbg(component->dev, "Unsupport bclk ratio\n");
878 return -EINVAL;
879 }
880
881 return 0;
882}
883
884static int rt1015_probe(struct snd_soc_component *component)
885{
886 struct rt1015_priv *rt1015 =
887 snd_soc_component_get_drvdata(component);
888
889 rt1015->component = component;
890 rt1015->bclk_ratio = 0;
891 snd_soc_component_write(component, RT1015_BAT_RPO_STEP1, 0x061c);
892
893 return 0;
894}
895
896static void rt1015_remove(struct snd_soc_component *component)
897{
898 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
899
900 regmap_write(rt1015->regmap, RT1015_RESET, 0);
901}
902
903#define RT1015_STEREO_RATES SNDRV_PCM_RATE_8000_192000
904#define RT1015_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
905 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S8)
906
907static struct snd_soc_dai_ops rt1015_aif_dai_ops = {
908 .hw_params = rt1015_hw_params,
909 .set_fmt = rt1015_set_dai_fmt,
910 .set_bclk_ratio = rt1015_set_bclk_ratio,
911};
912
913static struct snd_soc_dai_driver rt1015_dai[] = {
914 {
915 .name = "rt1015-aif",
916 .id = 0,
917 .playback = {
918 .stream_name = "AIF Playback",
919 .channels_min = 1,
920 .channels_max = 4,
921 .rates = RT1015_STEREO_RATES,
922 .formats = RT1015_FORMATS,
923 },
924 .ops = &rt1015_aif_dai_ops,
925 }
926};
927
928#ifdef CONFIG_PM
929static int rt1015_suspend(struct snd_soc_component *component)
930{
931 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
932
933 regcache_cache_only(rt1015->regmap, true);
934 regcache_mark_dirty(rt1015->regmap);
935
936 return 0;
937}
938
939static int rt1015_resume(struct snd_soc_component *component)
940{
941 struct rt1015_priv *rt1015 = snd_soc_component_get_drvdata(component);
942
943 regcache_cache_only(rt1015->regmap, false);
944 regcache_sync(rt1015->regmap);
945 return 0;
946}
947#else
948#define rt1015_suspend NULL
949#define rt1015_resume NULL
950#endif
951
952static const struct snd_soc_component_driver soc_component_dev_rt1015 = {
953 .probe = rt1015_probe,
954 .remove = rt1015_remove,
955 .suspend = rt1015_suspend,
956 .resume = rt1015_resume,
957 .controls = rt1015_snd_controls,
958 .num_controls = ARRAY_SIZE(rt1015_snd_controls),
959 .dapm_widgets = rt1015_dapm_widgets,
960 .num_dapm_widgets = ARRAY_SIZE(rt1015_dapm_widgets),
961 .dapm_routes = rt1015_dapm_routes,
962 .num_dapm_routes = ARRAY_SIZE(rt1015_dapm_routes),
963 .set_sysclk = rt1015_set_component_sysclk,
964 .set_pll = rt1015_set_component_pll,
965 .use_pmdown_time = 1,
966 .endianness = 1,
967 .non_legacy_dai_naming = 1,
968};
969
970static const struct regmap_config rt1015_regmap = {
971 .reg_bits = 16,
972 .val_bits = 16,
973 .max_register = RT1015_S_BST_TIMING_INTER36,
974 .volatile_reg = rt1015_volatile_register,
975 .readable_reg = rt1015_readable_register,
976 .cache_type = REGCACHE_RBTREE,
977 .reg_defaults = rt1015_reg,
978 .num_reg_defaults = ARRAY_SIZE(rt1015_reg),
979};
980
981static const struct i2c_device_id rt1015_i2c_id[] = {
982 { "rt1015", 0 },
983 { }
984};
985MODULE_DEVICE_TABLE(i2c, rt1015_i2c_id);
986
987#if defined(CONFIG_OF)
988static const struct of_device_id rt1015_of_match[] = {
989 { .compatible = "realtek,rt1015", },
990 {},
991};
992MODULE_DEVICE_TABLE(of, rt1015_of_match);
993#endif
994
995#ifdef CONFIG_ACPI
996static struct acpi_device_id rt1015_acpi_match[] = {
997 {"10EC1015", 0,},
998 {},
999};
1000MODULE_DEVICE_TABLE(acpi, rt1015_acpi_match);
1001#endif
1002
1003static int rt1015_i2c_probe(struct i2c_client *i2c,
1004 const struct i2c_device_id *id)
1005{
1006 struct rt1015_priv *rt1015;
1007 int ret;
1008 unsigned int val;
1009
1010 rt1015 = devm_kzalloc(&i2c->dev, sizeof(struct rt1015_priv),
1011 GFP_KERNEL);
1012 if (rt1015 == NULL)
1013 return -ENOMEM;
1014
1015 i2c_set_clientdata(i2c, rt1015);
1016
1017 rt1015->regmap = devm_regmap_init_i2c(i2c, &rt1015_regmap);
1018 if (IS_ERR(rt1015->regmap)) {
1019 ret = PTR_ERR(rt1015->regmap);
1020 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1021 ret);
1022 return ret;
1023 }
1024
1025 regmap_read(rt1015->regmap, RT1015_DEVICE_ID, &val);
1026 if ((val != RT1015_DEVICE_ID_VAL) && (val != RT1015_DEVICE_ID_VAL2)) {
1027 dev_err(&i2c->dev,
1028 "Device with ID register %x is not rt1015\n", val);
1029 return -ENODEV;
1030 }
1031
1032 return devm_snd_soc_register_component(&i2c->dev,
1033 &soc_component_dev_rt1015,
1034 rt1015_dai, ARRAY_SIZE(rt1015_dai));
1035}
1036
1037static void rt1015_i2c_shutdown(struct i2c_client *client)
1038{
1039 struct rt1015_priv *rt1015 = i2c_get_clientdata(client);
1040
1041 regmap_write(rt1015->regmap, RT1015_RESET, 0);
1042}
1043
1044static struct i2c_driver rt1015_i2c_driver = {
1045 .driver = {
1046 .name = "rt1015",
1047 .of_match_table = of_match_ptr(rt1015_of_match),
1048 .acpi_match_table = ACPI_PTR(rt1015_acpi_match),
1049 },
1050 .probe = rt1015_i2c_probe,
1051 .shutdown = rt1015_i2c_shutdown,
1052 .id_table = rt1015_i2c_id,
1053};
1054module_i2c_driver(rt1015_i2c_driver);
1055
1056MODULE_DESCRIPTION("ASoC RT1015 driver");
1057MODULE_AUTHOR("Jack Yu <jack.yu@realtek.com>");
1058MODULE_LICENSE("GPL v2");
1059
