1
2
3
4
5#include <linux/module.h>
6#include <linux/moduleparam.h>
7#include <linux/init.h>
8#include <linux/delay.h>
9#include <linux/pm.h>
10#include <linux/i2c.h>
11#include <linux/gpio/consumer.h>
12#include <linux/regulator/consumer.h>
13#include <linux/acpi.h>
14#include <linux/of.h>
15#include <linux/of_gpio.h>
16#include <linux/slab.h>
17#include <sound/core.h>
18#include <sound/pcm.h>
19#include <sound/pcm_params.h>
20#include <sound/soc.h>
21#include <sound/initval.h>
22#include <sound/tlv.h>
23
24#include "tlv320adcx140.h"
25
26struct adcx140_priv {
27 struct snd_soc_component *component;
28 struct regulator *supply_areg;
29 struct gpio_desc *gpio_reset;
30 struct regmap *regmap;
31 struct device *dev;
32
33 int micbias_vg;
34
35 unsigned int dai_fmt;
36 unsigned int tdm_delay;
37 unsigned int slot_width;
38};
39
40static const char * const gpo_config_names[] = {
41 "ti,gpo-config-1",
42 "ti,gpo-config-2",
43 "ti,gpo-config-3",
44 "ti,gpo-config-4",
45};
46
47static const struct reg_default adcx140_reg_defaults[] = {
48 { ADCX140_PAGE_SELECT, 0x00 },
49 { ADCX140_SW_RESET, 0x00 },
50 { ADCX140_SLEEP_CFG, 0x00 },
51 { ADCX140_SHDN_CFG, 0x05 },
52 { ADCX140_ASI_CFG0, 0x30 },
53 { ADCX140_ASI_CFG1, 0x00 },
54 { ADCX140_ASI_CFG2, 0x00 },
55 { ADCX140_ASI_CH1, 0x00 },
56 { ADCX140_ASI_CH2, 0x01 },
57 { ADCX140_ASI_CH3, 0x02 },
58 { ADCX140_ASI_CH4, 0x03 },
59 { ADCX140_ASI_CH5, 0x04 },
60 { ADCX140_ASI_CH6, 0x05 },
61 { ADCX140_ASI_CH7, 0x06 },
62 { ADCX140_ASI_CH8, 0x07 },
63 { ADCX140_MST_CFG0, 0x02 },
64 { ADCX140_MST_CFG1, 0x48 },
65 { ADCX140_ASI_STS, 0xff },
66 { ADCX140_CLK_SRC, 0x10 },
67 { ADCX140_PDMCLK_CFG, 0x40 },
68 { ADCX140_PDM_CFG, 0x00 },
69 { ADCX140_GPIO_CFG0, 0x22 },
70 { ADCX140_GPO_CFG0, 0x00 },
71 { ADCX140_GPO_CFG1, 0x00 },
72 { ADCX140_GPO_CFG2, 0x00 },
73 { ADCX140_GPO_CFG3, 0x00 },
74 { ADCX140_GPO_VAL, 0x00 },
75 { ADCX140_GPIO_MON, 0x00 },
76 { ADCX140_GPI_CFG0, 0x00 },
77 { ADCX140_GPI_CFG1, 0x00 },
78 { ADCX140_GPI_MON, 0x00 },
79 { ADCX140_INT_CFG, 0x00 },
80 { ADCX140_INT_MASK0, 0xff },
81 { ADCX140_INT_LTCH0, 0x00 },
82 { ADCX140_BIAS_CFG, 0x00 },
83 { ADCX140_CH1_CFG0, 0x00 },
84 { ADCX140_CH1_CFG1, 0x00 },
85 { ADCX140_CH1_CFG2, 0xc9 },
86 { ADCX140_CH1_CFG3, 0x80 },
87 { ADCX140_CH1_CFG4, 0x00 },
88 { ADCX140_CH2_CFG0, 0x00 },
89 { ADCX140_CH2_CFG1, 0x00 },
90 { ADCX140_CH2_CFG2, 0xc9 },
91 { ADCX140_CH2_CFG3, 0x80 },
92 { ADCX140_CH2_CFG4, 0x00 },
93 { ADCX140_CH3_CFG0, 0x00 },
94 { ADCX140_CH3_CFG1, 0x00 },
95 { ADCX140_CH3_CFG2, 0xc9 },
96 { ADCX140_CH3_CFG3, 0x80 },
97 { ADCX140_CH3_CFG4, 0x00 },
98 { ADCX140_CH4_CFG0, 0x00 },
99 { ADCX140_CH4_CFG1, 0x00 },
100 { ADCX140_CH4_CFG2, 0xc9 },
101 { ADCX140_CH4_CFG3, 0x80 },
102 { ADCX140_CH4_CFG4, 0x00 },
103 { ADCX140_CH5_CFG2, 0xc9 },
104 { ADCX140_CH5_CFG3, 0x80 },
105 { ADCX140_CH5_CFG4, 0x00 },
106 { ADCX140_CH6_CFG2, 0xc9 },
107 { ADCX140_CH6_CFG3, 0x80 },
108 { ADCX140_CH6_CFG4, 0x00 },
109 { ADCX140_CH7_CFG2, 0xc9 },
110 { ADCX140_CH7_CFG3, 0x80 },
111 { ADCX140_CH7_CFG4, 0x00 },
112 { ADCX140_CH8_CFG2, 0xc9 },
113 { ADCX140_CH8_CFG3, 0x80 },
114 { ADCX140_CH8_CFG4, 0x00 },
115 { ADCX140_DSP_CFG0, 0x01 },
116 { ADCX140_DSP_CFG1, 0x40 },
117 { ADCX140_DRE_CFG0, 0x7b },
118 { ADCX140_AGC_CFG0, 0xe7 },
119 { ADCX140_IN_CH_EN, 0xf0 },
120 { ADCX140_ASI_OUT_CH_EN, 0x00 },
121 { ADCX140_PWR_CFG, 0x00 },
122 { ADCX140_DEV_STS0, 0x00 },
123 { ADCX140_DEV_STS1, 0x80 },
124};
125
126static const struct regmap_range_cfg adcx140_ranges[] = {
127 {
128 .range_min = 0,
129 .range_max = 12 * 128,
130 .selector_reg = ADCX140_PAGE_SELECT,
131 .selector_mask = 0xff,
132 .selector_shift = 0,
133 .window_start = 0,
134 .window_len = 128,
135 },
136};
137
138static bool adcx140_volatile(struct device *dev, unsigned int reg)
139{
140 switch (reg) {
141 case ADCX140_SW_RESET:
142 case ADCX140_DEV_STS0:
143 case ADCX140_DEV_STS1:
144 case ADCX140_ASI_STS:
145 return true;
146 default:
147 return false;
148 }
149}
150
151static const struct regmap_config adcx140_i2c_regmap = {
152 .reg_bits = 8,
153 .val_bits = 8,
154 .reg_defaults = adcx140_reg_defaults,
155 .num_reg_defaults = ARRAY_SIZE(adcx140_reg_defaults),
156 .cache_type = REGCACHE_FLAT,
157 .ranges = adcx140_ranges,
158 .num_ranges = ARRAY_SIZE(adcx140_ranges),
159 .max_register = 12 * 128,
160 .volatile_reg = adcx140_volatile,
161};
162
163
164static DECLARE_TLV_DB_SCALE(dig_vol_tlv, -10000, 50, 0);
165
166
167static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 100, 0);
168
169
170static DECLARE_TLV_DB_SCALE(dre_thresh_tlv, -6600, 100, 0);
171
172static DECLARE_TLV_DB_SCALE(dre_gain_tlv, 200, 200, 0);
173
174
175static DECLARE_TLV_DB_SCALE(agc_thresh_tlv, -3600, 200, 0);
176
177static DECLARE_TLV_DB_SCALE(agc_gain_tlv, 300, 300, 0);
178
179static const char * const decimation_filter_text[] = {
180 "Linear Phase", "Low Latency", "Ultra-low Latency"
181};
182
183static SOC_ENUM_SINGLE_DECL(decimation_filter_enum, ADCX140_DSP_CFG0, 4,
184 decimation_filter_text);
185
186static const struct snd_kcontrol_new decimation_filter_controls[] = {
187 SOC_DAPM_ENUM("Decimation Filter", decimation_filter_enum),
188};
189
190static const char * const pdmclk_text[] = {
191 "2.8224 MHz", "1.4112 MHz", "705.6 kHz", "5.6448 MHz"
192};
193
194static SOC_ENUM_SINGLE_DECL(pdmclk_select_enum, ADCX140_PDMCLK_CFG, 0,
195 pdmclk_text);
196
197static const struct snd_kcontrol_new pdmclk_div_controls[] = {
198 SOC_DAPM_ENUM("PDM Clk Divider Select", pdmclk_select_enum),
199};
200
201static const char * const resistor_text[] = {
202 "2.5 kOhm", "10 kOhm", "20 kOhm"
203};
204
205static SOC_ENUM_SINGLE_DECL(in1_resistor_enum, ADCX140_CH1_CFG0, 2,
206 resistor_text);
207static SOC_ENUM_SINGLE_DECL(in2_resistor_enum, ADCX140_CH2_CFG0, 2,
208 resistor_text);
209static SOC_ENUM_SINGLE_DECL(in3_resistor_enum, ADCX140_CH3_CFG0, 2,
210 resistor_text);
211static SOC_ENUM_SINGLE_DECL(in4_resistor_enum, ADCX140_CH4_CFG0, 2,
212 resistor_text);
213
214static const struct snd_kcontrol_new in1_resistor_controls[] = {
215 SOC_DAPM_ENUM("CH1 Resistor Select", in1_resistor_enum),
216};
217static const struct snd_kcontrol_new in2_resistor_controls[] = {
218 SOC_DAPM_ENUM("CH2 Resistor Select", in2_resistor_enum),
219};
220static const struct snd_kcontrol_new in3_resistor_controls[] = {
221 SOC_DAPM_ENUM("CH3 Resistor Select", in3_resistor_enum),
222};
223static const struct snd_kcontrol_new in4_resistor_controls[] = {
224 SOC_DAPM_ENUM("CH4 Resistor Select", in4_resistor_enum),
225};
226
227
228static const char * const adcx140_mic_sel_text[] = {"Analog", "Line In", "Digital"};
229static const char * const adcx140_analog_sel_text[] = {"Analog", "Line In"};
230
231static SOC_ENUM_SINGLE_DECL(adcx140_mic1p_enum,
232 ADCX140_CH1_CFG0, 5,
233 adcx140_mic_sel_text);
234
235static const struct snd_kcontrol_new adcx140_dapm_mic1p_control =
236SOC_DAPM_ENUM("MIC1P MUX", adcx140_mic1p_enum);
237
238static SOC_ENUM_SINGLE_DECL(adcx140_mic1_analog_enum,
239 ADCX140_CH1_CFG0, 7,
240 adcx140_analog_sel_text);
241
242static const struct snd_kcontrol_new adcx140_dapm_mic1_analog_control =
243SOC_DAPM_ENUM("MIC1 Analog MUX", adcx140_mic1_analog_enum);
244
245static SOC_ENUM_SINGLE_DECL(adcx140_mic1m_enum,
246 ADCX140_CH1_CFG0, 5,
247 adcx140_mic_sel_text);
248
249static const struct snd_kcontrol_new adcx140_dapm_mic1m_control =
250SOC_DAPM_ENUM("MIC1M MUX", adcx140_mic1m_enum);
251
252static SOC_ENUM_SINGLE_DECL(adcx140_mic2p_enum,
253 ADCX140_CH2_CFG0, 5,
254 adcx140_mic_sel_text);
255
256static const struct snd_kcontrol_new adcx140_dapm_mic2p_control =
257SOC_DAPM_ENUM("MIC2P MUX", adcx140_mic2p_enum);
258
259static SOC_ENUM_SINGLE_DECL(adcx140_mic2_analog_enum,
260 ADCX140_CH2_CFG0, 7,
261 adcx140_analog_sel_text);
262
263static const struct snd_kcontrol_new adcx140_dapm_mic2_analog_control =
264SOC_DAPM_ENUM("MIC2 Analog MUX", adcx140_mic2_analog_enum);
265
266static SOC_ENUM_SINGLE_DECL(adcx140_mic2m_enum,
267 ADCX140_CH2_CFG0, 5,
268 adcx140_mic_sel_text);
269
270static const struct snd_kcontrol_new adcx140_dapm_mic2m_control =
271SOC_DAPM_ENUM("MIC2M MUX", adcx140_mic2m_enum);
272
273static SOC_ENUM_SINGLE_DECL(adcx140_mic3p_enum,
274 ADCX140_CH3_CFG0, 5,
275 adcx140_mic_sel_text);
276
277static const struct snd_kcontrol_new adcx140_dapm_mic3p_control =
278SOC_DAPM_ENUM("MIC3P MUX", adcx140_mic3p_enum);
279
280static SOC_ENUM_SINGLE_DECL(adcx140_mic3_analog_enum,
281 ADCX140_CH3_CFG0, 7,
282 adcx140_analog_sel_text);
283
284static const struct snd_kcontrol_new adcx140_dapm_mic3_analog_control =
285SOC_DAPM_ENUM("MIC3 Analog MUX", adcx140_mic3_analog_enum);
286
287static SOC_ENUM_SINGLE_DECL(adcx140_mic3m_enum,
288 ADCX140_CH3_CFG0, 5,
289 adcx140_mic_sel_text);
290
291static const struct snd_kcontrol_new adcx140_dapm_mic3m_control =
292SOC_DAPM_ENUM("MIC3M MUX", adcx140_mic3m_enum);
293
294static SOC_ENUM_SINGLE_DECL(adcx140_mic4p_enum,
295 ADCX140_CH4_CFG0, 5,
296 adcx140_mic_sel_text);
297
298static const struct snd_kcontrol_new adcx140_dapm_mic4p_control =
299SOC_DAPM_ENUM("MIC4P MUX", adcx140_mic4p_enum);
300
301static SOC_ENUM_SINGLE_DECL(adcx140_mic4_analog_enum,
302 ADCX140_CH4_CFG0, 7,
303 adcx140_analog_sel_text);
304
305static const struct snd_kcontrol_new adcx140_dapm_mic4_analog_control =
306SOC_DAPM_ENUM("MIC4 Analog MUX", adcx140_mic4_analog_enum);
307
308static SOC_ENUM_SINGLE_DECL(adcx140_mic4m_enum,
309 ADCX140_CH4_CFG0, 5,
310 adcx140_mic_sel_text);
311
312static const struct snd_kcontrol_new adcx140_dapm_mic4m_control =
313SOC_DAPM_ENUM("MIC4M MUX", adcx140_mic4m_enum);
314
315static const struct snd_kcontrol_new adcx140_dapm_ch1_en_switch =
316 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 7, 1, 0);
317static const struct snd_kcontrol_new adcx140_dapm_ch2_en_switch =
318 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 6, 1, 0);
319static const struct snd_kcontrol_new adcx140_dapm_ch3_en_switch =
320 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 5, 1, 0);
321static const struct snd_kcontrol_new adcx140_dapm_ch4_en_switch =
322 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 4, 1, 0);
323static const struct snd_kcontrol_new adcx140_dapm_ch5_en_switch =
324 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 3, 1, 0);
325static const struct snd_kcontrol_new adcx140_dapm_ch6_en_switch =
326 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 2, 1, 0);
327static const struct snd_kcontrol_new adcx140_dapm_ch7_en_switch =
328 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 1, 1, 0);
329static const struct snd_kcontrol_new adcx140_dapm_ch8_en_switch =
330 SOC_DAPM_SINGLE("Switch", ADCX140_ASI_OUT_CH_EN, 0, 1, 0);
331
332static const struct snd_kcontrol_new adcx140_dapm_ch1_dre_en_switch =
333 SOC_DAPM_SINGLE("Switch", ADCX140_CH1_CFG0, 0, 1, 0);
334static const struct snd_kcontrol_new adcx140_dapm_ch2_dre_en_switch =
335 SOC_DAPM_SINGLE("Switch", ADCX140_CH2_CFG0, 0, 1, 0);
336static const struct snd_kcontrol_new adcx140_dapm_ch3_dre_en_switch =
337 SOC_DAPM_SINGLE("Switch", ADCX140_CH3_CFG0, 0, 1, 0);
338static const struct snd_kcontrol_new adcx140_dapm_ch4_dre_en_switch =
339 SOC_DAPM_SINGLE("Switch", ADCX140_CH4_CFG0, 0, 1, 0);
340
341static const struct snd_kcontrol_new adcx140_dapm_dre_en_switch =
342 SOC_DAPM_SINGLE("Switch", ADCX140_DSP_CFG1, 3, 1, 0);
343
344
345static const struct snd_kcontrol_new adcx140_output_mixer_controls[] = {
346 SOC_DAPM_SINGLE("Digital CH1 Switch", 0, 0, 0, 0),
347 SOC_DAPM_SINGLE("Digital CH2 Switch", 0, 0, 0, 0),
348 SOC_DAPM_SINGLE("Digital CH3 Switch", 0, 0, 0, 0),
349 SOC_DAPM_SINGLE("Digital CH4 Switch", 0, 0, 0, 0),
350};
351
352static const struct snd_soc_dapm_widget adcx140_dapm_widgets[] = {
353
354 SND_SOC_DAPM_INPUT("MIC1P"),
355 SND_SOC_DAPM_INPUT("MIC1M"),
356 SND_SOC_DAPM_INPUT("MIC2P"),
357 SND_SOC_DAPM_INPUT("MIC2M"),
358 SND_SOC_DAPM_INPUT("MIC3P"),
359 SND_SOC_DAPM_INPUT("MIC3M"),
360 SND_SOC_DAPM_INPUT("MIC4P"),
361 SND_SOC_DAPM_INPUT("MIC4M"),
362
363 SND_SOC_DAPM_OUTPUT("CH1_OUT"),
364 SND_SOC_DAPM_OUTPUT("CH2_OUT"),
365 SND_SOC_DAPM_OUTPUT("CH3_OUT"),
366 SND_SOC_DAPM_OUTPUT("CH4_OUT"),
367 SND_SOC_DAPM_OUTPUT("CH5_OUT"),
368 SND_SOC_DAPM_OUTPUT("CH6_OUT"),
369 SND_SOC_DAPM_OUTPUT("CH7_OUT"),
370 SND_SOC_DAPM_OUTPUT("CH8_OUT"),
371
372 SND_SOC_DAPM_MIXER("Output Mixer", SND_SOC_NOPM, 0, 0,
373 &adcx140_output_mixer_controls[0],
374 ARRAY_SIZE(adcx140_output_mixer_controls)),
375
376
377 SND_SOC_DAPM_MUX("MIC1P Input Mux", SND_SOC_NOPM, 0, 0,
378 &adcx140_dapm_mic1p_control),
379 SND_SOC_DAPM_MUX("MIC2P Input Mux", SND_SOC_NOPM, 0, 0,
380 &adcx140_dapm_mic2p_control),
381 SND_SOC_DAPM_MUX("MIC3P Input Mux", SND_SOC_NOPM, 0, 0,
382 &adcx140_dapm_mic3p_control),
383 SND_SOC_DAPM_MUX("MIC4P Input Mux", SND_SOC_NOPM, 0, 0,
384 &adcx140_dapm_mic4p_control),
385
386
387 SND_SOC_DAPM_MUX("MIC1 Analog Mux", SND_SOC_NOPM, 0, 0,
388 &adcx140_dapm_mic1_analog_control),
389 SND_SOC_DAPM_MUX("MIC2 Analog Mux", SND_SOC_NOPM, 0, 0,
390 &adcx140_dapm_mic2_analog_control),
391 SND_SOC_DAPM_MUX("MIC3 Analog Mux", SND_SOC_NOPM, 0, 0,
392 &adcx140_dapm_mic3_analog_control),
393 SND_SOC_DAPM_MUX("MIC4 Analog Mux", SND_SOC_NOPM, 0, 0,
394 &adcx140_dapm_mic4_analog_control),
395
396 SND_SOC_DAPM_MUX("MIC1M Input Mux", SND_SOC_NOPM, 0, 0,
397 &adcx140_dapm_mic1m_control),
398 SND_SOC_DAPM_MUX("MIC2M Input Mux", SND_SOC_NOPM, 0, 0,
399 &adcx140_dapm_mic2m_control),
400 SND_SOC_DAPM_MUX("MIC3M Input Mux", SND_SOC_NOPM, 0, 0,
401 &adcx140_dapm_mic3m_control),
402 SND_SOC_DAPM_MUX("MIC4M Input Mux", SND_SOC_NOPM, 0, 0,
403 &adcx140_dapm_mic4m_control),
404
405 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH1", SND_SOC_NOPM, 0, 0, NULL, 0),
406 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH2", SND_SOC_NOPM, 0, 0, NULL, 0),
407 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH3", SND_SOC_NOPM, 0, 0, NULL, 0),
408 SND_SOC_DAPM_PGA("MIC_GAIN_CTL_CH4", SND_SOC_NOPM, 0, 0, NULL, 0),
409
410 SND_SOC_DAPM_ADC("CH1_ADC", "CH1 Capture", ADCX140_IN_CH_EN, 7, 0),
411 SND_SOC_DAPM_ADC("CH2_ADC", "CH2 Capture", ADCX140_IN_CH_EN, 6, 0),
412 SND_SOC_DAPM_ADC("CH3_ADC", "CH3 Capture", ADCX140_IN_CH_EN, 5, 0),
413 SND_SOC_DAPM_ADC("CH4_ADC", "CH4 Capture", ADCX140_IN_CH_EN, 4, 0),
414
415 SND_SOC_DAPM_SWITCH("CH1_ASI_EN", SND_SOC_NOPM, 0, 0,
416 &adcx140_dapm_ch1_en_switch),
417 SND_SOC_DAPM_SWITCH("CH2_ASI_EN", SND_SOC_NOPM, 0, 0,
418 &adcx140_dapm_ch2_en_switch),
419 SND_SOC_DAPM_SWITCH("CH3_ASI_EN", SND_SOC_NOPM, 0, 0,
420 &adcx140_dapm_ch3_en_switch),
421 SND_SOC_DAPM_SWITCH("CH4_ASI_EN", SND_SOC_NOPM, 0, 0,
422 &adcx140_dapm_ch4_en_switch),
423
424 SND_SOC_DAPM_SWITCH("CH5_ASI_EN", SND_SOC_NOPM, 0, 0,
425 &adcx140_dapm_ch5_en_switch),
426 SND_SOC_DAPM_SWITCH("CH6_ASI_EN", SND_SOC_NOPM, 0, 0,
427 &adcx140_dapm_ch6_en_switch),
428 SND_SOC_DAPM_SWITCH("CH7_ASI_EN", SND_SOC_NOPM, 0, 0,
429 &adcx140_dapm_ch7_en_switch),
430 SND_SOC_DAPM_SWITCH("CH8_ASI_EN", SND_SOC_NOPM, 0, 0,
431 &adcx140_dapm_ch8_en_switch),
432
433 SND_SOC_DAPM_SWITCH("DRE_ENABLE", SND_SOC_NOPM, 0, 0,
434 &adcx140_dapm_dre_en_switch),
435
436 SND_SOC_DAPM_SWITCH("CH1_DRE_EN", SND_SOC_NOPM, 0, 0,
437 &adcx140_dapm_ch1_dre_en_switch),
438 SND_SOC_DAPM_SWITCH("CH2_DRE_EN", SND_SOC_NOPM, 0, 0,
439 &adcx140_dapm_ch2_dre_en_switch),
440 SND_SOC_DAPM_SWITCH("CH3_DRE_EN", SND_SOC_NOPM, 0, 0,
441 &adcx140_dapm_ch3_dre_en_switch),
442 SND_SOC_DAPM_SWITCH("CH4_DRE_EN", SND_SOC_NOPM, 0, 0,
443 &adcx140_dapm_ch4_dre_en_switch),
444
445 SND_SOC_DAPM_MUX("IN1 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
446 in1_resistor_controls),
447 SND_SOC_DAPM_MUX("IN2 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
448 in2_resistor_controls),
449 SND_SOC_DAPM_MUX("IN3 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
450 in3_resistor_controls),
451 SND_SOC_DAPM_MUX("IN4 Analog Mic Resistor", SND_SOC_NOPM, 0, 0,
452 in4_resistor_controls),
453
454 SND_SOC_DAPM_MUX("PDM Clk Div Select", SND_SOC_NOPM, 0, 0,
455 pdmclk_div_controls),
456
457 SND_SOC_DAPM_MUX("Decimation Filter", SND_SOC_NOPM, 0, 0,
458 decimation_filter_controls),
459};
460
461static const struct snd_soc_dapm_route adcx140_audio_map[] = {
462
463 {"CH1_OUT", NULL, "Output Mixer"},
464 {"CH2_OUT", NULL, "Output Mixer"},
465 {"CH3_OUT", NULL, "Output Mixer"},
466 {"CH4_OUT", NULL, "Output Mixer"},
467
468 {"CH1_ASI_EN", "Switch", "CH1_ADC"},
469 {"CH2_ASI_EN", "Switch", "CH2_ADC"},
470 {"CH3_ASI_EN", "Switch", "CH3_ADC"},
471 {"CH4_ASI_EN", "Switch", "CH4_ADC"},
472
473 {"CH5_ASI_EN", "Switch", "CH5_OUT"},
474 {"CH6_ASI_EN", "Switch", "CH6_OUT"},
475 {"CH7_ASI_EN", "Switch", "CH7_OUT"},
476 {"CH8_ASI_EN", "Switch", "CH8_OUT"},
477
478 {"Decimation Filter", "Linear Phase", "DRE_ENABLE"},
479 {"Decimation Filter", "Low Latency", "DRE_ENABLE"},
480 {"Decimation Filter", "Ultra-low Latency", "DRE_ENABLE"},
481
482 {"DRE_ENABLE", "Switch", "CH1_DRE_EN"},
483 {"DRE_ENABLE", "Switch", "CH2_DRE_EN"},
484 {"DRE_ENABLE", "Switch", "CH3_DRE_EN"},
485 {"DRE_ENABLE", "Switch", "CH4_DRE_EN"},
486
487 {"CH1_DRE_EN", "Switch", "CH1_ADC"},
488 {"CH2_DRE_EN", "Switch", "CH2_ADC"},
489 {"CH3_DRE_EN", "Switch", "CH3_ADC"},
490 {"CH4_DRE_EN", "Switch", "CH4_ADC"},
491
492
493 {"CH1_ADC", NULL, "MIC_GAIN_CTL_CH1"},
494 {"CH2_ADC", NULL, "MIC_GAIN_CTL_CH2"},
495 {"CH3_ADC", NULL, "MIC_GAIN_CTL_CH3"},
496 {"CH4_ADC", NULL, "MIC_GAIN_CTL_CH4"},
497
498 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
499 {"MIC_GAIN_CTL_CH1", NULL, "IN1 Analog Mic Resistor"},
500 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
501 {"MIC_GAIN_CTL_CH2", NULL, "IN2 Analog Mic Resistor"},
502 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
503 {"MIC_GAIN_CTL_CH3", NULL, "IN3 Analog Mic Resistor"},
504 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
505 {"MIC_GAIN_CTL_CH4", NULL, "IN4 Analog Mic Resistor"},
506
507 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1P Input Mux"},
508 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1P Input Mux"},
509 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1P Input Mux"},
510
511 {"IN1 Analog Mic Resistor", "2.5 kOhm", "MIC1M Input Mux"},
512 {"IN1 Analog Mic Resistor", "10 kOhm", "MIC1M Input Mux"},
513 {"IN1 Analog Mic Resistor", "20 kOhm", "MIC1M Input Mux"},
514
515 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2P Input Mux"},
516 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2P Input Mux"},
517 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2P Input Mux"},
518
519 {"IN2 Analog Mic Resistor", "2.5 kOhm", "MIC2M Input Mux"},
520 {"IN2 Analog Mic Resistor", "10 kOhm", "MIC2M Input Mux"},
521 {"IN2 Analog Mic Resistor", "20 kOhm", "MIC2M Input Mux"},
522
523 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3P Input Mux"},
524 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3P Input Mux"},
525 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3P Input Mux"},
526
527 {"IN3 Analog Mic Resistor", "2.5 kOhm", "MIC3M Input Mux"},
528 {"IN3 Analog Mic Resistor", "10 kOhm", "MIC3M Input Mux"},
529 {"IN3 Analog Mic Resistor", "20 kOhm", "MIC3M Input Mux"},
530
531 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4P Input Mux"},
532 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4P Input Mux"},
533 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4P Input Mux"},
534
535 {"IN4 Analog Mic Resistor", "2.5 kOhm", "MIC4M Input Mux"},
536 {"IN4 Analog Mic Resistor", "10 kOhm", "MIC4M Input Mux"},
537 {"IN4 Analog Mic Resistor", "20 kOhm", "MIC4M Input Mux"},
538
539 {"PDM Clk Div Select", "2.8224 MHz", "MIC1P Input Mux"},
540 {"PDM Clk Div Select", "1.4112 MHz", "MIC1P Input Mux"},
541 {"PDM Clk Div Select", "705.6 kHz", "MIC1P Input Mux"},
542 {"PDM Clk Div Select", "5.6448 MHz", "MIC1P Input Mux"},
543
544 {"MIC1 Analog Mux", "Line In", "MIC1P"},
545 {"MIC2 Analog Mux", "Line In", "MIC2P"},
546 {"MIC3 Analog Mux", "Line In", "MIC3P"},
547 {"MIC4 Analog Mux", "Line In", "MIC4P"},
548
549 {"MIC1P Input Mux", "Analog", "MIC1P"},
550 {"MIC1M Input Mux", "Analog", "MIC1M"},
551 {"MIC2P Input Mux", "Analog", "MIC2P"},
552 {"MIC2M Input Mux", "Analog", "MIC2M"},
553 {"MIC3P Input Mux", "Analog", "MIC3P"},
554 {"MIC3M Input Mux", "Analog", "MIC3M"},
555 {"MIC4P Input Mux", "Analog", "MIC4P"},
556 {"MIC4M Input Mux", "Analog", "MIC4M"},
557};
558
559static const struct snd_kcontrol_new adcx140_snd_controls[] = {
560 SOC_SINGLE_TLV("Analog CH1 Mic Gain Volume", ADCX140_CH1_CFG1, 2, 42, 0,
561 adc_tlv),
562 SOC_SINGLE_TLV("Analog CH2 Mic Gain Volume", ADCX140_CH2_CFG1, 2, 42, 0,
563 adc_tlv),
564 SOC_SINGLE_TLV("Analog CH3 Mic Gain Volume", ADCX140_CH3_CFG1, 2, 42, 0,
565 adc_tlv),
566 SOC_SINGLE_TLV("Analog CH4 Mic Gain Volume", ADCX140_CH4_CFG1, 2, 42, 0,
567 adc_tlv),
568
569 SOC_SINGLE_TLV("DRE Threshold", ADCX140_DRE_CFG0, 4, 9, 0,
570 dre_thresh_tlv),
571 SOC_SINGLE_TLV("DRE Max Gain", ADCX140_DRE_CFG0, 0, 12, 0,
572 dre_gain_tlv),
573
574 SOC_SINGLE_TLV("AGC Threshold", ADCX140_AGC_CFG0, 4, 15, 0,
575 agc_thresh_tlv),
576 SOC_SINGLE_TLV("AGC Max Gain", ADCX140_AGC_CFG0, 0, 13, 0,
577 agc_gain_tlv),
578
579 SOC_SINGLE_TLV("Digital CH1 Out Volume", ADCX140_CH1_CFG2,
580 0, 0xff, 0, dig_vol_tlv),
581 SOC_SINGLE_TLV("Digital CH2 Out Volume", ADCX140_CH2_CFG2,
582 0, 0xff, 0, dig_vol_tlv),
583 SOC_SINGLE_TLV("Digital CH3 Out Volume", ADCX140_CH3_CFG2,
584 0, 0xff, 0, dig_vol_tlv),
585 SOC_SINGLE_TLV("Digital CH4 Out Volume", ADCX140_CH4_CFG2,
586 0, 0xff, 0, dig_vol_tlv),
587 SOC_SINGLE_TLV("Digital CH5 Out Volume", ADCX140_CH5_CFG2,
588 0, 0xff, 0, dig_vol_tlv),
589 SOC_SINGLE_TLV("Digital CH6 Out Volume", ADCX140_CH6_CFG2,
590 0, 0xff, 0, dig_vol_tlv),
591 SOC_SINGLE_TLV("Digital CH7 Out Volume", ADCX140_CH7_CFG2,
592 0, 0xff, 0, dig_vol_tlv),
593 SOC_SINGLE_TLV("Digital CH8 Out Volume", ADCX140_CH8_CFG2,
594 0, 0xff, 0, dig_vol_tlv),
595};
596
597static int adcx140_reset(struct adcx140_priv *adcx140)
598{
599 int ret = 0;
600
601 if (adcx140->gpio_reset) {
602 gpiod_direction_output(adcx140->gpio_reset, 0);
603
604 usleep_range(30000, 100000);
605 gpiod_direction_output(adcx140->gpio_reset, 1);
606 } else {
607 ret = regmap_write(adcx140->regmap, ADCX140_SW_RESET,
608 ADCX140_RESET);
609 }
610
611
612 usleep_range(10000, 100000);
613
614 return ret;
615}
616
617static int adcx140_hw_params(struct snd_pcm_substream *substream,
618 struct snd_pcm_hw_params *params,
619 struct snd_soc_dai *dai)
620{
621 struct snd_soc_component *component = dai->component;
622 u8 data = 0;
623
624 switch (params_width(params)) {
625 case 16:
626 data = ADCX140_16_BIT_WORD;
627 break;
628 case 20:
629 data = ADCX140_20_BIT_WORD;
630 break;
631 case 24:
632 data = ADCX140_24_BIT_WORD;
633 break;
634 case 32:
635 data = ADCX140_32_BIT_WORD;
636 break;
637 default:
638 dev_err(component->dev, "%s: Unsupported width %d\n",
639 __func__, params_width(params));
640 return -EINVAL;
641 }
642
643 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
644 ADCX140_WORD_LEN_MSK, data);
645
646 return 0;
647}
648
649static int adcx140_set_dai_fmt(struct snd_soc_dai *codec_dai,
650 unsigned int fmt)
651{
652 struct snd_soc_component *component = codec_dai->component;
653 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
654 u8 iface_reg1 = 0;
655 u8 iface_reg2 = 0;
656 int offset = 0;
657 int width = adcx140->slot_width;
658
659
660 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
661 case SND_SOC_DAIFMT_CBM_CFM:
662 iface_reg2 |= ADCX140_BCLK_FSYNC_MASTER;
663 break;
664 case SND_SOC_DAIFMT_CBS_CFS:
665 break;
666 case SND_SOC_DAIFMT_CBS_CFM:
667 case SND_SOC_DAIFMT_CBM_CFS:
668 default:
669 dev_err(component->dev, "Invalid DAI master/slave interface\n");
670 return -EINVAL;
671 }
672
673
674 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
675 case SND_SOC_DAIFMT_NB_IF:
676 iface_reg1 |= ADCX140_FSYNCINV_BIT;
677 break;
678 case SND_SOC_DAIFMT_IB_IF:
679 iface_reg1 |= ADCX140_BCLKINV_BIT | ADCX140_FSYNCINV_BIT;
680 break;
681 case SND_SOC_DAIFMT_IB_NF:
682 iface_reg1 |= ADCX140_BCLKINV_BIT;
683 break;
684 case SND_SOC_DAIFMT_NB_NF:
685 break;
686 default:
687 dev_err(component->dev, "Invalid DAI clock signal polarity\n");
688 return -EINVAL;
689 }
690
691
692 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
693 case SND_SOC_DAIFMT_I2S:
694 iface_reg1 |= ADCX140_I2S_MODE_BIT;
695 break;
696 case SND_SOC_DAIFMT_LEFT_J:
697 iface_reg1 |= ADCX140_LEFT_JUST_BIT;
698 break;
699 case SND_SOC_DAIFMT_DSP_A:
700 offset += (adcx140->tdm_delay * width + 1);
701 break;
702 case SND_SOC_DAIFMT_DSP_B:
703 offset += adcx140->tdm_delay * width;
704 break;
705 default:
706 dev_err(component->dev, "Invalid DAI interface format\n");
707 return -EINVAL;
708 }
709
710 adcx140->dai_fmt = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
711
712 snd_soc_component_update_bits(component, ADCX140_ASI_CFG0,
713 ADCX140_FSYNCINV_BIT |
714 ADCX140_BCLKINV_BIT |
715 ADCX140_ASI_FORMAT_MSK,
716 iface_reg1);
717 snd_soc_component_update_bits(component, ADCX140_MST_CFG0,
718 ADCX140_BCLK_FSYNC_MASTER, iface_reg2);
719
720
721 snd_soc_component_update_bits(component, ADCX140_ASI_CFG1,
722 ADCX140_TX_OFFSET_MASK, offset);
723
724
725 return 0;
726}
727
728static int adcx140_set_dai_tdm_slot(struct snd_soc_dai *codec_dai,
729 unsigned int tx_mask, unsigned int rx_mask,
730 int slots, int slot_width)
731{
732 struct snd_soc_component *component = codec_dai->component;
733 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
734 unsigned int lsb;
735
736
737 lsb = __ffs(tx_mask);
738 if ((lsb + 1) != __fls(tx_mask)) {
739 dev_err(component->dev, "Invalid mask, slots must be adjacent\n");
740 return -EINVAL;
741 }
742
743 switch (slot_width) {
744 case 16:
745 case 20:
746 case 24:
747 case 32:
748 break;
749 default:
750 dev_err(component->dev, "Unsupported slot width %d\n", slot_width);
751 return -EINVAL;
752 }
753
754 adcx140->tdm_delay = lsb;
755 adcx140->slot_width = slot_width;
756
757 return 0;
758}
759
760static const struct snd_soc_dai_ops adcx140_dai_ops = {
761 .hw_params = adcx140_hw_params,
762 .set_fmt = adcx140_set_dai_fmt,
763 .set_tdm_slot = adcx140_set_dai_tdm_slot,
764};
765
766static int adcx140_configure_gpo(struct adcx140_priv *adcx140)
767{
768 u32 gpo_outputs[ADCX140_NUM_GPOS];
769 u32 gpo_output_val = 0;
770 int ret;
771 int i;
772
773 for (i = 0; i < ADCX140_NUM_GPOS; i++) {
774 ret = device_property_read_u32_array(adcx140->dev,
775 gpo_config_names[i],
776 gpo_outputs,
777 ADCX140_NUM_GPO_CFGS);
778 if (ret)
779 continue;
780
781 if (gpo_outputs[0] > ADCX140_GPO_CFG_MAX) {
782 dev_err(adcx140->dev, "GPO%d config out of range\n", i + 1);
783 return -EINVAL;
784 }
785
786 if (gpo_outputs[1] > ADCX140_GPO_DRV_MAX) {
787 dev_err(adcx140->dev, "GPO%d drive out of range\n", i + 1);
788 return -EINVAL;
789 }
790
791 gpo_output_val = gpo_outputs[0] << ADCX140_GPO_SHIFT |
792 gpo_outputs[1];
793 ret = regmap_write(adcx140->regmap, ADCX140_GPO_CFG0 + i,
794 gpo_output_val);
795 if (ret)
796 return ret;
797 }
798
799 return 0;
800
801}
802
803static int adcx140_codec_probe(struct snd_soc_component *component)
804{
805 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
806 int sleep_cfg_val = ADCX140_WAKE_DEV;
807 u32 bias_source;
808 u32 vref_source;
809 u8 bias_cfg;
810 int pdm_count;
811 u32 pdm_edges[ADCX140_NUM_PDM_EDGES];
812 u32 pdm_edge_val = 0;
813 int gpi_count;
814 u32 gpi_inputs[ADCX140_NUM_GPI_PINS];
815 u32 gpi_input_val = 0;
816 int i;
817 int ret;
818
819 ret = device_property_read_u32(adcx140->dev, "ti,mic-bias-source",
820 &bias_source);
821 if (ret)
822 bias_source = ADCX140_MIC_BIAS_VAL_VREF;
823
824 if (bias_source > ADCX140_MIC_BIAS_VAL_AVDD) {
825 dev_err(adcx140->dev, "Mic Bias source value is invalid\n");
826 return -EINVAL;
827 }
828
829 ret = device_property_read_u32(adcx140->dev, "ti,vref-source",
830 &vref_source);
831 if (ret)
832 vref_source = ADCX140_MIC_BIAS_VREF_275V;
833
834 if (vref_source > ADCX140_MIC_BIAS_VREF_1375V) {
835 dev_err(adcx140->dev, "Mic Bias source value is invalid\n");
836 return -EINVAL;
837 }
838
839 bias_cfg = bias_source << ADCX140_MIC_BIAS_SHIFT | vref_source;
840
841 ret = adcx140_reset(adcx140);
842 if (ret)
843 goto out;
844
845 if (adcx140->supply_areg == NULL)
846 sleep_cfg_val |= ADCX140_AREG_INTERNAL;
847
848 ret = regmap_write(adcx140->regmap, ADCX140_SLEEP_CFG, sleep_cfg_val);
849 if (ret) {
850 dev_err(adcx140->dev, "setting sleep config failed %d\n", ret);
851 goto out;
852 }
853
854
855 usleep_range(1000, 100000);
856
857 pdm_count = device_property_count_u32(adcx140->dev,
858 "ti,pdm-edge-select");
859 if (pdm_count <= ADCX140_NUM_PDM_EDGES && pdm_count > 0) {
860 ret = device_property_read_u32_array(adcx140->dev,
861 "ti,pdm-edge-select",
862 pdm_edges, pdm_count);
863 if (ret)
864 return ret;
865
866 for (i = 0; i < pdm_count; i++)
867 pdm_edge_val |= pdm_edges[i] << (ADCX140_PDM_EDGE_SHIFT - i);
868
869 ret = regmap_write(adcx140->regmap, ADCX140_PDM_CFG,
870 pdm_edge_val);
871 if (ret)
872 return ret;
873 }
874
875 gpi_count = device_property_count_u32(adcx140->dev, "ti,gpi-config");
876 if (gpi_count <= ADCX140_NUM_GPI_PINS && gpi_count > 0) {
877 ret = device_property_read_u32_array(adcx140->dev,
878 "ti,gpi-config",
879 gpi_inputs, gpi_count);
880 if (ret)
881 return ret;
882
883 gpi_input_val = gpi_inputs[ADCX140_GPI1_INDEX] << ADCX140_GPI_SHIFT |
884 gpi_inputs[ADCX140_GPI2_INDEX];
885
886 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG0,
887 gpi_input_val);
888 if (ret)
889 return ret;
890
891 gpi_input_val = gpi_inputs[ADCX140_GPI3_INDEX] << ADCX140_GPI_SHIFT |
892 gpi_inputs[ADCX140_GPI4_INDEX];
893
894 ret = regmap_write(adcx140->regmap, ADCX140_GPI_CFG1,
895 gpi_input_val);
896 if (ret)
897 return ret;
898 }
899
900 ret = adcx140_configure_gpo(adcx140);
901 if (ret)
902 goto out;
903
904 ret = regmap_update_bits(adcx140->regmap, ADCX140_BIAS_CFG,
905 ADCX140_MIC_BIAS_VAL_MSK |
906 ADCX140_MIC_BIAS_VREF_MSK, bias_cfg);
907 if (ret)
908 dev_err(adcx140->dev, "setting MIC bias failed %d\n", ret);
909out:
910 return ret;
911}
912
913static int adcx140_set_bias_level(struct snd_soc_component *component,
914 enum snd_soc_bias_level level)
915{
916 struct adcx140_priv *adcx140 = snd_soc_component_get_drvdata(component);
917 int pwr_cfg = 0;
918
919 switch (level) {
920 case SND_SOC_BIAS_ON:
921 case SND_SOC_BIAS_PREPARE:
922 case SND_SOC_BIAS_STANDBY:
923 pwr_cfg = ADCX140_PWR_CFG_BIAS_PDZ | ADCX140_PWR_CFG_PLL_PDZ |
924 ADCX140_PWR_CFG_ADC_PDZ;
925 break;
926 case SND_SOC_BIAS_OFF:
927 pwr_cfg = 0x0;
928 break;
929 }
930
931 return regmap_write(adcx140->regmap, ADCX140_PWR_CFG, pwr_cfg);
932}
933
934static const struct snd_soc_component_driver soc_codec_driver_adcx140 = {
935 .probe = adcx140_codec_probe,
936 .set_bias_level = adcx140_set_bias_level,
937 .controls = adcx140_snd_controls,
938 .num_controls = ARRAY_SIZE(adcx140_snd_controls),
939 .dapm_widgets = adcx140_dapm_widgets,
940 .num_dapm_widgets = ARRAY_SIZE(adcx140_dapm_widgets),
941 .dapm_routes = adcx140_audio_map,
942 .num_dapm_routes = ARRAY_SIZE(adcx140_audio_map),
943 .suspend_bias_off = 1,
944 .idle_bias_on = 0,
945 .use_pmdown_time = 1,
946 .endianness = 1,
947 .non_legacy_dai_naming = 1,
948};
949
950static struct snd_soc_dai_driver adcx140_dai_driver[] = {
951 {
952 .name = "tlv320adcx140-codec",
953 .capture = {
954 .stream_name = "Capture",
955 .channels_min = 2,
956 .channels_max = ADCX140_MAX_CHANNELS,
957 .rates = ADCX140_RATES,
958 .formats = ADCX140_FORMATS,
959 },
960 .ops = &adcx140_dai_ops,
961 .symmetric_rates = 1,
962 }
963};
964
965static const struct of_device_id tlv320adcx140_of_match[] = {
966 { .compatible = "ti,tlv320adc3140" },
967 { .compatible = "ti,tlv320adc5140" },
968 { .compatible = "ti,tlv320adc6140" },
969 {},
970};
971MODULE_DEVICE_TABLE(of, tlv320adcx140_of_match);
972
973static int adcx140_i2c_probe(struct i2c_client *i2c,
974 const struct i2c_device_id *id)
975{
976 struct adcx140_priv *adcx140;
977 int ret;
978
979 adcx140 = devm_kzalloc(&i2c->dev, sizeof(*adcx140), GFP_KERNEL);
980 if (!adcx140)
981 return -ENOMEM;
982
983 adcx140->dev = &i2c->dev;
984
985 adcx140->gpio_reset = devm_gpiod_get_optional(adcx140->dev,
986 "reset", GPIOD_OUT_LOW);
987 if (IS_ERR(adcx140->gpio_reset))
988 dev_info(&i2c->dev, "Reset GPIO not defined\n");
989
990 adcx140->supply_areg = devm_regulator_get_optional(adcx140->dev,
991 "areg");
992 if (IS_ERR(adcx140->supply_areg)) {
993 if (PTR_ERR(adcx140->supply_areg) == -EPROBE_DEFER)
994 return -EPROBE_DEFER;
995
996 adcx140->supply_areg = NULL;
997 } else {
998 ret = regulator_enable(adcx140->supply_areg);
999 if (ret) {
1000 dev_err(adcx140->dev, "Failed to enable areg\n");
1001 return ret;
1002 }
1003 }
1004
1005 adcx140->regmap = devm_regmap_init_i2c(i2c, &adcx140_i2c_regmap);
1006 if (IS_ERR(adcx140->regmap)) {
1007 ret = PTR_ERR(adcx140->regmap);
1008 dev_err(&i2c->dev, "Failed to allocate register map: %d\n",
1009 ret);
1010 return ret;
1011 }
1012
1013 i2c_set_clientdata(i2c, adcx140);
1014
1015 return devm_snd_soc_register_component(&i2c->dev,
1016 &soc_codec_driver_adcx140,
1017 adcx140_dai_driver, 1);
1018}
1019
1020static const struct i2c_device_id adcx140_i2c_id[] = {
1021 { "tlv320adc3140", 0 },
1022 { "tlv320adc5140", 1 },
1023 { "tlv320adc6140", 2 },
1024 {}
1025};
1026MODULE_DEVICE_TABLE(i2c, adcx140_i2c_id);
1027
1028static struct i2c_driver adcx140_i2c_driver = {
1029 .driver = {
1030 .name = "tlv320adcx140-codec",
1031 .of_match_table = of_match_ptr(tlv320adcx140_of_match),
1032 },
1033 .probe = adcx140_i2c_probe,
1034 .id_table = adcx140_i2c_id,
1035};
1036module_i2c_driver(adcx140_i2c_driver);
1037
1038MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com>");
1039MODULE_DESCRIPTION("ASoC TLV320ADCX140 CODEC Driver");
1040MODULE_LICENSE("GPL v2");
1041
