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6#include <linux/init.h>
7#include <linux/io.h>
8#include <linux/of.h>
9#include <linux/of_device.h>
10#include <linux/kernel.h>
11#include <linux/module.h>
12#include <linux/platform_device.h>
13#include <linux/slab.h>
14
15#include <linux/clk.h>
16#include <linux/delay.h>
17
18#include <linux/dma-mapping.h>
19
20#include <sound/core.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/soc.h>
24#include <sound/initval.h>
25#include <sound/dmaengine_pcm.h>
26
27#include "jz4740-i2s.h"
28
29#define JZ4740_DMA_TYPE_AIC_TRANSMIT 24
30#define JZ4740_DMA_TYPE_AIC_RECEIVE 25
31
32#define JZ_REG_AIC_CONF 0x00
33#define JZ_REG_AIC_CTRL 0x04
34#define JZ_REG_AIC_I2S_FMT 0x10
35#define JZ_REG_AIC_FIFO_STATUS 0x14
36#define JZ_REG_AIC_I2S_STATUS 0x1c
37#define JZ_REG_AIC_CLK_DIV 0x30
38#define JZ_REG_AIC_FIFO 0x34
39
40#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_MASK (0xf << 12)
41#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_MASK (0xf << 8)
42#define JZ_AIC_CONF_OVERFLOW_PLAY_LAST BIT(6)
43#define JZ_AIC_CONF_INTERNAL_CODEC BIT(5)
44#define JZ_AIC_CONF_I2S BIT(4)
45#define JZ_AIC_CONF_RESET BIT(3)
46#define JZ_AIC_CONF_BIT_CLK_MASTER BIT(2)
47#define JZ_AIC_CONF_SYNC_CLK_MASTER BIT(1)
48#define JZ_AIC_CONF_ENABLE BIT(0)
49
50#define JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 12
51#define JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 8
52#define JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET 24
53#define JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET 16
54
55#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK (0x7 << 19)
56#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK (0x7 << 16)
57#define JZ_AIC_CTRL_ENABLE_RX_DMA BIT(15)
58#define JZ_AIC_CTRL_ENABLE_TX_DMA BIT(14)
59#define JZ_AIC_CTRL_MONO_TO_STEREO BIT(11)
60#define JZ_AIC_CTRL_SWITCH_ENDIANNESS BIT(10)
61#define JZ_AIC_CTRL_SIGNED_TO_UNSIGNED BIT(9)
62#define JZ_AIC_CTRL_FLUSH BIT(8)
63#define JZ_AIC_CTRL_ENABLE_ROR_INT BIT(6)
64#define JZ_AIC_CTRL_ENABLE_TUR_INT BIT(5)
65#define JZ_AIC_CTRL_ENABLE_RFS_INT BIT(4)
66#define JZ_AIC_CTRL_ENABLE_TFS_INT BIT(3)
67#define JZ_AIC_CTRL_ENABLE_LOOPBACK BIT(2)
68#define JZ_AIC_CTRL_ENABLE_PLAYBACK BIT(1)
69#define JZ_AIC_CTRL_ENABLE_CAPTURE BIT(0)
70
71#define JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET 19
72#define JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET 16
73
74#define JZ_AIC_I2S_FMT_DISABLE_BIT_CLK BIT(12)
75#define JZ_AIC_I2S_FMT_DISABLE_BIT_ICLK BIT(13)
76#define JZ_AIC_I2S_FMT_ENABLE_SYS_CLK BIT(4)
77#define JZ_AIC_I2S_FMT_MSB BIT(0)
78
79#define JZ_AIC_I2S_STATUS_BUSY BIT(2)
80
81#define JZ_AIC_CLK_DIV_MASK 0xf
82#define I2SDIV_DV_SHIFT 0
83#define I2SDIV_DV_MASK (0xf << I2SDIV_DV_SHIFT)
84#define I2SDIV_IDV_SHIFT 8
85#define I2SDIV_IDV_MASK (0xf << I2SDIV_IDV_SHIFT)
86
87enum jz47xx_i2s_version {
88 JZ_I2S_JZ4740,
89 JZ_I2S_JZ4760,
90 JZ_I2S_JZ4770,
91 JZ_I2S_JZ4780,
92};
93
94struct i2s_soc_info {
95 enum jz47xx_i2s_version version;
96 struct snd_soc_dai_driver *dai;
97};
98
99struct jz4740_i2s {
100 struct resource *mem;
101 void __iomem *base;
102 dma_addr_t phys_base;
103
104 struct clk *clk_aic;
105 struct clk *clk_i2s;
106
107 struct snd_dmaengine_dai_dma_data playback_dma_data;
108 struct snd_dmaengine_dai_dma_data capture_dma_data;
109
110 const struct i2s_soc_info *soc_info;
111};
112
113static inline uint32_t jz4740_i2s_read(const struct jz4740_i2s *i2s,
114 unsigned int reg)
115{
116 return readl(i2s->base + reg);
117}
118
119static inline void jz4740_i2s_write(const struct jz4740_i2s *i2s,
120 unsigned int reg, uint32_t value)
121{
122 writel(value, i2s->base + reg);
123}
124
125static int jz4740_i2s_startup(struct snd_pcm_substream *substream,
126 struct snd_soc_dai *dai)
127{
128 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
129 uint32_t conf, ctrl;
130 int ret;
131
132 if (snd_soc_dai_active(dai))
133 return 0;
134
135 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
136 ctrl |= JZ_AIC_CTRL_FLUSH;
137 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
138
139 ret = clk_prepare_enable(i2s->clk_i2s);
140 if (ret)
141 return ret;
142
143 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
144 conf |= JZ_AIC_CONF_ENABLE;
145 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
146
147 return 0;
148}
149
150static void jz4740_i2s_shutdown(struct snd_pcm_substream *substream,
151 struct snd_soc_dai *dai)
152{
153 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
154 uint32_t conf;
155
156 if (snd_soc_dai_active(dai))
157 return;
158
159 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
160 conf &= ~JZ_AIC_CONF_ENABLE;
161 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
162
163 clk_disable_unprepare(i2s->clk_i2s);
164}
165
166static int jz4740_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
167 struct snd_soc_dai *dai)
168{
169 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
170
171 uint32_t ctrl;
172 uint32_t mask;
173
174 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
175 mask = JZ_AIC_CTRL_ENABLE_PLAYBACK | JZ_AIC_CTRL_ENABLE_TX_DMA;
176 else
177 mask = JZ_AIC_CTRL_ENABLE_CAPTURE | JZ_AIC_CTRL_ENABLE_RX_DMA;
178
179 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
180
181 switch (cmd) {
182 case SNDRV_PCM_TRIGGER_START:
183 case SNDRV_PCM_TRIGGER_RESUME:
184 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
185 ctrl |= mask;
186 break;
187 case SNDRV_PCM_TRIGGER_STOP:
188 case SNDRV_PCM_TRIGGER_SUSPEND:
189 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
190 ctrl &= ~mask;
191 break;
192 default:
193 return -EINVAL;
194 }
195
196 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
197
198 return 0;
199}
200
201static int jz4740_i2s_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
202{
203 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
204
205 uint32_t format = 0;
206 uint32_t conf;
207
208 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
209
210 conf &= ~(JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER);
211
212 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
213 case SND_SOC_DAIFMT_CBS_CFS:
214 conf |= JZ_AIC_CONF_BIT_CLK_MASTER | JZ_AIC_CONF_SYNC_CLK_MASTER;
215 format |= JZ_AIC_I2S_FMT_ENABLE_SYS_CLK;
216 break;
217 case SND_SOC_DAIFMT_CBM_CFS:
218 conf |= JZ_AIC_CONF_SYNC_CLK_MASTER;
219 break;
220 case SND_SOC_DAIFMT_CBS_CFM:
221 conf |= JZ_AIC_CONF_BIT_CLK_MASTER;
222 break;
223 case SND_SOC_DAIFMT_CBM_CFM:
224 break;
225 default:
226 return -EINVAL;
227 }
228
229 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
230 case SND_SOC_DAIFMT_MSB:
231 format |= JZ_AIC_I2S_FMT_MSB;
232 break;
233 case SND_SOC_DAIFMT_I2S:
234 break;
235 default:
236 return -EINVAL;
237 }
238
239 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
240 case SND_SOC_DAIFMT_NB_NF:
241 break;
242 default:
243 return -EINVAL;
244 }
245
246 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
247 jz4740_i2s_write(i2s, JZ_REG_AIC_I2S_FMT, format);
248
249 return 0;
250}
251
252static int jz4740_i2s_hw_params(struct snd_pcm_substream *substream,
253 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
254{
255 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
256 unsigned int sample_size;
257 uint32_t ctrl, div_reg;
258 int div;
259
260 ctrl = jz4740_i2s_read(i2s, JZ_REG_AIC_CTRL);
261
262 div_reg = jz4740_i2s_read(i2s, JZ_REG_AIC_CLK_DIV);
263 div = clk_get_rate(i2s->clk_i2s) / (64 * params_rate(params));
264
265 switch (params_format(params)) {
266 case SNDRV_PCM_FORMAT_S8:
267 sample_size = 0;
268 break;
269 case SNDRV_PCM_FORMAT_S16:
270 sample_size = 1;
271 break;
272 default:
273 return -EINVAL;
274 }
275
276 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
277 ctrl &= ~JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_MASK;
278 ctrl |= sample_size << JZ_AIC_CTRL_OUTPUT_SAMPLE_SIZE_OFFSET;
279 if (params_channels(params) == 1)
280 ctrl |= JZ_AIC_CTRL_MONO_TO_STEREO;
281 else
282 ctrl &= ~JZ_AIC_CTRL_MONO_TO_STEREO;
283
284 div_reg &= ~I2SDIV_DV_MASK;
285 div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
286 } else {
287 ctrl &= ~JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_MASK;
288 ctrl |= sample_size << JZ_AIC_CTRL_INPUT_SAMPLE_SIZE_OFFSET;
289
290 if (i2s->soc_info->version >= JZ_I2S_JZ4770) {
291 div_reg &= ~I2SDIV_IDV_MASK;
292 div_reg |= (div - 1) << I2SDIV_IDV_SHIFT;
293 } else {
294 div_reg &= ~I2SDIV_DV_MASK;
295 div_reg |= (div - 1) << I2SDIV_DV_SHIFT;
296 }
297 }
298
299 jz4740_i2s_write(i2s, JZ_REG_AIC_CTRL, ctrl);
300 jz4740_i2s_write(i2s, JZ_REG_AIC_CLK_DIV, div_reg);
301
302 return 0;
303}
304
305static int jz4740_i2s_set_sysclk(struct snd_soc_dai *dai, int clk_id,
306 unsigned int freq, int dir)
307{
308 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
309 struct clk *parent;
310 int ret = 0;
311
312 switch (clk_id) {
313 case JZ4740_I2S_CLKSRC_EXT:
314 parent = clk_get(NULL, "ext");
315 clk_set_parent(i2s->clk_i2s, parent);
316 break;
317 case JZ4740_I2S_CLKSRC_PLL:
318 parent = clk_get(NULL, "pll half");
319 clk_set_parent(i2s->clk_i2s, parent);
320 ret = clk_set_rate(i2s->clk_i2s, freq);
321 break;
322 default:
323 return -EINVAL;
324 }
325 clk_put(parent);
326
327 return ret;
328}
329
330static int jz4740_i2s_suspend(struct snd_soc_component *component)
331{
332 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
333 uint32_t conf;
334
335 if (snd_soc_component_active(component)) {
336 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
337 conf &= ~JZ_AIC_CONF_ENABLE;
338 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
339
340 clk_disable_unprepare(i2s->clk_i2s);
341 }
342
343 clk_disable_unprepare(i2s->clk_aic);
344
345 return 0;
346}
347
348static int jz4740_i2s_resume(struct snd_soc_component *component)
349{
350 struct jz4740_i2s *i2s = snd_soc_component_get_drvdata(component);
351 uint32_t conf;
352 int ret;
353
354 ret = clk_prepare_enable(i2s->clk_aic);
355 if (ret)
356 return ret;
357
358 if (snd_soc_component_active(component)) {
359 ret = clk_prepare_enable(i2s->clk_i2s);
360 if (ret) {
361 clk_disable_unprepare(i2s->clk_aic);
362 return ret;
363 }
364
365 conf = jz4740_i2s_read(i2s, JZ_REG_AIC_CONF);
366 conf |= JZ_AIC_CONF_ENABLE;
367 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
368 }
369
370 return 0;
371}
372
373static void jz4740_i2c_init_pcm_config(struct jz4740_i2s *i2s)
374{
375 struct snd_dmaengine_dai_dma_data *dma_data;
376
377
378 dma_data = &i2s->playback_dma_data;
379 dma_data->maxburst = 16;
380 dma_data->slave_id = JZ4740_DMA_TYPE_AIC_TRANSMIT;
381 dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
382
383
384 dma_data = &i2s->capture_dma_data;
385 dma_data->maxburst = 16;
386 dma_data->slave_id = JZ4740_DMA_TYPE_AIC_RECEIVE;
387 dma_data->addr = i2s->phys_base + JZ_REG_AIC_FIFO;
388}
389
390static int jz4740_i2s_dai_probe(struct snd_soc_dai *dai)
391{
392 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
393 uint32_t conf;
394 int ret;
395
396 ret = clk_prepare_enable(i2s->clk_aic);
397 if (ret)
398 return ret;
399
400 jz4740_i2c_init_pcm_config(i2s);
401 snd_soc_dai_init_dma_data(dai, &i2s->playback_dma_data,
402 &i2s->capture_dma_data);
403
404 if (i2s->soc_info->version >= JZ_I2S_JZ4760) {
405 conf = (7 << JZ4760_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
406 (8 << JZ4760_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
407 JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
408 JZ_AIC_CONF_I2S |
409 JZ_AIC_CONF_INTERNAL_CODEC;
410 } else {
411 conf = (7 << JZ_AIC_CONF_FIFO_RX_THRESHOLD_OFFSET) |
412 (8 << JZ_AIC_CONF_FIFO_TX_THRESHOLD_OFFSET) |
413 JZ_AIC_CONF_OVERFLOW_PLAY_LAST |
414 JZ_AIC_CONF_I2S |
415 JZ_AIC_CONF_INTERNAL_CODEC;
416 }
417
418 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, JZ_AIC_CONF_RESET);
419 jz4740_i2s_write(i2s, JZ_REG_AIC_CONF, conf);
420
421 return 0;
422}
423
424static int jz4740_i2s_dai_remove(struct snd_soc_dai *dai)
425{
426 struct jz4740_i2s *i2s = snd_soc_dai_get_drvdata(dai);
427
428 clk_disable_unprepare(i2s->clk_aic);
429 return 0;
430}
431
432static const struct snd_soc_dai_ops jz4740_i2s_dai_ops = {
433 .startup = jz4740_i2s_startup,
434 .shutdown = jz4740_i2s_shutdown,
435 .trigger = jz4740_i2s_trigger,
436 .hw_params = jz4740_i2s_hw_params,
437 .set_fmt = jz4740_i2s_set_fmt,
438 .set_sysclk = jz4740_i2s_set_sysclk,
439};
440
441#define JZ4740_I2S_FMTS (SNDRV_PCM_FMTBIT_S8 | \
442 SNDRV_PCM_FMTBIT_S16_LE)
443
444static struct snd_soc_dai_driver jz4740_i2s_dai = {
445 .probe = jz4740_i2s_dai_probe,
446 .remove = jz4740_i2s_dai_remove,
447 .playback = {
448 .channels_min = 1,
449 .channels_max = 2,
450 .rates = SNDRV_PCM_RATE_8000_48000,
451 .formats = JZ4740_I2S_FMTS,
452 },
453 .capture = {
454 .channels_min = 2,
455 .channels_max = 2,
456 .rates = SNDRV_PCM_RATE_8000_48000,
457 .formats = JZ4740_I2S_FMTS,
458 },
459 .symmetric_rates = 1,
460 .ops = &jz4740_i2s_dai_ops,
461};
462
463static const struct i2s_soc_info jz4740_i2s_soc_info = {
464 .version = JZ_I2S_JZ4740,
465 .dai = &jz4740_i2s_dai,
466};
467
468static const struct i2s_soc_info jz4760_i2s_soc_info = {
469 .version = JZ_I2S_JZ4760,
470 .dai = &jz4740_i2s_dai,
471};
472
473static struct snd_soc_dai_driver jz4770_i2s_dai = {
474 .probe = jz4740_i2s_dai_probe,
475 .remove = jz4740_i2s_dai_remove,
476 .playback = {
477 .channels_min = 1,
478 .channels_max = 2,
479 .rates = SNDRV_PCM_RATE_8000_48000,
480 .formats = JZ4740_I2S_FMTS,
481 },
482 .capture = {
483 .channels_min = 2,
484 .channels_max = 2,
485 .rates = SNDRV_PCM_RATE_8000_48000,
486 .formats = JZ4740_I2S_FMTS,
487 },
488 .ops = &jz4740_i2s_dai_ops,
489};
490
491static const struct i2s_soc_info jz4770_i2s_soc_info = {
492 .version = JZ_I2S_JZ4770,
493 .dai = &jz4770_i2s_dai,
494};
495
496static const struct i2s_soc_info jz4780_i2s_soc_info = {
497 .version = JZ_I2S_JZ4780,
498 .dai = &jz4770_i2s_dai,
499};
500
501static const struct snd_soc_component_driver jz4740_i2s_component = {
502 .name = "jz4740-i2s",
503 .suspend = jz4740_i2s_suspend,
504 .resume = jz4740_i2s_resume,
505};
506
507static const struct of_device_id jz4740_of_matches[] = {
508 { .compatible = "ingenic,jz4740-i2s", .data = &jz4740_i2s_soc_info },
509 { .compatible = "ingenic,jz4760-i2s", .data = &jz4760_i2s_soc_info },
510 { .compatible = "ingenic,jz4770-i2s", .data = &jz4770_i2s_soc_info },
511 { .compatible = "ingenic,jz4780-i2s", .data = &jz4780_i2s_soc_info },
512 { }
513};
514MODULE_DEVICE_TABLE(of, jz4740_of_matches);
515
516static int jz4740_i2s_dev_probe(struct platform_device *pdev)
517{
518 struct device *dev = &pdev->dev;
519 struct jz4740_i2s *i2s;
520 struct resource *mem;
521 int ret;
522
523 i2s = devm_kzalloc(dev, sizeof(*i2s), GFP_KERNEL);
524 if (!i2s)
525 return -ENOMEM;
526
527 i2s->soc_info = device_get_match_data(dev);
528
529 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
530 i2s->base = devm_ioremap_resource(dev, mem);
531 if (IS_ERR(i2s->base))
532 return PTR_ERR(i2s->base);
533
534 i2s->phys_base = mem->start;
535
536 i2s->clk_aic = devm_clk_get(dev, "aic");
537 if (IS_ERR(i2s->clk_aic))
538 return PTR_ERR(i2s->clk_aic);
539
540 i2s->clk_i2s = devm_clk_get(dev, "i2s");
541 if (IS_ERR(i2s->clk_i2s))
542 return PTR_ERR(i2s->clk_i2s);
543
544 platform_set_drvdata(pdev, i2s);
545
546 ret = devm_snd_soc_register_component(dev, &jz4740_i2s_component,
547 i2s->soc_info->dai, 1);
548 if (ret)
549 return ret;
550
551 return devm_snd_dmaengine_pcm_register(dev, NULL,
552 SND_DMAENGINE_PCM_FLAG_COMPAT);
553}
554
555static struct platform_driver jz4740_i2s_driver = {
556 .probe = jz4740_i2s_dev_probe,
557 .driver = {
558 .name = "jz4740-i2s",
559 .of_match_table = jz4740_of_matches,
560 },
561};
562
563module_platform_driver(jz4740_i2s_driver);
564
565MODULE_AUTHOR("Lars-Peter Clausen, <lars@metafoo.de>");
566MODULE_DESCRIPTION("Ingenic JZ4740 SoC I2S driver");
567MODULE_LICENSE("GPL");
568MODULE_ALIAS("platform:jz4740-i2s");
569
