1
2
3
4
5
6
7
8
9
10
11
12#include <linux/clk.h>
13#include <linux/delay.h>
14#include <linux/device.h>
15#include <linux/gpio.h>
16#include <linux/io.h>
17#include <linux/jiffies.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_gpio.h>
21#include <linux/platform_device.h>
22#include <linux/pm_runtime.h>
23#include <linux/regmap.h>
24#include <linux/slab.h>
25#include <sound/core.h>
26#include <sound/pcm.h>
27#include <sound/pcm_params.h>
28#include <sound/soc.h>
29#include <sound/dmaengine_pcm.h>
30
31#include "tegra20_ac97.h"
32
33#define DRV_NAME "tegra20-ac97"
34
35static struct tegra20_ac97 *workdata;
36
37static void tegra20_ac97_codec_reset(struct snd_ac97 *ac97)
38{
39 u32 readback;
40 unsigned long timeout;
41
42
43 gpio_set_value(workdata->reset_gpio, 0);
44 udelay(2);
45
46 gpio_set_value(workdata->reset_gpio, 1);
47 udelay(2);
48
49 timeout = jiffies + msecs_to_jiffies(100);
50
51 do {
52 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
53 if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
54 break;
55 usleep_range(1000, 2000);
56 } while (!time_after(jiffies, timeout));
57}
58
59static void tegra20_ac97_codec_warm_reset(struct snd_ac97 *ac97)
60{
61 u32 readback;
62 unsigned long timeout;
63
64
65
66
67
68
69 gpio_request(workdata->sync_gpio, "codec-sync");
70
71 gpio_direction_output(workdata->sync_gpio, 1);
72
73 udelay(2);
74 gpio_set_value(workdata->sync_gpio, 0);
75 udelay(2);
76 gpio_free(workdata->sync_gpio);
77
78 timeout = jiffies + msecs_to_jiffies(100);
79
80 do {
81 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
82 if (readback & TEGRA20_AC97_STATUS1_CODEC1_RDY)
83 break;
84 usleep_range(1000, 2000);
85 } while (!time_after(jiffies, timeout));
86}
87
88static unsigned short tegra20_ac97_codec_read(struct snd_ac97 *ac97_snd,
89 unsigned short reg)
90{
91 u32 readback;
92 unsigned long timeout;
93
94 regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
95 (((reg | 0x80) << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
96 TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
97 TEGRA20_AC97_CMD_BUSY);
98
99 timeout = jiffies + msecs_to_jiffies(100);
100
101 do {
102 regmap_read(workdata->regmap, TEGRA20_AC97_STATUS1, &readback);
103 if (readback & TEGRA20_AC97_STATUS1_STA_VALID1)
104 break;
105 usleep_range(1000, 2000);
106 } while (!time_after(jiffies, timeout));
107
108 return ((readback & TEGRA20_AC97_STATUS1_STA_DATA1_MASK) >>
109 TEGRA20_AC97_STATUS1_STA_DATA1_SHIFT);
110}
111
112static void tegra20_ac97_codec_write(struct snd_ac97 *ac97_snd,
113 unsigned short reg, unsigned short val)
114{
115 u32 readback;
116 unsigned long timeout;
117
118 regmap_write(workdata->regmap, TEGRA20_AC97_CMD,
119 ((reg << TEGRA20_AC97_CMD_CMD_ADDR_SHIFT) &
120 TEGRA20_AC97_CMD_CMD_ADDR_MASK) |
121 ((val << TEGRA20_AC97_CMD_CMD_DATA_SHIFT) &
122 TEGRA20_AC97_CMD_CMD_DATA_MASK) |
123 TEGRA20_AC97_CMD_BUSY);
124
125 timeout = jiffies + msecs_to_jiffies(100);
126
127 do {
128 regmap_read(workdata->regmap, TEGRA20_AC97_CMD, &readback);
129 if (!(readback & TEGRA20_AC97_CMD_BUSY))
130 break;
131 usleep_range(1000, 2000);
132 } while (!time_after(jiffies, timeout));
133}
134
135static struct snd_ac97_bus_ops tegra20_ac97_ops = {
136 .read = tegra20_ac97_codec_read,
137 .write = tegra20_ac97_codec_write,
138 .reset = tegra20_ac97_codec_reset,
139 .warm_reset = tegra20_ac97_codec_warm_reset,
140};
141
142static inline void tegra20_ac97_start_playback(struct tegra20_ac97 *ac97)
143{
144 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
145 TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN,
146 TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN);
147
148 regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
149 TEGRA20_AC97_CTRL_PCM_DAC_EN |
150 TEGRA20_AC97_CTRL_STM_EN,
151 TEGRA20_AC97_CTRL_PCM_DAC_EN |
152 TEGRA20_AC97_CTRL_STM_EN);
153}
154
155static inline void tegra20_ac97_stop_playback(struct tegra20_ac97 *ac97)
156{
157 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
158 TEGRA20_AC97_FIFO_SCR_PB_QRT_MT_EN, 0);
159
160 regmap_update_bits(ac97->regmap, TEGRA20_AC97_CTRL,
161 TEGRA20_AC97_CTRL_PCM_DAC_EN, 0);
162}
163
164static inline void tegra20_ac97_start_capture(struct tegra20_ac97 *ac97)
165{
166 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
167 TEGRA20_AC97_FIFO_SCR_REC_FULL_EN,
168 TEGRA20_AC97_FIFO_SCR_REC_FULL_EN);
169}
170
171static inline void tegra20_ac97_stop_capture(struct tegra20_ac97 *ac97)
172{
173 regmap_update_bits(ac97->regmap, TEGRA20_AC97_FIFO1_SCR,
174 TEGRA20_AC97_FIFO_SCR_REC_FULL_EN, 0);
175}
176
177static int tegra20_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
178 struct snd_soc_dai *dai)
179{
180 struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
181
182 switch (cmd) {
183 case SNDRV_PCM_TRIGGER_START:
184 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
185 case SNDRV_PCM_TRIGGER_RESUME:
186 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
187 tegra20_ac97_start_playback(ac97);
188 else
189 tegra20_ac97_start_capture(ac97);
190 break;
191 case SNDRV_PCM_TRIGGER_STOP:
192 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
193 case SNDRV_PCM_TRIGGER_SUSPEND:
194 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
195 tegra20_ac97_stop_playback(ac97);
196 else
197 tegra20_ac97_stop_capture(ac97);
198 break;
199 default:
200 return -EINVAL;
201 }
202
203 return 0;
204}
205
206static const struct snd_soc_dai_ops tegra20_ac97_dai_ops = {
207 .trigger = tegra20_ac97_trigger,
208};
209
210static int tegra20_ac97_probe(struct snd_soc_dai *dai)
211{
212 struct tegra20_ac97 *ac97 = snd_soc_dai_get_drvdata(dai);
213
214 dai->capture_dma_data = &ac97->capture_dma_data;
215 dai->playback_dma_data = &ac97->playback_dma_data;
216
217 return 0;
218}
219
220static struct snd_soc_dai_driver tegra20_ac97_dai = {
221 .name = "tegra-ac97-pcm",
222 .probe = tegra20_ac97_probe,
223 .playback = {
224 .stream_name = "PCM Playback",
225 .channels_min = 2,
226 .channels_max = 2,
227 .rates = SNDRV_PCM_RATE_8000_48000,
228 .formats = SNDRV_PCM_FMTBIT_S16_LE,
229 },
230 .capture = {
231 .stream_name = "PCM Capture",
232 .channels_min = 2,
233 .channels_max = 2,
234 .rates = SNDRV_PCM_RATE_8000_48000,
235 .formats = SNDRV_PCM_FMTBIT_S16_LE,
236 },
237 .ops = &tegra20_ac97_dai_ops,
238};
239
240static const struct snd_soc_component_driver tegra20_ac97_component = {
241 .name = DRV_NAME,
242};
243
244static bool tegra20_ac97_wr_rd_reg(struct device *dev, unsigned int reg)
245{
246 switch (reg) {
247 case TEGRA20_AC97_CTRL:
248 case TEGRA20_AC97_CMD:
249 case TEGRA20_AC97_STATUS1:
250 case TEGRA20_AC97_FIFO1_SCR:
251 case TEGRA20_AC97_FIFO_TX1:
252 case TEGRA20_AC97_FIFO_RX1:
253 return true;
254 default:
255 break;
256 }
257
258 return false;
259}
260
261static bool tegra20_ac97_volatile_reg(struct device *dev, unsigned int reg)
262{
263 switch (reg) {
264 case TEGRA20_AC97_STATUS1:
265 case TEGRA20_AC97_FIFO1_SCR:
266 case TEGRA20_AC97_FIFO_TX1:
267 case TEGRA20_AC97_FIFO_RX1:
268 return true;
269 default:
270 break;
271 }
272
273 return false;
274}
275
276static bool tegra20_ac97_precious_reg(struct device *dev, unsigned int reg)
277{
278 switch (reg) {
279 case TEGRA20_AC97_FIFO_TX1:
280 case TEGRA20_AC97_FIFO_RX1:
281 return true;
282 default:
283 break;
284 }
285
286 return false;
287}
288
289static const struct regmap_config tegra20_ac97_regmap_config = {
290 .reg_bits = 32,
291 .reg_stride = 4,
292 .val_bits = 32,
293 .max_register = TEGRA20_AC97_FIFO_RX1,
294 .writeable_reg = tegra20_ac97_wr_rd_reg,
295 .readable_reg = tegra20_ac97_wr_rd_reg,
296 .volatile_reg = tegra20_ac97_volatile_reg,
297 .precious_reg = tegra20_ac97_precious_reg,
298 .cache_type = REGCACHE_FLAT,
299};
300
301static int tegra20_ac97_platform_probe(struct platform_device *pdev)
302{
303 struct tegra20_ac97 *ac97;
304 struct resource *mem;
305 void __iomem *regs;
306 int ret = 0;
307
308 ac97 = devm_kzalloc(&pdev->dev, sizeof(struct tegra20_ac97),
309 GFP_KERNEL);
310 if (!ac97) {
311 ret = -ENOMEM;
312 goto err;
313 }
314 dev_set_drvdata(&pdev->dev, ac97);
315
316 ac97->clk_ac97 = devm_clk_get(&pdev->dev, NULL);
317 if (IS_ERR(ac97->clk_ac97)) {
318 dev_err(&pdev->dev, "Can't retrieve ac97 clock\n");
319 ret = PTR_ERR(ac97->clk_ac97);
320 goto err;
321 }
322
323 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
324 regs = devm_ioremap_resource(&pdev->dev, mem);
325 if (IS_ERR(regs)) {
326 ret = PTR_ERR(regs);
327 goto err_clk_put;
328 }
329
330 ac97->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
331 &tegra20_ac97_regmap_config);
332 if (IS_ERR(ac97->regmap)) {
333 dev_err(&pdev->dev, "regmap init failed\n");
334 ret = PTR_ERR(ac97->regmap);
335 goto err_clk_put;
336 }
337
338 ac97->reset_gpio = of_get_named_gpio(pdev->dev.of_node,
339 "nvidia,codec-reset-gpio", 0);
340 if (gpio_is_valid(ac97->reset_gpio)) {
341 ret = devm_gpio_request_one(&pdev->dev, ac97->reset_gpio,
342 GPIOF_OUT_INIT_HIGH, "codec-reset");
343 if (ret) {
344 dev_err(&pdev->dev, "could not get codec-reset GPIO\n");
345 goto err_clk_put;
346 }
347 } else {
348 dev_err(&pdev->dev, "no codec-reset GPIO supplied\n");
349 goto err_clk_put;
350 }
351
352 ac97->sync_gpio = of_get_named_gpio(pdev->dev.of_node,
353 "nvidia,codec-sync-gpio", 0);
354 if (!gpio_is_valid(ac97->sync_gpio)) {
355 dev_err(&pdev->dev, "no codec-sync GPIO supplied\n");
356 goto err_clk_put;
357 }
358
359 ac97->capture_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_RX1;
360 ac97->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
361 ac97->capture_dma_data.maxburst = 4;
362
363 ac97->playback_dma_data.addr = mem->start + TEGRA20_AC97_FIFO_TX1;
364 ac97->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
365 ac97->playback_dma_data.maxburst = 4;
366
367 ret = clk_prepare_enable(ac97->clk_ac97);
368 if (ret) {
369 dev_err(&pdev->dev, "clk_enable failed: %d\n", ret);
370 goto err_clk_put;
371 }
372
373 ret = snd_soc_set_ac97_ops(&tegra20_ac97_ops);
374 if (ret) {
375 dev_err(&pdev->dev, "Failed to set AC'97 ops: %d\n", ret);
376 goto err_clk_disable_unprepare;
377 }
378
379 ret = snd_soc_register_component(&pdev->dev, &tegra20_ac97_component,
380 &tegra20_ac97_dai, 1);
381 if (ret) {
382 dev_err(&pdev->dev, "Could not register DAI: %d\n", ret);
383 ret = -ENOMEM;
384 goto err_clk_disable_unprepare;
385 }
386
387 ret = tegra_pcm_platform_register(&pdev->dev);
388 if (ret) {
389 dev_err(&pdev->dev, "Could not register PCM: %d\n", ret);
390 goto err_unregister_component;
391 }
392
393
394 workdata = ac97;
395
396 return 0;
397
398err_unregister_component:
399 snd_soc_unregister_component(&pdev->dev);
400err_clk_disable_unprepare:
401 clk_disable_unprepare(ac97->clk_ac97);
402err_clk_put:
403err:
404 snd_soc_set_ac97_ops(NULL);
405 return ret;
406}
407
408static int tegra20_ac97_platform_remove(struct platform_device *pdev)
409{
410 struct tegra20_ac97 *ac97 = dev_get_drvdata(&pdev->dev);
411
412 tegra_pcm_platform_unregister(&pdev->dev);
413 snd_soc_unregister_component(&pdev->dev);
414
415 clk_disable_unprepare(ac97->clk_ac97);
416
417 snd_soc_set_ac97_ops(NULL);
418
419 return 0;
420}
421
422static const struct of_device_id tegra20_ac97_of_match[] = {
423 { .compatible = "nvidia,tegra20-ac97", },
424 {},
425};
426
427static struct platform_driver tegra20_ac97_driver = {
428 .driver = {
429 .name = DRV_NAME,
430 .of_match_table = tegra20_ac97_of_match,
431 },
432 .probe = tegra20_ac97_platform_probe,
433 .remove = tegra20_ac97_platform_remove,
434};
435module_platform_driver(tegra20_ac97_driver);
436
437MODULE_AUTHOR("Lucas Stach");
438MODULE_DESCRIPTION("Tegra20 AC97 ASoC driver");
439MODULE_LICENSE("GPL v2");
440MODULE_ALIAS("platform:" DRV_NAME);
441MODULE_DEVICE_TABLE(of, tegra20_ac97_of_match);
442
