1 DMA attributes 2 ============== 3 4This document describes the semantics of the DMA attributes that are 5defined in linux/dma-attrs.h. 6 7DMA_ATTR_WRITE_BARRIER 8---------------------- 9 10DMA_ATTR_WRITE_BARRIER is a (write) barrier attribute for DMA. DMA 11to a memory region with the DMA_ATTR_WRITE_BARRIER attribute forces 12all pending DMA writes to complete, and thus provides a mechanism to 13strictly order DMA from a device across all intervening busses and 14bridges. This barrier is not specific to a particular type of 15interconnect, it applies to the system as a whole, and so its 16implementation must account for the idiosyncrasies of the system all 17the way from the DMA device to memory. 18 19As an example of a situation where DMA_ATTR_WRITE_BARRIER would be 20useful, suppose that a device does a DMA write to indicate that data is 21ready and available in memory. The DMA of the "completion indication" 22could race with data DMA. Mapping the memory used for completion 23indications with DMA_ATTR_WRITE_BARRIER would prevent the race. 24 25DMA_ATTR_WEAK_ORDERING 26---------------------- 27 28DMA_ATTR_WEAK_ORDERING specifies that reads and writes to the mapping 29may be weakly ordered, that is that reads and writes may pass each other. 30 31Since it is optional for platforms to implement DMA_ATTR_WEAK_ORDERING, 32those that do not will simply ignore the attribute and exhibit default 33behavior. 34 35DMA_ATTR_WRITE_COMBINE 36---------------------- 37 38DMA_ATTR_WRITE_COMBINE specifies that writes to the mapping may be 39buffered to improve performance. 40 41Since it is optional for platforms to implement DMA_ATTR_WRITE_COMBINE, 42those that do not will simply ignore the attribute and exhibit default 43behavior. 44 45DMA_ATTR_NON_CONSISTENT 46----------------------- 47 48DMA_ATTR_NON_CONSISTENT lets the platform to choose to return either 49consistent or non-consistent memory as it sees fit. By using this API, 50you are guaranteeing to the platform that you have all the correct and 51necessary sync points for this memory in the driver. 52 53DMA_ATTR_NO_KERNEL_MAPPING 54-------------------------- 55 56DMA_ATTR_NO_KERNEL_MAPPING lets the platform to avoid creating a kernel 57virtual mapping for the allocated buffer. On some architectures creating 58such mapping is non-trivial task and consumes very limited resources 59(like kernel virtual address space or dma consistent address space). 60Buffers allocated with this attribute can be only passed to user space 61by calling dma_mmap_attrs(). By using this API, you are guaranteeing 62that you won't dereference the pointer returned by dma_alloc_attr(). You 63can treat it as a cookie that must be passed to dma_mmap_attrs() and 64dma_free_attrs(). Make sure that both of these also get this attribute 65set on each call. 66 67Since it is optional for platforms to implement 68DMA_ATTR_NO_KERNEL_MAPPING, those that do not will simply ignore the 69attribute and exhibit default behavior. 70 71DMA_ATTR_SKIP_CPU_SYNC 72---------------------- 73 74By default dma_map_{single,page,sg} functions family transfer a given 75buffer from CPU domain to device domain. Some advanced use cases might 76require sharing a buffer between more than one device. This requires 77having a mapping created separately for each device and is usually 78performed by calling dma_map_{single,page,sg} function more than once 79for the given buffer with device pointer to each device taking part in 80the buffer sharing. The first call transfers a buffer from 'CPU' domain 81to 'device' domain, what synchronizes CPU caches for the given region 82(usually it means that the cache has been flushed or invalidated 83depending on the dma direction). However, next calls to 84dma_map_{single,page,sg}() for other devices will perform exactly the 85same synchronization operation on the CPU cache. CPU cache synchronization 86might be a time consuming operation, especially if the buffers are 87large, so it is highly recommended to avoid it if possible. 88DMA_ATTR_SKIP_CPU_SYNC allows platform code to skip synchronization of 89the CPU cache for the given buffer assuming that it has been already 90transferred to 'device' domain. This attribute can be also used for 91dma_unmap_{single,page,sg} functions family to force buffer to stay in 92device domain after releasing a mapping for it. Use this attribute with 93care! 94 95DMA_ATTR_FORCE_CONTIGUOUS 96------------------------- 97 98By default DMA-mapping subsystem is allowed to assemble the buffer 99allocated by dma_alloc_attrs() function from individual pages if it can 100be mapped as contiguous chunk into device dma address space. By 101specifying this attribute the allocated buffer is forced to be contiguous 102also in physical memory. 103 104DMA_ATTR_ALLOC_SINGLE_PAGES 105--------------------------- 106 107This is a hint to the DMA-mapping subsystem that it's probably not worth 108the time to try to allocate memory to in a way that gives better TLB 109efficiency (AKA it's not worth trying to build the mapping out of larger 110pages). You might want to specify this if: 111- You know that the accesses to this memory won't thrash the TLB. 112 You might know that the accesses are likely to be sequential or 113 that they aren't sequential but it's unlikely you'll ping-pong 114 between many addresses that are likely to be in different physical 115 pages. 116- You know that the penalty of TLB misses while accessing the 117 memory will be small enough to be inconsequential. If you are 118 doing a heavy operation like decryption or decompression this 119 might be the case. 120- You know that the DMA mapping is fairly transitory. If you expect 121 the mapping to have a short lifetime then it may be worth it to 122 optimize allocation (avoid coming up with large pages) instead of 123 getting the slight performance win of larger pages. 124Setting this hint doesn't guarantee that you won't get huge pages, but it 125means that we won't try quite as hard to get them. 126 127NOTE: At the moment DMA_ATTR_ALLOC_SINGLE_PAGES is only implemented on ARM, 128though ARM64 patches will likely be posted soon. 129