1#ifndef __ALPHA_MCE_H 2#define __ALPHA_MCE_H 3 4/* 5 * This is the logout header that should be common to all platforms 6 * (assuming they are running OSF/1 PALcode, I guess). 7 */ 8struct el_common { 9 unsigned int size; /* size in bytes of logout area */ 10 unsigned int sbz1 : 30; /* should be zero */ 11 unsigned int err2 : 1; /* second error */ 12 unsigned int retry : 1; /* retry flag */ 13 unsigned int proc_offset; /* processor-specific offset */ 14 unsigned int sys_offset; /* system-specific offset */ 15 unsigned int code; /* machine check code */ 16 unsigned int frame_rev; /* frame revision */ 17}; 18 19/* Machine Check Frame for uncorrectable errors (Large format) 20 * --- This is used to log uncorrectable errors such as 21 * double bit ECC errors. 22 * --- These errors are detected by both processor and systems. 23 */ 24struct el_common_EV5_uncorrectable_mcheck { 25 unsigned long shadow[8]; /* Shadow reg. 8-14, 25 */ 26 unsigned long paltemp[24]; /* PAL TEMP REGS. */ 27 unsigned long exc_addr; /* Address of excepting instruction*/ 28 unsigned long exc_sum; /* Summary of arithmetic traps. */ 29 unsigned long exc_mask; /* Exception mask (from exc_sum). */ 30 unsigned long pal_base; /* Base address for PALcode. */ 31 unsigned long isr; /* Interrupt Status Reg. */ 32 unsigned long icsr; /* CURRENT SETUP OF EV5 IBOX */ 33 unsigned long ic_perr_stat; /* I-CACHE Reg. <11> set Data parity 34 <12> set TAG parity*/ 35 unsigned long dc_perr_stat; /* D-CACHE error Reg. Bits set to 1: 36 <2> Data error in bank 0 37 <3> Data error in bank 1 38 <4> Tag error in bank 0 39 <5> Tag error in bank 1 */ 40 unsigned long va; /* Effective VA of fault or miss. */ 41 unsigned long mm_stat; /* Holds the reason for D-stream 42 fault or D-cache parity errors */ 43 unsigned long sc_addr; /* Address that was being accessed 44 when EV5 detected Secondary cache 45 failure. */ 46 unsigned long sc_stat; /* Helps determine if the error was 47 TAG/Data parity(Secondary Cache)*/ 48 unsigned long bc_tag_addr; /* Contents of EV5 BC_TAG_ADDR */ 49 unsigned long ei_addr; /* Physical address of any transfer 50 that is logged in EV5 EI_STAT */ 51 unsigned long fill_syndrome; /* For correcting ECC errors. */ 52 unsigned long ei_stat; /* Helps identify reason of any 53 processor uncorrectable error 54 at its external interface. */ 55 unsigned long ld_lock; /* Contents of EV5 LD_LOCK register*/ 56}; 57 58struct el_common_EV6_mcheck { 59 unsigned int FrameSize; /* Bytes, including this field */ 60 unsigned int FrameFlags; /* <31> = Retry, <30> = Second Error */ 61 unsigned int CpuOffset; /* Offset to CPU-specific info */ 62 unsigned int SystemOffset; /* Offset to system-specific info */ 63 unsigned int MCHK_Code; 64 unsigned int MCHK_Frame_Rev; 65 unsigned long I_STAT; /* EV6 Internal Processor Registers */ 66 unsigned long DC_STAT; /* (See the 21264 Spec) */ 67 unsigned long C_ADDR; 68 unsigned long DC1_SYNDROME; 69 unsigned long DC0_SYNDROME; 70 unsigned long C_STAT; 71 unsigned long C_STS; 72 unsigned long MM_STAT; 73 unsigned long EXC_ADDR; 74 unsigned long IER_CM; 75 unsigned long ISUM; 76 unsigned long RESERVED0; 77 unsigned long PAL_BASE; 78 unsigned long I_CTL; 79 unsigned long PCTX; 80}; 81 82 83#endif /* __ALPHA_MCE_H */ 84