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13#include <linux/gpio.h>
14#include <linux/suspend.h>
15#include <linux/sched.h>
16#include <linux/proc_fs.h>
17#include <linux/genalloc.h>
18#include <linux/interrupt.h>
19#include <linux/sysfs.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_platform.h>
23#include <linux/of_address.h>
24#include <linux/platform_device.h>
25#include <linux/io.h>
26#include <linux/clk/at91_pmc.h>
27
28#include <asm/irq.h>
29#include <linux/atomic.h>
30#include <asm/mach/time.h>
31#include <asm/mach/irq.h>
32#include <asm/fncpy.h>
33#include <asm/cacheflush.h>
34#include <asm/system_misc.h>
35
36#include "generic.h"
37#include "pm.h"
38
39static void __iomem *pmc;
40
41
42
43
44
45
46
47#ifdef CONFIG_PINCTRL_AT91
48extern void at91_pinctrl_gpio_suspend(void);
49extern void at91_pinctrl_gpio_resume(void);
50#endif
51
52static struct {
53 unsigned long uhp_udp_mask;
54 int memctrl;
55} at91_pm_data;
56
57void __iomem *at91_ramc_base[2];
58
59static int at91_pm_valid_state(suspend_state_t state)
60{
61 switch (state) {
62 case PM_SUSPEND_ON:
63 case PM_SUSPEND_STANDBY:
64 case PM_SUSPEND_MEM:
65 return 1;
66
67 default:
68 return 0;
69 }
70}
71
72
73static suspend_state_t target_state;
74
75
76
77
78static int at91_pm_begin(suspend_state_t state)
79{
80 target_state = state;
81 return 0;
82}
83
84
85
86
87
88static int at91_pm_verify_clocks(void)
89{
90 unsigned long scsr;
91 int i;
92
93 scsr = readl(pmc + AT91_PMC_SCSR);
94
95
96 if ((scsr & at91_pm_data.uhp_udp_mask) != 0) {
97 pr_err("AT91: PM - Suspend-to-RAM with USB still active\n");
98 return 0;
99 }
100
101
102 for (i = 0; i < 4; i++) {
103 u32 css;
104
105 if ((scsr & (AT91_PMC_PCK0 << i)) == 0)
106 continue;
107 css = readl(pmc + AT91_PMC_PCKR(i)) & AT91_PMC_CSS;
108 if (css != AT91_PMC_CSS_SLOW) {
109 pr_err("AT91: PM - Suspend-to-RAM with PCK%d src %d\n", i, css);
110 return 0;
111 }
112 }
113
114 return 1;
115}
116
117
118
119
120
121
122
123
124
125
126
127int at91_suspend_entering_slow_clock(void)
128{
129 return (target_state == PM_SUSPEND_MEM);
130}
131EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
132
133static void (*at91_suspend_sram_fn)(void __iomem *pmc, void __iomem *ramc0,
134 void __iomem *ramc1, int memctrl);
135
136extern void at91_pm_suspend_in_sram(void __iomem *pmc, void __iomem *ramc0,
137 void __iomem *ramc1, int memctrl);
138extern u32 at91_pm_suspend_in_sram_sz;
139
140static void at91_pm_suspend(suspend_state_t state)
141{
142 unsigned int pm_data = at91_pm_data.memctrl;
143
144 pm_data |= (state == PM_SUSPEND_MEM) ?
145 AT91_PM_MODE(AT91_PM_SLOW_CLOCK) : 0;
146
147 flush_cache_all();
148 outer_disable();
149
150 at91_suspend_sram_fn(pmc, at91_ramc_base[0],
151 at91_ramc_base[1], pm_data);
152
153 outer_resume();
154}
155
156static int at91_pm_enter(suspend_state_t state)
157{
158#ifdef CONFIG_PINCTRL_AT91
159 at91_pinctrl_gpio_suspend();
160#endif
161 switch (state) {
162
163
164
165
166
167 case PM_SUSPEND_MEM:
168
169
170
171 if (!at91_pm_verify_clocks())
172 goto error;
173
174 at91_pm_suspend(state);
175
176 break;
177
178
179
180
181
182
183
184 case PM_SUSPEND_STANDBY:
185 at91_pm_suspend(state);
186 break;
187
188 case PM_SUSPEND_ON:
189 cpu_do_idle();
190 break;
191
192 default:
193 pr_debug("AT91: PM - bogus suspend state %d\n", state);
194 goto error;
195 }
196
197error:
198 target_state = PM_SUSPEND_ON;
199
200#ifdef CONFIG_PINCTRL_AT91
201 at91_pinctrl_gpio_resume();
202#endif
203 return 0;
204}
205
206
207
208
209static void at91_pm_end(void)
210{
211 target_state = PM_SUSPEND_ON;
212}
213
214
215static const struct platform_suspend_ops at91_pm_ops = {
216 .valid = at91_pm_valid_state,
217 .begin = at91_pm_begin,
218 .enter = at91_pm_enter,
219 .end = at91_pm_end,
220};
221
222static struct platform_device at91_cpuidle_device = {
223 .name = "cpuidle-at91",
224};
225
226static void at91_pm_set_standby(void (*at91_standby)(void))
227{
228 if (at91_standby)
229 at91_cpuidle_device.dev.platform_data = at91_standby;
230}
231
232
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234
235
236
237
238
239
240
241static void at91rm9200_standby(void)
242{
243 u32 lpr = at91_ramc_read(0, AT91_MC_SDRAMC_LPR);
244
245 asm volatile(
246 "b 1f\n\t"
247 ".align 5\n\t"
248 "1: mcr p15, 0, %0, c7, c10, 4\n\t"
249 " str %0, [%1, %2]\n\t"
250 " str %3, [%1, %4]\n\t"
251 " mcr p15, 0, %0, c7, c0, 4\n\t"
252 " str %5, [%1, %2]"
253 :
254 : "r" (0), "r" (at91_ramc_base[0]), "r" (AT91_MC_SDRAMC_LPR),
255 "r" (1), "r" (AT91_MC_SDRAMC_SRR),
256 "r" (lpr));
257}
258
259
260
261
262static void at91_ddr_standby(void)
263{
264
265
266 u32 lpr0, lpr1 = 0;
267 u32 saved_lpr0, saved_lpr1 = 0;
268
269 if (at91_ramc_base[1]) {
270 saved_lpr1 = at91_ramc_read(1, AT91_DDRSDRC_LPR);
271 lpr1 = saved_lpr1 & ~AT91_DDRSDRC_LPCB;
272 lpr1 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
273 }
274
275 saved_lpr0 = at91_ramc_read(0, AT91_DDRSDRC_LPR);
276 lpr0 = saved_lpr0 & ~AT91_DDRSDRC_LPCB;
277 lpr0 |= AT91_DDRSDRC_LPCB_SELF_REFRESH;
278
279
280 at91_ramc_write(0, AT91_DDRSDRC_LPR, lpr0);
281 if (at91_ramc_base[1])
282 at91_ramc_write(1, AT91_DDRSDRC_LPR, lpr1);
283
284 cpu_do_idle();
285
286 at91_ramc_write(0, AT91_DDRSDRC_LPR, saved_lpr0);
287 if (at91_ramc_base[1])
288 at91_ramc_write(1, AT91_DDRSDRC_LPR, saved_lpr1);
289}
290
291
292
293
294static void at91sam9_sdram_standby(void)
295{
296 u32 lpr0, lpr1 = 0;
297 u32 saved_lpr0, saved_lpr1 = 0;
298
299 if (at91_ramc_base[1]) {
300 saved_lpr1 = at91_ramc_read(1, AT91_SDRAMC_LPR);
301 lpr1 = saved_lpr1 & ~AT91_SDRAMC_LPCB;
302 lpr1 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
303 }
304
305 saved_lpr0 = at91_ramc_read(0, AT91_SDRAMC_LPR);
306 lpr0 = saved_lpr0 & ~AT91_SDRAMC_LPCB;
307 lpr0 |= AT91_SDRAMC_LPCB_SELF_REFRESH;
308
309
310 at91_ramc_write(0, AT91_SDRAMC_LPR, lpr0);
311 if (at91_ramc_base[1])
312 at91_ramc_write(1, AT91_SDRAMC_LPR, lpr1);
313
314 cpu_do_idle();
315
316 at91_ramc_write(0, AT91_SDRAMC_LPR, saved_lpr0);
317 if (at91_ramc_base[1])
318 at91_ramc_write(1, AT91_SDRAMC_LPR, saved_lpr1);
319}
320
321static const struct of_device_id const ramc_ids[] __initconst = {
322 { .compatible = "atmel,at91rm9200-sdramc", .data = at91rm9200_standby },
323 { .compatible = "atmel,at91sam9260-sdramc", .data = at91sam9_sdram_standby },
324 { .compatible = "atmel,at91sam9g45-ddramc", .data = at91_ddr_standby },
325 { .compatible = "atmel,sama5d3-ddramc", .data = at91_ddr_standby },
326 { }
327};
328
329static __init void at91_dt_ramc(void)
330{
331 struct device_node *np;
332 const struct of_device_id *of_id;
333 int idx = 0;
334 const void *standby = NULL;
335
336 for_each_matching_node_and_match(np, ramc_ids, &of_id) {
337 at91_ramc_base[idx] = of_iomap(np, 0);
338 if (!at91_ramc_base[idx])
339 panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
340
341 if (!standby)
342 standby = of_id->data;
343
344 idx++;
345 }
346
347 if (!idx)
348 panic(pr_fmt("unable to find compatible ram controller node in dtb\n"));
349
350 if (!standby) {
351 pr_warn("ramc no standby function available\n");
352 return;
353 }
354
355 at91_pm_set_standby(standby);
356}
357
358void at91rm9200_idle(void)
359{
360
361
362
363
364 writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR);
365}
366
367void at91sam9_idle(void)
368{
369 writel(AT91_PMC_PCK, pmc + AT91_PMC_SCDR);
370 cpu_do_idle();
371}
372
373static void __init at91_pm_sram_init(void)
374{
375 struct gen_pool *sram_pool;
376 phys_addr_t sram_pbase;
377 unsigned long sram_base;
378 struct device_node *node;
379 struct platform_device *pdev = NULL;
380
381 for_each_compatible_node(node, NULL, "mmio-sram") {
382 pdev = of_find_device_by_node(node);
383 if (pdev) {
384 of_node_put(node);
385 break;
386 }
387 }
388
389 if (!pdev) {
390 pr_warn("%s: failed to find sram device!\n", __func__);
391 return;
392 }
393
394 sram_pool = gen_pool_get(&pdev->dev, NULL);
395 if (!sram_pool) {
396 pr_warn("%s: sram pool unavailable!\n", __func__);
397 return;
398 }
399
400 sram_base = gen_pool_alloc(sram_pool, at91_pm_suspend_in_sram_sz);
401 if (!sram_base) {
402 pr_warn("%s: unable to alloc sram!\n", __func__);
403 return;
404 }
405
406 sram_pbase = gen_pool_virt_to_phys(sram_pool, sram_base);
407 at91_suspend_sram_fn = __arm_ioremap_exec(sram_pbase,
408 at91_pm_suspend_in_sram_sz, false);
409 if (!at91_suspend_sram_fn) {
410 pr_warn("SRAM: Could not map\n");
411 return;
412 }
413
414
415 at91_suspend_sram_fn = fncpy(at91_suspend_sram_fn,
416 &at91_pm_suspend_in_sram, at91_pm_suspend_in_sram_sz);
417}
418
419static const struct of_device_id atmel_pmc_ids[] __initconst = {
420 { .compatible = "atmel,at91rm9200-pmc" },
421 { .compatible = "atmel,at91sam9260-pmc" },
422 { .compatible = "atmel,at91sam9g45-pmc" },
423 { .compatible = "atmel,at91sam9n12-pmc" },
424 { .compatible = "atmel,at91sam9x5-pmc" },
425 { .compatible = "atmel,sama5d3-pmc" },
426 { .compatible = "atmel,sama5d2-pmc" },
427 { },
428};
429
430static void __init at91_pm_init(void (*pm_idle)(void))
431{
432 struct device_node *pmc_np;
433
434 if (at91_cpuidle_device.dev.platform_data)
435 platform_device_register(&at91_cpuidle_device);
436
437 pmc_np = of_find_matching_node(NULL, atmel_pmc_ids);
438 pmc = of_iomap(pmc_np, 0);
439 if (!pmc) {
440 pr_err("AT91: PM not supported, PMC not found\n");
441 return;
442 }
443
444 if (pm_idle)
445 arm_pm_idle = pm_idle;
446
447 at91_pm_sram_init();
448
449 if (at91_suspend_sram_fn)
450 suspend_set_ops(&at91_pm_ops);
451 else
452 pr_info("AT91: PM not supported, due to no SRAM allocated\n");
453}
454
455void __init at91rm9200_pm_init(void)
456{
457 at91_dt_ramc();
458
459
460
461
462 at91_ramc_write(0, AT91_MC_SDRAMC_LPR, 0);
463
464 at91_pm_data.uhp_udp_mask = AT91RM9200_PMC_UHP | AT91RM9200_PMC_UDP;
465 at91_pm_data.memctrl = AT91_MEMCTRL_MC;
466
467 at91_pm_init(at91rm9200_idle);
468}
469
470void __init at91sam9260_pm_init(void)
471{
472 at91_dt_ramc();
473 at91_pm_data.memctrl = AT91_MEMCTRL_SDRAMC;
474 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
475 at91_pm_init(at91sam9_idle);
476}
477
478void __init at91sam9g45_pm_init(void)
479{
480 at91_dt_ramc();
481 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP;
482 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
483 at91_pm_init(at91sam9_idle);
484}
485
486void __init at91sam9x5_pm_init(void)
487{
488 at91_dt_ramc();
489 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
490 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
491 at91_pm_init(at91sam9_idle);
492}
493
494void __init sama5_pm_init(void)
495{
496 at91_dt_ramc();
497 at91_pm_data.uhp_udp_mask = AT91SAM926x_PMC_UHP | AT91SAM926x_PMC_UDP;
498 at91_pm_data.memctrl = AT91_MEMCTRL_DDRSDR;
499 at91_pm_init(NULL);
500}
501