1/* 2 * arch/arm/mach-dove/include/mach/bridge-regs.h 3 * 4 * Mbus-L to Mbus Bridge Registers 5 * 6 * This file is licensed under the terms of the GNU General Public 7 * License version 2. This program is licensed "as is" without any 8 * warranty of any kind, whether express or implied. 9 */ 10 11#ifndef __ASM_ARCH_BRIDGE_REGS_H 12#define __ASM_ARCH_BRIDGE_REGS_H 13 14#include <mach/dove.h> 15 16#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0000) 17 18#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104) 19#define CPU_CTRL_PCIE0_LINK 0x00000001 20#define CPU_RESET 0x00000002 21#define CPU_CTRL_PCIE1_LINK 0x00000008 22 23#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108) 24#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108) 25#define SOFT_RESET_OUT_EN 0x00000004 26 27#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c) 28#define SOFT_RESET 0x00000001 29 30#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110) 31#define BRIDGE_INT_TIMER1_CLR (~0x0004) 32 33#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200) 34#define IRQ_CAUSE_LOW_OFF 0x0000 35#define IRQ_MASK_LOW_OFF 0x0004 36#define FIQ_MASK_LOW_OFF 0x0008 37#define ENDPOINT_MASK_LOW_OFF 0x000c 38#define IRQ_CAUSE_HIGH_OFF 0x0010 39#define IRQ_MASK_HIGH_OFF 0x0014 40#define FIQ_MASK_HIGH_OFF 0x0018 41#define ENDPOINT_MASK_HIGH_OFF 0x001c 42#define PCIE_INTERRUPT_MASK_OFF 0x0020 43 44#define IRQ_MASK_LOW (IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF) 45#define FIQ_MASK_LOW (IRQ_VIRT_BASE + FIQ_MASK_LOW_OFF) 46#define ENDPOINT_MASK_LOW (IRQ_VIRT_BASE + ENDPOINT_MASK_LOW_OFF) 47#define IRQ_MASK_HIGH (IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF) 48#define FIQ_MASK_HIGH (IRQ_VIRT_BASE + FIQ_MASK_HIGH_OFF) 49#define ENDPOINT_MASK_HIGH (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF) 50#define PCIE_INTERRUPT_MASK (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF) 51 52#define POWER_MANAGEMENT (BRIDGE_VIRT_BASE + 0x011c) 53 54#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300) 55#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300) 56 57#endif 58