LXR linux/arch/arm/mach-imx/mm-imx3.c

   1/*
   2 *  Copyright (C) 1999,2000 Arm Limited
   3 *  Copyright (C) 2000 Deep Blue Solutions Ltd
   4 *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
   5 *  Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
   6 *    - add MX31 specific definitions
   7 *
   8 * This program is free software; you can redistribute it and/or modify
   9 * it under the terms of the GNU General Public License as published by
  10 * the Free Software Foundation; either version 2 of the License, or
  11 * (at your option) any later version.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 */
  18
  19#include <linux/mm.h>
  20#include <linux/init.h>
  21#include <linux/err.h>
  22#include <linux/pinctrl/machine.h>
  23
  24#include <asm/pgtable.h>
  25#include <asm/system_misc.h>
  26#include <asm/hardware/cache-l2x0.h>
  27#include <asm/mach/map.h>
  28
  29#include "common.h"
  30#include "crmregs-imx3.h"
  31#include "devices/devices-common.h"
  32#include "hardware.h"
  33#include "iomux-v3.h"
  34
  35void __iomem *mx3_ccm_base;
  36
  37static void imx3_idle(void)
  38{
  39        unsigned long reg = 0;
  40
  41        mx3_cpu_lp_set(MX3_WAIT);
  42
  43        __asm__ __volatile__(
  44                /* disable I and D cache */
  45                "mrc p15, 0, %0, c1, c0, 0\n"
  46                "bic %0, %0, #0x00001000\n"
  47                "bic %0, %0, #0x00000004\n"
  48                "mcr p15, 0, %0, c1, c0, 0\n"
  49                /* invalidate I cache */
  50                "mov %0, #0\n"
  51                "mcr p15, 0, %0, c7, c5, 0\n"
  52                /* clear and invalidate D cache */
  53                "mov %0, #0\n"
  54                "mcr p15, 0, %0, c7, c14, 0\n"
  55                /* WFI */
  56                "mov %0, #0\n"
  57                "mcr p15, 0, %0, c7, c0, 4\n"
  58                "nop\n" "nop\n" "nop\n" "nop\n"
  59                "nop\n" "nop\n" "nop\n"
  60                /* enable I and D cache */
  61                "mrc p15, 0, %0, c1, c0, 0\n"
  62                "orr %0, %0, #0x00001000\n"
  63                "orr %0, %0, #0x00000004\n"
  64                "mcr p15, 0, %0, c1, c0, 0\n"
  65                : "=r" (reg));
  66}
  67
  68static void __iomem *imx3_ioremap_caller(phys_addr_t phys_addr, size_t size,
  69                                         unsigned int mtype, void *caller)
  70{
  71        if (mtype == MT_DEVICE) {
  72                /*
  73                 * Access all peripherals below 0x80000000 as nonshared device
  74                 * on mx3, but leave l2cc alone.  Otherwise cache corruptions
  75                 * can occur.
  76                 */
  77                if (phys_addr < 0x80000000 &&
  78                                !addr_in_module(phys_addr, MX3x_L2CC))
  79                        mtype = MT_DEVICE_NONSHARED;
  80        }
  81
  82        return __arm_ioremap_caller(phys_addr, size, mtype, caller);
  83}
  84
  85static void __init imx3_init_l2x0(void)
  86{
  87#ifdef CONFIG_CACHE_L2X0
  88        void __iomem *l2x0_base;
  89        void __iomem *clkctl_base;
  90
  91/*
  92 * First of all, we must repair broken chip settings. There are some
  93 * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
  94 * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
  95 * Workaraound is to setup the correct register setting prior enabling the
  96 * L2 cache. This should not hurt already working CPUs, as they are using the
  97 * same value.
  98 */
  99#define L2_MEM_VAL 0x10
 100
 101        clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
 102        if (clkctl_base != NULL) {
 103                writel(0x00000515, clkctl_base + L2_MEM_VAL);
 104                iounmap(clkctl_base);
 105        } else {
 106                pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
 107        }
 108
 109        l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
 110        if (!l2x0_base) {
 111                printk(KERN_ERR "remapping L2 cache area failed\n");
 112                return;
 113        }
 114
 115        l2x0_init(l2x0_base, 0x00030024, 0x00000000);
 116#endif
 117}
 118
 119#ifdef CONFIG_SOC_IMX31
 120static struct map_desc mx31_io_desc[] __initdata = {
 121        imx_map_entry(MX31, X_MEMC, MT_DEVICE),
 122        imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
 123        imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
 124        imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
 125        imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
 126};
 127
 128/*
 129 * This function initializes the memory map. It is called during the
 130 * system startup to create static physical to virtual memory mappings
 131 * for the IO modules.
 132 */
 133void __init mx31_map_io(void)
 134{
 135        iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
 136}
 137
 138void __init imx31_init_early(void)
 139{
 140        mxc_set_cpu_type(MXC_CPU_MX31);
 141        arch_ioremap_caller = imx3_ioremap_caller;
 142        arm_pm_idle = imx3_idle;
 143        mx3_ccm_base = MX31_IO_ADDRESS(MX31_CCM_BASE_ADDR);
 144}
 145
 146void __init mx31_init_irq(void)
 147{
 148        mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
 149}
 150
 151static struct sdma_script_start_addrs imx31_to1_sdma_script __initdata = {
 152        .per_2_per_addr = 1677,
 153};
 154
 155static struct sdma_script_start_addrs imx31_to2_sdma_script __initdata = {
 156        .ap_2_ap_addr = 423,
 157        .ap_2_bp_addr = 829,
 158        .bp_2_ap_addr = 1029,
 159};
 160
 161static struct sdma_platform_data imx31_sdma_pdata __initdata = {
 162        .fw_name = "sdma-imx31-to2.bin",
 163        .script_addrs = &imx31_to2_sdma_script,
 164};
 165
 166static const struct resource imx31_audmux_res[] __initconst = {
 167        DEFINE_RES_MEM(MX31_AUDMUX_BASE_ADDR, SZ_16K),
 168};
 169
 170void __init imx31_soc_init(void)
 171{
 172        int to_version = mx31_revision() >> 4;
 173
 174        imx3_init_l2x0();
 175
 176        mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
 177        mxc_device_init();
 178
 179        mxc_register_gpio("imx31-gpio", 0, MX31_GPIO1_BASE_ADDR, SZ_16K, MX31_INT_GPIO1, 0);
 180        mxc_register_gpio("imx31-gpio", 1, MX31_GPIO2_BASE_ADDR, SZ_16K, MX31_INT_GPIO2, 0);
 181        mxc_register_gpio("imx31-gpio", 2, MX31_GPIO3_BASE_ADDR, SZ_16K, MX31_INT_GPIO3, 0);
 182
 183        pinctrl_provide_dummies();
 184
 185        if (to_version == 1) {
 186                strncpy(imx31_sdma_pdata.fw_name, "sdma-imx31-to1.bin",
 187                        strlen(imx31_sdma_pdata.fw_name));
 188                imx31_sdma_pdata.script_addrs = &imx31_to1_sdma_script;
 189        }
 190
 191        imx_add_imx_sdma("imx31-sdma", MX31_SDMA_BASE_ADDR, MX31_INT_SDMA, &imx31_sdma_pdata);
 192
 193        imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS1_BASE_ADDR));
 194        imx_set_aips(MX31_IO_ADDRESS(MX31_AIPS2_BASE_ADDR));
 195
 196        platform_device_register_simple("imx31-audmux", 0, imx31_audmux_res,
 197                                        ARRAY_SIZE(imx31_audmux_res));
 198}
 199#endif /* ifdef CONFIG_SOC_IMX31 */
 200
 201#ifdef CONFIG_SOC_IMX35
 202static struct map_desc mx35_io_desc[] __initdata = {
 203        imx_map_entry(MX35, X_MEMC, MT_DEVICE),
 204        imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
 205        imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
 206        imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
 207        imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
 208};
 209
 210void __init mx35_map_io(void)
 211{
 212        iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
 213}
 214
 215void __init imx35_init_early(void)
 216{
 217        mxc_set_cpu_type(MXC_CPU_MX35);
 218        mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
 219        arm_pm_idle = imx3_idle;
 220        arch_ioremap_caller = imx3_ioremap_caller;
 221        mx3_ccm_base = MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR);
 222}
 223
 224void __init mx35_init_irq(void)
 225{
 226        mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
 227}
 228
 229static struct sdma_script_start_addrs imx35_to1_sdma_script __initdata = {
 230        .ap_2_ap_addr = 642,
 231        .uart_2_mcu_addr = 817,
 232        .mcu_2_app_addr = 747,
 233        .uartsh_2_mcu_addr = 1183,
 234        .per_2_shp_addr = 1033,
 235        .mcu_2_shp_addr = 961,
 236        .ata_2_mcu_addr = 1333,
 237        .mcu_2_ata_addr = 1252,
 238        .app_2_mcu_addr = 683,
 239        .shp_2_per_addr = 1111,
 240        .shp_2_mcu_addr = 892,
 241};
 242
 243static struct sdma_script_start_addrs imx35_to2_sdma_script __initdata = {
 244        .ap_2_ap_addr = 729,
 245        .uart_2_mcu_addr = 904,
 246        .per_2_app_addr = 1597,
 247        .mcu_2_app_addr = 834,
 248        .uartsh_2_mcu_addr = 1270,
 249        .per_2_shp_addr = 1120,
 250        .mcu_2_shp_addr = 1048,
 251        .ata_2_mcu_addr = 1429,
 252        .mcu_2_ata_addr = 1339,
 253        .app_2_per_addr = 1531,
 254        .app_2_mcu_addr = 770,
 255        .shp_2_per_addr = 1198,
 256        .shp_2_mcu_addr = 979,
 257};
 258
 259static struct sdma_platform_data imx35_sdma_pdata __initdata = {
 260        .fw_name = "sdma-imx35-to2.bin",
 261        .script_addrs = &imx35_to2_sdma_script,
 262};
 263
 264static const struct resource imx35_audmux_res[] __initconst = {
 265        DEFINE_RES_MEM(MX35_AUDMUX_BASE_ADDR, SZ_16K),
 266};
 267
 268void __init imx35_soc_init(void)
 269{
 270        int to_version = mx35_revision() >> 4;
 271
 272        imx3_init_l2x0();
 273
 274        mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
 275        mxc_device_init();
 276
 277        mxc_register_gpio("imx35-gpio", 0, MX35_GPIO1_BASE_ADDR, SZ_16K, MX35_INT_GPIO1, 0);
 278        mxc_register_gpio("imx35-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
 279        mxc_register_gpio("imx35-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
 280
 281        pinctrl_provide_dummies();
 282        if (to_version == 1) {
 283                strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
 284                        strlen(imx35_sdma_pdata.fw_name));
 285                imx35_sdma_pdata.script_addrs = &imx35_to1_sdma_script;
 286        }
 287
 288        imx_add_imx_sdma("imx35-sdma", MX35_SDMA_BASE_ADDR, MX35_INT_SDMA, &imx35_sdma_pdata);
 289
 290        /* Setup AIPS registers */
 291        imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS1_BASE_ADDR));
 292        imx_set_aips(MX35_IO_ADDRESS(MX35_AIPS2_BASE_ADDR));
 293
 294        /* i.mx35 has the i.mx31 type audmux */
 295        platform_device_register_simple("imx31-audmux", 0, imx35_audmux_res,
 296                                        ARRAY_SIZE(imx35_audmux_res));
 297}
 298#endif /* ifdef CONFIG_SOC_IMX35 */
 299