1#include <linux/module.h>
2#include <linux/kernel.h>
3#include <linux/init.h>
4#include <linux/list.h>
5#include <linux/io.h>
6#include <linux/clk.h>
7#include <linux/clk/mmp.h>
8
9#include "addr-map.h"
10
11#include "common.h"
12#include "clock.h"
13
14
15
16
17#define APBC_RTC APBC_REG(0x000)
18#define APBC_TWSI1 APBC_REG(0x004)
19#define APBC_TWSI2 APBC_REG(0x008)
20#define APBC_TWSI3 APBC_REG(0x00c)
21#define APBC_TWSI4 APBC_REG(0x010)
22#define APBC_KPC APBC_REG(0x018)
23#define APBC_UART1 APBC_REG(0x02c)
24#define APBC_UART2 APBC_REG(0x030)
25#define APBC_UART3 APBC_REG(0x034)
26#define APBC_GPIO APBC_REG(0x038)
27#define APBC_PWM0 APBC_REG(0x03c)
28#define APBC_PWM1 APBC_REG(0x040)
29#define APBC_PWM2 APBC_REG(0x044)
30#define APBC_PWM3 APBC_REG(0x048)
31#define APBC_SSP0 APBC_REG(0x04c)
32#define APBC_SSP1 APBC_REG(0x050)
33#define APBC_SSP2 APBC_REG(0x054)
34#define APBC_SSP3 APBC_REG(0x058)
35#define APBC_SSP4 APBC_REG(0x05c)
36#define APBC_SSP5 APBC_REG(0x060)
37#define APBC_TWSI5 APBC_REG(0x07c)
38#define APBC_TWSI6 APBC_REG(0x080)
39#define APBC_UART4 APBC_REG(0x088)
40
41#define APMU_USB APMU_REG(0x05c)
42#define APMU_NAND APMU_REG(0x060)
43#define APMU_SDH0 APMU_REG(0x054)
44#define APMU_SDH1 APMU_REG(0x058)
45#define APMU_SDH2 APMU_REG(0x0e8)
46#define APMU_SDH3 APMU_REG(0x0ec)
47
48static void sdhc_clk_enable(struct clk *clk)
49{
50 uint32_t clk_rst;
51
52 clk_rst = __raw_readl(clk->clk_rst);
53 clk_rst |= clk->enable_val;
54 __raw_writel(clk_rst, clk->clk_rst);
55}
56
57static void sdhc_clk_disable(struct clk *clk)
58{
59 uint32_t clk_rst;
60
61 clk_rst = __raw_readl(clk->clk_rst);
62 clk_rst &= ~clk->enable_val;
63 __raw_writel(clk_rst, clk->clk_rst);
64}
65
66struct clkops sdhc_clk_ops = {
67 .enable = sdhc_clk_enable,
68 .disable = sdhc_clk_disable,
69};
70
71
72static APBC_CLK(uart1, UART1, 1, 26000000);
73static APBC_CLK(uart2, UART2, 1, 26000000);
74static APBC_CLK(uart3, UART3, 1, 26000000);
75static APBC_CLK(uart4, UART4, 1, 26000000);
76static APBC_CLK(twsi1, TWSI1, 0, 26000000);
77static APBC_CLK(twsi2, TWSI2, 0, 26000000);
78static APBC_CLK(twsi3, TWSI3, 0, 26000000);
79static APBC_CLK(twsi4, TWSI4, 0, 26000000);
80static APBC_CLK(twsi5, TWSI5, 0, 26000000);
81static APBC_CLK(twsi6, TWSI6, 0, 26000000);
82static APBC_CLK(gpio, GPIO, 0, 26000000);
83
84static APMU_CLK(nand, NAND, 0xbf, 100000000);
85static APMU_CLK_OPS(sdh0, SDH0, 0x1b, 200000000, &sdhc_clk_ops);
86static APMU_CLK_OPS(sdh1, SDH1, 0x1b, 200000000, &sdhc_clk_ops);
87static APMU_CLK_OPS(sdh2, SDH2, 0x1b, 200000000, &sdhc_clk_ops);
88static APMU_CLK_OPS(sdh3, SDH3, 0x1b, 200000000, &sdhc_clk_ops);
89
90static struct clk_lookup mmp2_clkregs[] = {
91 INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
92 INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
93 INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
94 INIT_CLKREG(&clk_uart4, "pxa2xx-uart.3", NULL),
95 INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.0", NULL),
96 INIT_CLKREG(&clk_twsi2, "pxa2xx-i2c.1", NULL),
97 INIT_CLKREG(&clk_twsi3, "pxa2xx-i2c.2", NULL),
98 INIT_CLKREG(&clk_twsi4, "pxa2xx-i2c.3", NULL),
99 INIT_CLKREG(&clk_twsi5, "pxa2xx-i2c.4", NULL),
100 INIT_CLKREG(&clk_twsi6, "pxa2xx-i2c.5", NULL),
101 INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
102 INIT_CLKREG(&clk_gpio, "mmp2-gpio", NULL),
103 INIT_CLKREG(&clk_sdh0, "sdhci-pxav3.0", "PXA-SDHCLK"),
104 INIT_CLKREG(&clk_sdh1, "sdhci-pxav3.1", "PXA-SDHCLK"),
105 INIT_CLKREG(&clk_sdh2, "sdhci-pxav3.2", "PXA-SDHCLK"),
106 INIT_CLKREG(&clk_sdh3, "sdhci-pxav3.3", "PXA-SDHCLK"),
107};
108
109void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
110 phys_addr_t apbc_phys)
111{
112 clkdev_add_table(ARRAY_AND_SIZE(mmp2_clkregs));
113}
114
