LXR linux/arch/arm/mach-mmp/clock-pxa168.c

   1#include <linux/module.h>
   2#include <linux/kernel.h>
   3#include <linux/init.h>
   4#include <linux/list.h>
   5#include <linux/io.h>
   6#include <linux/clk.h>
   7#include <linux/clk/mmp.h>
   8
   9#include "addr-map.h"
  10
  11#include "common.h"
  12#include "clock.h"
  13
  14/*
  15 * APB clock register offsets for PXA168
  16 */
  17#define APBC_UART1      APBC_REG(0x000)
  18#define APBC_UART2      APBC_REG(0x004)
  19#define APBC_GPIO       APBC_REG(0x008)
  20#define APBC_PWM1       APBC_REG(0x00c)
  21#define APBC_PWM2       APBC_REG(0x010)
  22#define APBC_PWM3       APBC_REG(0x014)
  23#define APBC_PWM4       APBC_REG(0x018)
  24#define APBC_RTC        APBC_REG(0x028)
  25#define APBC_TWSI0      APBC_REG(0x02c)
  26#define APBC_KPC        APBC_REG(0x030)
  27#define APBC_TWSI1      APBC_REG(0x06c)
  28#define APBC_UART3      APBC_REG(0x070)
  29#define APBC_SSP1       APBC_REG(0x81c)
  30#define APBC_SSP2       APBC_REG(0x820)
  31#define APBC_SSP3       APBC_REG(0x84c)
  32#define APBC_SSP4       APBC_REG(0x858)
  33#define APBC_SSP5       APBC_REG(0x85c)
  34
  35#define APMU_NAND       APMU_REG(0x060)
  36#define APMU_LCD        APMU_REG(0x04c)
  37#define APMU_ETH        APMU_REG(0x0fc)
  38#define APMU_USB        APMU_REG(0x05c)
  39
  40/* APB peripheral clocks */
  41static APBC_CLK(uart1, UART1, 1, 14745600);
  42static APBC_CLK(uart2, UART2, 1, 14745600);
  43static APBC_CLK(uart3, UART3, 1, 14745600);
  44static APBC_CLK(twsi0, TWSI0, 1, 33000000);
  45static APBC_CLK(twsi1, TWSI1, 1, 33000000);
  46static APBC_CLK(pwm1, PWM1, 1, 13000000);
  47static APBC_CLK(pwm2, PWM2, 1, 13000000);
  48static APBC_CLK(pwm3, PWM3, 1, 13000000);
  49static APBC_CLK(pwm4, PWM4, 1, 13000000);
  50static APBC_CLK(ssp1, SSP1, 4, 0);
  51static APBC_CLK(ssp2, SSP2, 4, 0);
  52static APBC_CLK(ssp3, SSP3, 4, 0);
  53static APBC_CLK(ssp4, SSP4, 4, 0);
  54static APBC_CLK(ssp5, SSP5, 4, 0);
  55static APBC_CLK(gpio, GPIO, 0, 13000000);
  56static APBC_CLK(keypad, KPC, 0, 32000);
  57static APBC_CLK(rtc, RTC, 8, 32768);
  58
  59static APMU_CLK(nand, NAND, 0x19b, 156000000);
  60static APMU_CLK(lcd, LCD, 0x7f, 312000000);
  61static APMU_CLK(eth, ETH, 0x09, 0);
  62static APMU_CLK(usb, USB, 0x12, 0);
  63
  64/* device and clock bindings */
  65static struct clk_lookup pxa168_clkregs[] = {
  66        INIT_CLKREG(&clk_uart1, "pxa2xx-uart.0", NULL),
  67        INIT_CLKREG(&clk_uart2, "pxa2xx-uart.1", NULL),
  68        INIT_CLKREG(&clk_uart3, "pxa2xx-uart.2", NULL),
  69        INIT_CLKREG(&clk_twsi0, "pxa2xx-i2c.0", NULL),
  70        INIT_CLKREG(&clk_twsi1, "pxa2xx-i2c.1", NULL),
  71        INIT_CLKREG(&clk_pwm1, "pxa168-pwm.0", NULL),
  72        INIT_CLKREG(&clk_pwm2, "pxa168-pwm.1", NULL),
  73        INIT_CLKREG(&clk_pwm3, "pxa168-pwm.2", NULL),
  74        INIT_CLKREG(&clk_pwm4, "pxa168-pwm.3", NULL),
  75        INIT_CLKREG(&clk_ssp1, "pxa168-ssp.0", NULL),
  76        INIT_CLKREG(&clk_ssp2, "pxa168-ssp.1", NULL),
  77        INIT_CLKREG(&clk_ssp3, "pxa168-ssp.2", NULL),
  78        INIT_CLKREG(&clk_ssp4, "pxa168-ssp.3", NULL),
  79        INIT_CLKREG(&clk_ssp5, "pxa168-ssp.4", NULL),
  80        INIT_CLKREG(&clk_nand, "pxa3xx-nand", NULL),
  81        INIT_CLKREG(&clk_lcd, "pxa168-fb", NULL),
  82        INIT_CLKREG(&clk_gpio, "mmp-gpio", NULL),
  83        INIT_CLKREG(&clk_keypad, "pxa27x-keypad", NULL),
  84        INIT_CLKREG(&clk_eth, "pxa168-eth", "MFUCLK"),
  85        INIT_CLKREG(&clk_usb, NULL, "PXA168-USBCLK"),
  86        INIT_CLKREG(&clk_rtc, "sa1100-rtc", NULL),
  87};
  88
  89void __init pxa168_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
  90                            phys_addr_t apbc_phys)
  91{
  92        clkdev_add_table(ARRAY_AND_SIZE(pxa168_clkregs));
  93}
  94