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36#include <linux/kernel.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/interrupt.h>
40#include <linux/spinlock.h>
41#include <linux/clk.h>
42#include <linux/err.h>
43#include <linux/clocksource.h>
44#include <linux/clockchips.h>
45#include <linux/io.h>
46#include <linux/sched_clock.h>
47
48#include <asm/irq.h>
49
50#include <mach/hardware.h>
51#include <asm/mach/irq.h>
52#include <asm/mach/time.h>
53
54#include "iomap.h"
55#include "common.h"
56
57#ifdef CONFIG_OMAP_MPU_TIMER
58
59#define OMAP_MPU_TIMER_BASE OMAP_MPU_TIMER1_BASE
60#define OMAP_MPU_TIMER_OFFSET 0x100
61
62typedef struct {
63 u32 cntl;
64 u32 load_tim;
65 u32 read_tim;
66} omap_mpu_timer_regs_t;
67
68#define omap_mpu_timer_base(n) \
69((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
70 (n)*OMAP_MPU_TIMER_OFFSET))
71
72static inline unsigned long notrace omap_mpu_timer_read(int nr)
73{
74 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
75 return readl(&timer->read_tim);
76}
77
78static inline void omap_mpu_set_autoreset(int nr)
79{
80 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
81
82 writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl);
83}
84
85static inline void omap_mpu_remove_autoreset(int nr)
86{
87 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
88
89 writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl);
90}
91
92static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
93 int autoreset)
94{
95 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
96 unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST;
97
98 if (autoreset)
99 timerflags |= MPU_TIMER_AR;
100
101 writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl);
102 udelay(1);
103 writel(load_val, &timer->load_tim);
104 udelay(1);
105 writel(timerflags, &timer->cntl);
106}
107
108static inline void omap_mpu_timer_stop(int nr)
109{
110 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
111
112 writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl);
113}
114
115
116
117
118
119
120static int omap_mpu_set_next_event(unsigned long cycles,
121 struct clock_event_device *evt)
122{
123 omap_mpu_timer_start(0, cycles, 0);
124 return 0;
125}
126
127static int omap_mpu_set_oneshot(struct clock_event_device *evt)
128{
129 omap_mpu_timer_stop(0);
130 omap_mpu_remove_autoreset(0);
131 return 0;
132}
133
134static int omap_mpu_set_periodic(struct clock_event_device *evt)
135{
136 omap_mpu_set_autoreset(0);
137 return 0;
138}
139
140static struct clock_event_device clockevent_mpu_timer1 = {
141 .name = "mpu_timer1",
142 .features = CLOCK_EVT_FEAT_PERIODIC |
143 CLOCK_EVT_FEAT_ONESHOT,
144 .set_next_event = omap_mpu_set_next_event,
145 .set_state_periodic = omap_mpu_set_periodic,
146 .set_state_oneshot = omap_mpu_set_oneshot,
147};
148
149static irqreturn_t omap_mpu_timer1_interrupt(int irq, void *dev_id)
150{
151 struct clock_event_device *evt = &clockevent_mpu_timer1;
152
153 evt->event_handler(evt);
154
155 return IRQ_HANDLED;
156}
157
158static struct irqaction omap_mpu_timer1_irq = {
159 .name = "mpu_timer1",
160 .flags = IRQF_TIMER | IRQF_IRQPOLL,
161 .handler = omap_mpu_timer1_interrupt,
162};
163
164static __init void omap_init_mpu_timer(unsigned long rate)
165{
166 setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
167 omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
168
169 clockevent_mpu_timer1.cpumask = cpumask_of(0);
170 clockevents_config_and_register(&clockevent_mpu_timer1, rate,
171 1, -1);
172}
173
174
175
176
177
178
179
180
181static u64 notrace omap_mpu_read_sched_clock(void)
182{
183 return ~omap_mpu_timer_read(1);
184}
185
186static void __init omap_init_clocksource(unsigned long rate)
187{
188 omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1);
189 static char err[] __initdata = KERN_ERR
190 "%s: can't register clocksource!\n";
191
192 omap_mpu_timer_start(1, ~0, 1);
193 sched_clock_register(omap_mpu_read_sched_clock, 32, rate);
194
195 if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate,
196 300, 32, clocksource_mmio_readl_down))
197 printk(err, "mpu_timer2");
198}
199
200static void __init omap_mpu_timer_init(void)
201{
202 struct clk *ck_ref = clk_get(NULL, "ck_ref");
203 unsigned long rate;
204
205 BUG_ON(IS_ERR(ck_ref));
206
207 rate = clk_get_rate(ck_ref);
208 clk_put(ck_ref);
209
210
211 rate /= 2;
212
213 omap_init_mpu_timer(rate);
214 omap_init_clocksource(rate);
215}
216
217#else
218static inline void omap_mpu_timer_init(void)
219{
220 pr_err("Bogus timer, should not happen\n");
221}
222#endif
223
224
225
226
227
228
229void __init omap1_timer_init(void)
230{
231 if (omap_32k_timer_init() != 0)
232 omap_mpu_timer_init();
233}
234