LXR linux/arch/arm/mach-s3c24xx/pll-s3c2440-12000000.c

   1/*
   2 * Copyright (c) 2006-2007 Simtec Electronics
   3 *      http://armlinux.simtec.co.uk/
   4 *      Ben Dooks <ben@simtec.co.uk>
   5 *      Vincent Sanders <vince@arm.linux.org.uk>
   6 *
   7 * S3C2440/S3C2442 CPU PLL tables (12MHz Crystal)
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License version 2 as
  11 * published by the Free Software Foundation.
  12*/
  13
  14#include <linux/types.h>
  15#include <linux/kernel.h>
  16#include <linux/device.h>
  17#include <linux/clk.h>
  18#include <linux/err.h>
  19
  20#include <plat/cpu.h>
  21#include <plat/cpu-freq-core.h>
  22
  23static struct cpufreq_frequency_table s3c2440_plls_12[] = {
  24        { .frequency = 75000000,        .driver_data = PLLVAL(0x75, 3, 3),  },  /* FVco 600.000000 */
  25        { .frequency = 80000000,        .driver_data = PLLVAL(0x98, 4, 3),  },  /* FVco 640.000000 */
  26        { .frequency = 90000000,        .driver_data = PLLVAL(0x70, 2, 3),  },  /* FVco 720.000000 */
  27        { .frequency = 100000000,       .driver_data = PLLVAL(0x5c, 1, 3),  },  /* FVco 800.000000 */
  28        { .frequency = 110000000,       .driver_data = PLLVAL(0x66, 1, 3),  },  /* FVco 880.000000 */
  29        { .frequency = 120000000,       .driver_data = PLLVAL(0x70, 1, 3),  },  /* FVco 960.000000 */
  30        { .frequency = 150000000,       .driver_data = PLLVAL(0x75, 3, 2),  },  /* FVco 600.000000 */
  31        { .frequency = 160000000,       .driver_data = PLLVAL(0x98, 4, 2),  },  /* FVco 640.000000 */
  32        { .frequency = 170000000,       .driver_data = PLLVAL(0x4d, 1, 2),  },  /* FVco 680.000000 */
  33        { .frequency = 180000000,       .driver_data = PLLVAL(0x70, 2, 2),  },  /* FVco 720.000000 */
  34        { .frequency = 190000000,       .driver_data = PLLVAL(0x57, 1, 2),  },  /* FVco 760.000000 */
  35        { .frequency = 200000000,       .driver_data = PLLVAL(0x5c, 1, 2),  },  /* FVco 800.000000 */
  36        { .frequency = 210000000,       .driver_data = PLLVAL(0x84, 2, 2),  },  /* FVco 840.000000 */
  37        { .frequency = 220000000,       .driver_data = PLLVAL(0x66, 1, 2),  },  /* FVco 880.000000 */
  38        { .frequency = 230000000,       .driver_data = PLLVAL(0x6b, 1, 2),  },  /* FVco 920.000000 */
  39        { .frequency = 240000000,       .driver_data = PLLVAL(0x70, 1, 2),  },  /* FVco 960.000000 */
  40        { .frequency = 300000000,       .driver_data = PLLVAL(0x75, 3, 1),  },  /* FVco 600.000000 */
  41        { .frequency = 310000000,       .driver_data = PLLVAL(0x93, 4, 1),  },  /* FVco 620.000000 */
  42        { .frequency = 320000000,       .driver_data = PLLVAL(0x98, 4, 1),  },  /* FVco 640.000000 */
  43        { .frequency = 330000000,       .driver_data = PLLVAL(0x66, 2, 1),  },  /* FVco 660.000000 */
  44        { .frequency = 340000000,       .driver_data = PLLVAL(0x4d, 1, 1),  },  /* FVco 680.000000 */
  45        { .frequency = 350000000,       .driver_data = PLLVAL(0xa7, 4, 1),  },  /* FVco 700.000000 */
  46        { .frequency = 360000000,       .driver_data = PLLVAL(0x70, 2, 1),  },  /* FVco 720.000000 */
  47        { .frequency = 370000000,       .driver_data = PLLVAL(0xb1, 4, 1),  },  /* FVco 740.000000 */
  48        { .frequency = 380000000,       .driver_data = PLLVAL(0x57, 1, 1),  },  /* FVco 760.000000 */
  49        { .frequency = 390000000,       .driver_data = PLLVAL(0x7a, 2, 1),  },  /* FVco 780.000000 */
  50        { .frequency = 400000000,       .driver_data = PLLVAL(0x5c, 1, 1),  },  /* FVco 800.000000 */
  51};
  52
  53static int s3c2440_plls12_add(struct device *dev, struct subsys_interface *sif)
  54{
  55        struct clk *xtal_clk;
  56        unsigned long xtal;
  57
  58        xtal_clk = clk_get(NULL, "xtal");
  59        if (IS_ERR(xtal_clk))
  60                return PTR_ERR(xtal_clk);
  61
  62        xtal = clk_get_rate(xtal_clk);
  63        clk_put(xtal_clk);
  64
  65        if (xtal == 12000000) {
  66                printk(KERN_INFO "Using PLL table for 12MHz crystal\n");
  67                return s3c_plltab_register(s3c2440_plls_12,
  68                                           ARRAY_SIZE(s3c2440_plls_12));
  69        }
  70
  71        return 0;
  72}
  73
  74static struct subsys_interface s3c2440_plls12_interface = {
  75        .name           = "s3c2440_plls12",
  76        .subsys         = &s3c2440_subsys,
  77        .add_dev        = s3c2440_plls12_add,
  78};
  79
  80static int __init s3c2440_pll_12mhz(void)
  81{
  82        return subsys_interface_register(&s3c2440_plls12_interface);
  83
  84}
  85arch_initcall(s3c2440_pll_12mhz);
  86
  87static struct subsys_interface s3c2442_plls12_interface = {
  88        .name           = "s3c2442_plls12",
  89        .subsys         = &s3c2442_subsys,
  90        .add_dev        = s3c2440_plls12_add,
  91};
  92
  93static int __init s3c2442_pll_12mhz(void)
  94{
  95        return subsys_interface_register(&s3c2442_plls12_interface);
  96
  97}
  98arch_initcall(s3c2442_pll_12mhz);
  99