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14#include <linux/types.h>
15#include <linux/kernel.h>
16#include <linux/device.h>
17#include <linux/clk.h>
18#include <linux/err.h>
19
20#include <plat/cpu.h>
21#include <plat/cpu-freq-core.h>
22
23static struct cpufreq_frequency_table s3c2440_plls_169344[] = {
24 { .frequency = 78019200, .driver_data = PLLVAL(121, 5, 3), },
25 { .frequency = 84067200, .driver_data = PLLVAL(131, 5, 3), },
26 { .frequency = 90115200, .driver_data = PLLVAL(141, 5, 3), },
27 { .frequency = 96163200, .driver_data = PLLVAL(151, 5, 3), },
28 { .frequency = 102135600, .driver_data = PLLVAL(185, 6, 3), },
29 { .frequency = 108259200, .driver_data = PLLVAL(171, 5, 3), },
30 { .frequency = 114307200, .driver_data = PLLVAL(127, 3, 3), },
31 { .frequency = 120234240, .driver_data = PLLVAL(134, 3, 3), },
32 { .frequency = 126161280, .driver_data = PLLVAL(141, 3, 3), },
33 { .frequency = 132088320, .driver_data = PLLVAL(148, 3, 3), },
34 { .frequency = 138015360, .driver_data = PLLVAL(155, 3, 3), },
35 { .frequency = 144789120, .driver_data = PLLVAL(163, 3, 3), },
36 { .frequency = 150100363, .driver_data = PLLVAL(187, 9, 2), },
37 { .frequency = 156038400, .driver_data = PLLVAL(121, 5, 2), },
38 { .frequency = 162086400, .driver_data = PLLVAL(126, 5, 2), },
39 { .frequency = 168134400, .driver_data = PLLVAL(131, 5, 2), },
40 { .frequency = 174048000, .driver_data = PLLVAL(177, 7, 2), },
41 { .frequency = 180230400, .driver_data = PLLVAL(141, 5, 2), },
42 { .frequency = 186278400, .driver_data = PLLVAL(124, 4, 2), },
43 { .frequency = 192326400, .driver_data = PLLVAL(151, 5, 2), },
44 { .frequency = 198132480, .driver_data = PLLVAL(109, 3, 2), },
45 { .frequency = 204271200, .driver_data = PLLVAL(185, 6, 2), },
46 { .frequency = 210268800, .driver_data = PLLVAL(141, 4, 2), },
47 { .frequency = 216518400, .driver_data = PLLVAL(171, 5, 2), },
48 { .frequency = 222264000, .driver_data = PLLVAL(97, 2, 2), },
49 { .frequency = 228614400, .driver_data = PLLVAL(127, 3, 2), },
50 { .frequency = 234259200, .driver_data = PLLVAL(158, 4, 2), },
51 { .frequency = 240468480, .driver_data = PLLVAL(134, 3, 2), },
52 { .frequency = 246960000, .driver_data = PLLVAL(167, 4, 2), },
53 { .frequency = 252322560, .driver_data = PLLVAL(141, 3, 2), },
54 { .frequency = 258249600, .driver_data = PLLVAL(114, 2, 2), },
55 { .frequency = 264176640, .driver_data = PLLVAL(148, 3, 2), },
56 { .frequency = 270950400, .driver_data = PLLVAL(120, 2, 2), },
57 { .frequency = 276030720, .driver_data = PLLVAL(155, 3, 2), },
58 { .frequency = 282240000, .driver_data = PLLVAL(92, 1, 2), },
59 { .frequency = 289578240, .driver_data = PLLVAL(163, 3, 2), },
60 { .frequency = 294235200, .driver_data = PLLVAL(131, 2, 2), },
61 { .frequency = 300200727, .driver_data = PLLVAL(187, 9, 1), },
62 { .frequency = 306358690, .driver_data = PLLVAL(191, 9, 1), },
63 { .frequency = 312076800, .driver_data = PLLVAL(121, 5, 1), },
64 { .frequency = 318366720, .driver_data = PLLVAL(86, 3, 1), },
65 { .frequency = 324172800, .driver_data = PLLVAL(126, 5, 1), },
66 { .frequency = 330220800, .driver_data = PLLVAL(109, 4, 1), },
67 { .frequency = 336268800, .driver_data = PLLVAL(131, 5, 1), },
68 { .frequency = 342074880, .driver_data = PLLVAL(93, 3, 1), },
69 { .frequency = 348096000, .driver_data = PLLVAL(177, 7, 1), },
70 { .frequency = 355622400, .driver_data = PLLVAL(118, 4, 1), },
71 { .frequency = 360460800, .driver_data = PLLVAL(141, 5, 1), },
72 { .frequency = 366206400, .driver_data = PLLVAL(165, 6, 1), },
73 { .frequency = 372556800, .driver_data = PLLVAL(124, 4, 1), },
74 { .frequency = 378201600, .driver_data = PLLVAL(126, 4, 1), },
75 { .frequency = 384652800, .driver_data = PLLVAL(151, 5, 1), },
76 { .frequency = 391608000, .driver_data = PLLVAL(177, 6, 1), },
77 { .frequency = 396264960, .driver_data = PLLVAL(109, 3, 1), },
78 { .frequency = 402192000, .driver_data = PLLVAL(87, 2, 1), },
79};
80
81static int s3c2440_plls169344_add(struct device *dev,
82 struct subsys_interface *sif)
83{
84 struct clk *xtal_clk;
85 unsigned long xtal;
86
87 xtal_clk = clk_get(NULL, "xtal");
88 if (IS_ERR(xtal_clk))
89 return PTR_ERR(xtal_clk);
90
91 xtal = clk_get_rate(xtal_clk);
92 clk_put(xtal_clk);
93
94 if (xtal == 169344000) {
95 printk(KERN_INFO "Using PLL table for 16.9344MHz crystal\n");
96 return s3c_plltab_register(s3c2440_plls_169344,
97 ARRAY_SIZE(s3c2440_plls_169344));
98 }
99
100 return 0;
101}
102
103static struct subsys_interface s3c2440_plls169344_interface = {
104 .name = "s3c2440_plls169344",
105 .subsys = &s3c2440_subsys,
106 .add_dev = s3c2440_plls169344_add,
107};
108
109static int __init s3c2440_pll_16934400(void)
110{
111 return subsys_interface_register(&s3c2440_plls169344_interface);
112}
113arch_initcall(s3c2440_pll_16934400);
114
115static struct subsys_interface s3c2442_plls169344_interface = {
116 .name = "s3c2442_plls169344",
117 .subsys = &s3c2442_subsys,
118 .add_dev = s3c2440_plls169344_add,
119};
120
121static int __init s3c2442_pll_16934400(void)
122{
123 return subsys_interface_register(&s3c2442_plls169344_interface);
124}
125arch_initcall(s3c2442_pll_16934400);
126
