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10#include <linux/module.h>
11#include <linux/kernel.h>
12#include <linux/errno.h>
13#include <linux/init.h>
14#include <linux/mman.h>
15#include <linux/nodemask.h>
16#include <linux/memblock.h>
17#include <linux/fs.h>
18#include <linux/vmalloc.h>
19#include <linux/sizes.h>
20
21#include <asm/cp15.h>
22#include <asm/cputype.h>
23#include <asm/sections.h>
24#include <asm/cachetype.h>
25#include <asm/fixmap.h>
26#include <asm/sections.h>
27#include <asm/setup.h>
28#include <asm/smp_plat.h>
29#include <asm/tlb.h>
30#include <asm/highmem.h>
31#include <asm/system_info.h>
32#include <asm/traps.h>
33#include <asm/procinfo.h>
34#include <asm/memory.h>
35
36#include <asm/mach/arch.h>
37#include <asm/mach/map.h>
38#include <asm/mach/pci.h>
39#include <asm/fixmap.h>
40
41#include "fault.h"
42#include "mm.h"
43#include "tcm.h"
44
45
46
47
48
49struct page *empty_zero_page;
50EXPORT_SYMBOL(empty_zero_page);
51
52
53
54
55pmd_t *top_pmd;
56
57pmdval_t user_pmd_table = _PAGE_USER_TABLE;
58
59#define CPOLICY_UNCACHED 0
60#define CPOLICY_BUFFERED 1
61#define CPOLICY_WRITETHROUGH 2
62#define CPOLICY_WRITEBACK 3
63#define CPOLICY_WRITEALLOC 4
64
65static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK;
66static unsigned int ecc_mask __initdata = 0;
67pgprot_t pgprot_user;
68pgprot_t pgprot_kernel;
69pgprot_t pgprot_hyp_device;
70pgprot_t pgprot_s2;
71pgprot_t pgprot_s2_device;
72
73EXPORT_SYMBOL(pgprot_user);
74EXPORT_SYMBOL(pgprot_kernel);
75
76struct cachepolicy {
77 const char policy[16];
78 unsigned int cr_mask;
79 pmdval_t pmd;
80 pteval_t pte;
81 pteval_t pte_s2;
82};
83
84#ifdef CONFIG_ARM_LPAE
85#define s2_policy(policy) policy
86#else
87#define s2_policy(policy) 0
88#endif
89
90static struct cachepolicy cache_policies[] __initdata = {
91 {
92 .policy = "uncached",
93 .cr_mask = CR_W|CR_C,
94 .pmd = PMD_SECT_UNCACHED,
95 .pte = L_PTE_MT_UNCACHED,
96 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
97 }, {
98 .policy = "buffered",
99 .cr_mask = CR_C,
100 .pmd = PMD_SECT_BUFFERED,
101 .pte = L_PTE_MT_BUFFERABLE,
102 .pte_s2 = s2_policy(L_PTE_S2_MT_UNCACHED),
103 }, {
104 .policy = "writethrough",
105 .cr_mask = 0,
106 .pmd = PMD_SECT_WT,
107 .pte = L_PTE_MT_WRITETHROUGH,
108 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITETHROUGH),
109 }, {
110 .policy = "writeback",
111 .cr_mask = 0,
112 .pmd = PMD_SECT_WB,
113 .pte = L_PTE_MT_WRITEBACK,
114 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
115 }, {
116 .policy = "writealloc",
117 .cr_mask = 0,
118 .pmd = PMD_SECT_WBWA,
119 .pte = L_PTE_MT_WRITEALLOC,
120 .pte_s2 = s2_policy(L_PTE_S2_MT_WRITEBACK),
121 }
122};
123
124#ifdef CONFIG_CPU_CP15
125static unsigned long initial_pmd_value __initdata = 0;
126
127
128
129
130
131
132
133
134void __init init_default_cache_policy(unsigned long pmd)
135{
136 int i;
137
138 initial_pmd_value = pmd;
139
140 pmd &= PMD_SECT_TEX(1) | PMD_SECT_BUFFERABLE | PMD_SECT_CACHEABLE;
141
142 for (i = 0; i < ARRAY_SIZE(cache_policies); i++)
143 if (cache_policies[i].pmd == pmd) {
144 cachepolicy = i;
145 break;
146 }
147
148 if (i == ARRAY_SIZE(cache_policies))
149 pr_err("ERROR: could not find cache policy\n");
150}
151
152
153
154
155
156
157static int __init early_cachepolicy(char *p)
158{
159 int i, selected = -1;
160
161 for (i = 0; i < ARRAY_SIZE(cache_policies); i++) {
162 int len = strlen(cache_policies[i].policy);
163
164 if (memcmp(p, cache_policies[i].policy, len) == 0) {
165 selected = i;
166 break;
167 }
168 }
169
170 if (selected == -1)
171 pr_err("ERROR: unknown or unsupported cache policy\n");
172
173
174
175
176
177
178
179
180 if (cpu_architecture() >= CPU_ARCH_ARMv6 && selected != cachepolicy) {
181 pr_warn("Only cachepolicy=%s supported on ARMv6 and later\n",
182 cache_policies[cachepolicy].policy);
183 return 0;
184 }
185
186 if (selected != cachepolicy) {
187 unsigned long cr = __clear_cr(cache_policies[selected].cr_mask);
188 cachepolicy = selected;
189 flush_cache_all();
190 set_cr(cr);
191 }
192 return 0;
193}
194early_param("cachepolicy", early_cachepolicy);
195
196static int __init early_nocache(char *__unused)
197{
198 char *p = "buffered";
199 pr_warn("nocache is deprecated; use cachepolicy=%s\n", p);
200 early_cachepolicy(p);
201 return 0;
202}
203early_param("nocache", early_nocache);
204
205static int __init early_nowrite(char *__unused)
206{
207 char *p = "uncached";
208 pr_warn("nowb is deprecated; use cachepolicy=%s\n", p);
209 early_cachepolicy(p);
210 return 0;
211}
212early_param("nowb", early_nowrite);
213
214#ifndef CONFIG_ARM_LPAE
215static int __init early_ecc(char *p)
216{
217 if (memcmp(p, "on", 2) == 0)
218 ecc_mask = PMD_PROTECTION;
219 else if (memcmp(p, "off", 3) == 0)
220 ecc_mask = 0;
221 return 0;
222}
223early_param("ecc", early_ecc);
224#endif
225
226#else
227
228static int __init early_cachepolicy(char *p)
229{
230 pr_warn("cachepolicy kernel parameter not supported without cp15\n");
231}
232early_param("cachepolicy", early_cachepolicy);
233
234static int __init noalign_setup(char *__unused)
235{
236 pr_warn("noalign kernel parameter not supported without cp15\n");
237}
238__setup("noalign", noalign_setup);
239
240#endif
241
242#define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN
243#define PROT_PTE_S2_DEVICE PROT_PTE_DEVICE
244#define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE
245
246static struct mem_type mem_types[] = {
247 [MT_DEVICE] = {
248 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED |
249 L_PTE_SHARED,
250 .prot_pte_s2 = s2_policy(PROT_PTE_S2_DEVICE) |
251 s2_policy(L_PTE_S2_MT_DEV_SHARED) |
252 L_PTE_SHARED,
253 .prot_l1 = PMD_TYPE_TABLE,
254 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S,
255 .domain = DOMAIN_IO,
256 },
257 [MT_DEVICE_NONSHARED] = {
258 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED,
259 .prot_l1 = PMD_TYPE_TABLE,
260 .prot_sect = PROT_SECT_DEVICE,
261 .domain = DOMAIN_IO,
262 },
263 [MT_DEVICE_CACHED] = {
264 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED,
265 .prot_l1 = PMD_TYPE_TABLE,
266 .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB,
267 .domain = DOMAIN_IO,
268 },
269 [MT_DEVICE_WC] = {
270 .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC,
271 .prot_l1 = PMD_TYPE_TABLE,
272 .prot_sect = PROT_SECT_DEVICE,
273 .domain = DOMAIN_IO,
274 },
275 [MT_UNCACHED] = {
276 .prot_pte = PROT_PTE_DEVICE,
277 .prot_l1 = PMD_TYPE_TABLE,
278 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
279 .domain = DOMAIN_IO,
280 },
281 [MT_CACHECLEAN] = {
282 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
283 .domain = DOMAIN_KERNEL,
284 },
285#ifndef CONFIG_ARM_LPAE
286 [MT_MINICLEAN] = {
287 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE,
288 .domain = DOMAIN_KERNEL,
289 },
290#endif
291 [MT_LOW_VECTORS] = {
292 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
293 L_PTE_RDONLY,
294 .prot_l1 = PMD_TYPE_TABLE,
295 .domain = DOMAIN_VECTORS,
296 },
297 [MT_HIGH_VECTORS] = {
298 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
299 L_PTE_USER | L_PTE_RDONLY,
300 .prot_l1 = PMD_TYPE_TABLE,
301 .domain = DOMAIN_VECTORS,
302 },
303 [MT_MEMORY_RWX] = {
304 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
305 .prot_l1 = PMD_TYPE_TABLE,
306 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
307 .domain = DOMAIN_KERNEL,
308 },
309 [MT_MEMORY_RW] = {
310 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
311 L_PTE_XN,
312 .prot_l1 = PMD_TYPE_TABLE,
313 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
314 .domain = DOMAIN_KERNEL,
315 },
316 [MT_ROM] = {
317 .prot_sect = PMD_TYPE_SECT,
318 .domain = DOMAIN_KERNEL,
319 },
320 [MT_MEMORY_RWX_NONCACHED] = {
321 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
322 L_PTE_MT_BUFFERABLE,
323 .prot_l1 = PMD_TYPE_TABLE,
324 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE,
325 .domain = DOMAIN_KERNEL,
326 },
327 [MT_MEMORY_RW_DTCM] = {
328 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
329 L_PTE_XN,
330 .prot_l1 = PMD_TYPE_TABLE,
331 .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN,
332 .domain = DOMAIN_KERNEL,
333 },
334 [MT_MEMORY_RWX_ITCM] = {
335 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY,
336 .prot_l1 = PMD_TYPE_TABLE,
337 .domain = DOMAIN_KERNEL,
338 },
339 [MT_MEMORY_RW_SO] = {
340 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
341 L_PTE_MT_UNCACHED | L_PTE_XN,
342 .prot_l1 = PMD_TYPE_TABLE,
343 .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S |
344 PMD_SECT_UNCACHED | PMD_SECT_XN,
345 .domain = DOMAIN_KERNEL,
346 },
347 [MT_MEMORY_DMA_READY] = {
348 .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
349 L_PTE_XN,
350 .prot_l1 = PMD_TYPE_TABLE,
351 .domain = DOMAIN_KERNEL,
352 },
353};
354
355const struct mem_type *get_mem_type(unsigned int type)
356{
357 return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL;
358}
359EXPORT_SYMBOL(get_mem_type);
360
361static pte_t *(*pte_offset_fixmap)(pmd_t *dir, unsigned long addr);
362
363static pte_t bm_pte[PTRS_PER_PTE + PTE_HWTABLE_PTRS]
364 __aligned(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE) __initdata;
365
366static pte_t * __init pte_offset_early_fixmap(pmd_t *dir, unsigned long addr)
367{
368 return &bm_pte[pte_index(addr)];
369}
370
371static pte_t *pte_offset_late_fixmap(pmd_t *dir, unsigned long addr)
372{
373 return pte_offset_kernel(dir, addr);
374}
375
376static inline pmd_t * __init fixmap_pmd(unsigned long addr)
377{
378 pgd_t *pgd = pgd_offset_k(addr);
379 pud_t *pud = pud_offset(pgd, addr);
380 pmd_t *pmd = pmd_offset(pud, addr);
381
382 return pmd;
383}
384
385void __init early_fixmap_init(void)
386{
387 pmd_t *pmd;
388
389
390
391
392
393 BUILD_BUG_ON((__fix_to_virt(__end_of_early_ioremap_region) >> PMD_SHIFT)
394 != FIXADDR_TOP >> PMD_SHIFT);
395
396 pmd = fixmap_pmd(FIXADDR_TOP);
397 pmd_populate_kernel(&init_mm, pmd, bm_pte);
398
399 pte_offset_fixmap = pte_offset_early_fixmap;
400}
401
402
403
404
405
406
407void __set_fixmap(enum fixed_addresses idx, phys_addr_t phys, pgprot_t prot)
408{
409 unsigned long vaddr = __fix_to_virt(idx);
410 pte_t *pte = pte_offset_fixmap(pmd_off_k(vaddr), vaddr);
411
412
413 BUILD_BUG_ON(FIXADDR_START + (__end_of_fixed_addresses * PAGE_SIZE) >
414 FIXADDR_END);
415 BUG_ON(idx >= __end_of_fixed_addresses);
416
417 if (pgprot_val(prot))
418 set_pte_at(NULL, vaddr, pte,
419 pfn_pte(phys >> PAGE_SHIFT, prot));
420 else
421 pte_clear(NULL, vaddr, pte);
422 local_flush_tlb_kernel_range(vaddr, vaddr + PAGE_SIZE);
423}
424
425
426
427
428static void __init build_mem_type_table(void)
429{
430 struct cachepolicy *cp;
431 unsigned int cr = get_cr();
432 pteval_t user_pgprot, kern_pgprot, vecs_pgprot;
433 pteval_t hyp_device_pgprot, s2_pgprot, s2_device_pgprot;
434 int cpu_arch = cpu_architecture();
435 int i;
436
437 if (cpu_arch < CPU_ARCH_ARMv6) {
438#if defined(CONFIG_CPU_DCACHE_DISABLE)
439 if (cachepolicy > CPOLICY_BUFFERED)
440 cachepolicy = CPOLICY_BUFFERED;
441#elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH)
442 if (cachepolicy > CPOLICY_WRITETHROUGH)
443 cachepolicy = CPOLICY_WRITETHROUGH;
444#endif
445 }
446 if (cpu_arch < CPU_ARCH_ARMv5) {
447 if (cachepolicy >= CPOLICY_WRITEALLOC)
448 cachepolicy = CPOLICY_WRITEBACK;
449 ecc_mask = 0;
450 }
451
452 if (is_smp()) {
453 if (cachepolicy != CPOLICY_WRITEALLOC) {
454 pr_warn("Forcing write-allocate cache policy for SMP\n");
455 cachepolicy = CPOLICY_WRITEALLOC;
456 }
457 if (!(initial_pmd_value & PMD_SECT_S)) {
458 pr_warn("Forcing shared mappings for SMP\n");
459 initial_pmd_value |= PMD_SECT_S;
460 }
461 }
462
463
464
465
466
467
468 if (cpu_arch < CPU_ARCH_ARMv5)
469 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
470 mem_types[i].prot_sect &= ~PMD_SECT_TEX(7);
471 if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3())
472 for (i = 0; i < ARRAY_SIZE(mem_types); i++)
473 mem_types[i].prot_sect &= ~PMD_SECT_S;
474
475
476
477
478
479
480 if (cpu_is_xscale_family()) {
481 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
482 mem_types[i].prot_sect &= ~PMD_BIT4;
483 mem_types[i].prot_l1 &= ~PMD_BIT4;
484 }
485 } else if (cpu_arch < CPU_ARCH_ARMv6) {
486 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
487 if (mem_types[i].prot_l1)
488 mem_types[i].prot_l1 |= PMD_BIT4;
489 if (mem_types[i].prot_sect)
490 mem_types[i].prot_sect |= PMD_BIT4;
491 }
492 }
493
494
495
496
497 if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) {
498 if (!cpu_is_xsc3()) {
499
500
501
502
503 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN;
504 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN;
505 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN;
506 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN;
507
508
509 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_XN;
510 }
511 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
512
513
514
515
516
517
518
519 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1);
520 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1);
521 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
522 } else if (cpu_is_xsc3()) {
523
524
525
526
527
528
529
530 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED;
531 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
532 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
533 } else {
534
535
536
537
538
539
540
541 mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED;
542 mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2);
543 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1);
544 }
545 } else {
546
547
548
549 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE;
550 }
551
552
553
554
555 cp = &cache_policies[cachepolicy];
556 vecs_pgprot = kern_pgprot = user_pgprot = cp->pte;
557 s2_pgprot = cp->pte_s2;
558 hyp_device_pgprot = mem_types[MT_DEVICE].prot_pte;
559 s2_device_pgprot = mem_types[MT_DEVICE].prot_pte_s2;
560
561#ifndef CONFIG_ARM_LPAE
562
563
564
565
566
567 if (cpu_arch == CPU_ARCH_ARMv6)
568 vecs_pgprot |= L_PTE_MT_VECTORS;
569
570
571
572
573
574 if (cpu_arch == CPU_ARCH_ARMv7 &&
575 (read_cpuid_ext(CPUID_EXT_MMFR0) & 0xF) >= 4) {
576 user_pmd_table |= PMD_PXNTABLE;
577 }
578#endif
579
580
581
582
583 if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) {
584#ifndef CONFIG_ARM_LPAE
585
586
587
588
589 mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
590 mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
591 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE;
592#endif
593
594
595
596
597
598
599 if (initial_pmd_value & PMD_SECT_S) {
600 user_pgprot |= L_PTE_SHARED;
601 kern_pgprot |= L_PTE_SHARED;
602 vecs_pgprot |= L_PTE_SHARED;
603 s2_pgprot |= L_PTE_SHARED;
604 mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S;
605 mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED;
606 mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S;
607 mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED;
608 mem_types[MT_MEMORY_RWX].prot_sect |= PMD_SECT_S;
609 mem_types[MT_MEMORY_RWX].prot_pte |= L_PTE_SHARED;
610 mem_types[MT_MEMORY_RW].prot_sect |= PMD_SECT_S;
611 mem_types[MT_MEMORY_RW].prot_pte |= L_PTE_SHARED;
612 mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED;
613 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_S;
614 mem_types[MT_MEMORY_RWX_NONCACHED].prot_pte |= L_PTE_SHARED;
615 }
616 }
617
618
619
620
621
622 if (cpu_arch >= CPU_ARCH_ARMv6) {
623 if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) {
624
625 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
626 PMD_SECT_BUFFERED;
627 } else {
628
629 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |=
630 PMD_SECT_TEX(1);
631 }
632 } else {
633 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE;
634 }
635
636#ifdef CONFIG_ARM_LPAE
637
638
639
640 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
641 mem_types[i].prot_pte |= PTE_EXT_AF;
642 if (mem_types[i].prot_sect)
643 mem_types[i].prot_sect |= PMD_SECT_AF;
644 }
645 kern_pgprot |= PTE_EXT_AF;
646 vecs_pgprot |= PTE_EXT_AF;
647
648
649
650
651 user_pgprot |= PTE_EXT_PXN;
652#endif
653
654 for (i = 0; i < 16; i++) {
655 pteval_t v = pgprot_val(protection_map[i]);
656 protection_map[i] = __pgprot(v | user_pgprot);
657 }
658
659 mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot;
660 mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot;
661
662 pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot);
663 pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG |
664 L_PTE_DIRTY | kern_pgprot);
665 pgprot_s2 = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | s2_pgprot);
666 pgprot_s2_device = __pgprot(s2_device_pgprot);
667 pgprot_hyp_device = __pgprot(hyp_device_pgprot);
668
669 mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask;
670 mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask;
671 mem_types[MT_MEMORY_RWX].prot_sect |= ecc_mask | cp->pmd;
672 mem_types[MT_MEMORY_RWX].prot_pte |= kern_pgprot;
673 mem_types[MT_MEMORY_RW].prot_sect |= ecc_mask | cp->pmd;
674 mem_types[MT_MEMORY_RW].prot_pte |= kern_pgprot;
675 mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot;
676 mem_types[MT_MEMORY_RWX_NONCACHED].prot_sect |= ecc_mask;
677 mem_types[MT_ROM].prot_sect |= cp->pmd;
678
679 switch (cp->pmd) {
680 case PMD_SECT_WT:
681 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT;
682 break;
683 case PMD_SECT_WB:
684 case PMD_SECT_WBWA:
685 mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB;
686 break;
687 }
688 pr_info("Memory policy: %sData cache %s\n",
689 ecc_mask ? "ECC enabled, " : "", cp->policy);
690
691 for (i = 0; i < ARRAY_SIZE(mem_types); i++) {
692 struct mem_type *t = &mem_types[i];
693 if (t->prot_l1)
694 t->prot_l1 |= PMD_DOMAIN(t->domain);
695 if (t->prot_sect)
696 t->prot_sect |= PMD_DOMAIN(t->domain);
697 }
698}
699
700#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
701pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
702 unsigned long size, pgprot_t vma_prot)
703{
704 if (!pfn_valid(pfn))
705 return pgprot_noncached(vma_prot);
706 else if (file->f_flags & O_SYNC)
707 return pgprot_writecombine(vma_prot);
708 return vma_prot;
709}
710EXPORT_SYMBOL(phys_mem_access_prot);
711#endif
712
713#define vectors_base() (vectors_high() ? 0xffff0000 : 0)
714
715static void __init *early_alloc_aligned(unsigned long sz, unsigned long align)
716{
717 void *ptr = __va(memblock_alloc(sz, align));
718 memset(ptr, 0, sz);
719 return ptr;
720}
721
722static void __init *early_alloc(unsigned long sz)
723{
724 return early_alloc_aligned(sz, sz);
725}
726
727static void *__init late_alloc(unsigned long sz)
728{
729 void *ptr = (void *)__get_free_pages(PGALLOC_GFP, get_order(sz));
730
731 BUG_ON(!ptr);
732 return ptr;
733}
734
735static pte_t * __init arm_pte_alloc(pmd_t *pmd, unsigned long addr,
736 unsigned long prot,
737 void *(*alloc)(unsigned long sz))
738{
739 if (pmd_none(*pmd)) {
740 pte_t *pte = alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE);
741 __pmd_populate(pmd, __pa(pte), prot);
742 }
743 BUG_ON(pmd_bad(*pmd));
744 return pte_offset_kernel(pmd, addr);
745}
746
747static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr,
748 unsigned long prot)
749{
750 return arm_pte_alloc(pmd, addr, prot, early_alloc);
751}
752
753static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr,
754 unsigned long end, unsigned long pfn,
755 const struct mem_type *type,
756 void *(*alloc)(unsigned long sz),
757 bool ng)
758{
759 pte_t *pte = arm_pte_alloc(pmd, addr, type->prot_l1, alloc);
760 do {
761 set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)),
762 ng ? PTE_EXT_NG : 0);
763 pfn++;
764 } while (pte++, addr += PAGE_SIZE, addr != end);
765}
766
767static void __init __map_init_section(pmd_t *pmd, unsigned long addr,
768 unsigned long end, phys_addr_t phys,
769 const struct mem_type *type, bool ng)
770{
771 pmd_t *p = pmd;
772
773#ifndef CONFIG_ARM_LPAE
774
775
776
777
778
779
780
781
782
783 if (addr & SECTION_SIZE)
784 pmd++;
785#endif
786 do {
787 *pmd = __pmd(phys | type->prot_sect | (ng ? PMD_SECT_nG : 0));
788 phys += SECTION_SIZE;
789 } while (pmd++, addr += SECTION_SIZE, addr != end);
790
791 flush_pmd_entry(p);
792}
793
794static void __init alloc_init_pmd(pud_t *pud, unsigned long addr,
795 unsigned long end, phys_addr_t phys,
796 const struct mem_type *type,
797 void *(*alloc)(unsigned long sz), bool ng)
798{
799 pmd_t *pmd = pmd_offset(pud, addr);
800 unsigned long next;
801
802 do {
803
804
805
806
807 next = pmd_addr_end(addr, end);
808
809
810
811
812
813 if (type->prot_sect &&
814 ((addr | next | phys) & ~SECTION_MASK) == 0) {
815 __map_init_section(pmd, addr, next, phys, type, ng);
816 } else {
817 alloc_init_pte(pmd, addr, next,
818 __phys_to_pfn(phys), type, alloc, ng);
819 }
820
821 phys += next - addr;
822
823 } while (pmd++, addr = next, addr != end);
824}
825
826static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr,
827 unsigned long end, phys_addr_t phys,
828 const struct mem_type *type,
829 void *(*alloc)(unsigned long sz), bool ng)
830{
831 pud_t *pud = pud_offset(pgd, addr);
832 unsigned long next;
833
834 do {
835 next = pud_addr_end(addr, end);
836 alloc_init_pmd(pud, addr, next, phys, type, alloc, ng);
837 phys += next - addr;
838 } while (pud++, addr = next, addr != end);
839}
840
841#ifndef CONFIG_ARM_LPAE
842static void __init create_36bit_mapping(struct mm_struct *mm,
843 struct map_desc *md,
844 const struct mem_type *type,
845 bool ng)
846{
847 unsigned long addr, length, end;
848 phys_addr_t phys;
849 pgd_t *pgd;
850
851 addr = md->virtual;
852 phys = __pfn_to_phys(md->pfn);
853 length = PAGE_ALIGN(md->length);
854
855 if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) {
856 pr_err("MM: CPU does not support supersection mapping for 0x%08llx at 0x%08lx\n",
857 (long long)__pfn_to_phys((u64)md->pfn), addr);
858 return;
859 }
860
861
862
863
864
865
866
867 if (type->domain) {
868 pr_err("MM: invalid domain in supersection mapping for 0x%08llx at 0x%08lx\n",
869 (long long)__pfn_to_phys((u64)md->pfn), addr);
870 return;
871 }
872
873 if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) {
874 pr_err("MM: cannot create mapping for 0x%08llx at 0x%08lx invalid alignment\n",
875 (long long)__pfn_to_phys((u64)md->pfn), addr);
876 return;
877 }
878
879
880
881
882
883 phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20);
884
885 pgd = pgd_offset(mm, addr);
886 end = addr + length;
887 do {
888 pud_t *pud = pud_offset(pgd, addr);
889 pmd_t *pmd = pmd_offset(pud, addr);
890 int i;
891
892 for (i = 0; i < 16; i++)
893 *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER |
894 (ng ? PMD_SECT_nG : 0));
895
896 addr += SUPERSECTION_SIZE;
897 phys += SUPERSECTION_SIZE;
898 pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT;
899 } while (addr != end);
900}
901#endif
902
903static void __init __create_mapping(struct mm_struct *mm, struct map_desc *md,
904 void *(*alloc)(unsigned long sz),
905 bool ng)
906{
907 unsigned long addr, length, end;
908 phys_addr_t phys;
909 const struct mem_type *type;
910 pgd_t *pgd;
911
912 type = &mem_types[md->type];
913
914#ifndef CONFIG_ARM_LPAE
915
916
917
918 if (md->pfn >= 0x100000) {
919 create_36bit_mapping(mm, md, type, ng);
920 return;
921 }
922#endif
923
924 addr = md->virtual & PAGE_MASK;
925 phys = __pfn_to_phys(md->pfn);
926 length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
927
928 if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) {
929 pr_warn("BUG: map for 0x%08llx at 0x%08lx can not be mapped using pages, ignoring.\n",
930 (long long)__pfn_to_phys(md->pfn), addr);
931 return;
932 }
933
934 pgd = pgd_offset(mm, addr);
935 end = addr + length;
936 do {
937 unsigned long next = pgd_addr_end(addr, end);
938
939 alloc_init_pud(pgd, addr, next, phys, type, alloc, ng);
940
941 phys += next - addr;
942 addr = next;
943 } while (pgd++, addr != end);
944}
945
946
947
948
949
950
951
952
953static void __init create_mapping(struct map_desc *md)
954{
955 if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) {
956 pr_warn("BUG: not creating mapping for 0x%08llx at 0x%08lx in user region\n",
957 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
958 return;
959 }
960
961 if ((md->type == MT_DEVICE || md->type == MT_ROM) &&
962 md->virtual >= PAGE_OFFSET && md->virtual < FIXADDR_START &&
963 (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) {
964 pr_warn("BUG: mapping for 0x%08llx at 0x%08lx out of vmalloc space\n",
965 (long long)__pfn_to_phys((u64)md->pfn), md->virtual);
966 }
967
968 __create_mapping(&init_mm, md, early_alloc, false);
969}
970
971void __init create_mapping_late(struct mm_struct *mm, struct map_desc *md,
972 bool ng)
973{
974#ifdef CONFIG_ARM_LPAE
975 pud_t *pud = pud_alloc(mm, pgd_offset(mm, md->virtual), md->virtual);
976 if (WARN_ON(!pud))
977 return;
978 pmd_alloc(mm, pud, 0);
979#endif
980 __create_mapping(mm, md, late_alloc, ng);
981}
982
983
984
985
986void __init iotable_init(struct map_desc *io_desc, int nr)
987{
988 struct map_desc *md;
989 struct vm_struct *vm;
990 struct static_vm *svm;
991
992 if (!nr)
993 return;
994
995 svm = early_alloc_aligned(sizeof(*svm) * nr, __alignof__(*svm));
996
997 for (md = io_desc; nr; md++, nr--) {
998 create_mapping(md);
999
1000 vm = &svm->vm;
1001 vm->addr = (void *)(md->virtual & PAGE_MASK);
1002 vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK));
1003 vm->phys_addr = __pfn_to_phys(md->pfn);
1004 vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING;
1005 vm->flags |= VM_ARM_MTYPE(md->type);
1006 vm->caller = iotable_init;
1007 add_static_vm_early(svm++);
1008 }
1009}
1010
1011void __init vm_reserve_area_early(unsigned long addr, unsigned long size,
1012 void *caller)
1013{
1014 struct vm_struct *vm;
1015 struct static_vm *svm;
1016
1017 svm = early_alloc_aligned(sizeof(*svm), __alignof__(*svm));
1018
1019 vm = &svm->vm;
1020 vm->addr = (void *)addr;
1021 vm->size = size;
1022 vm->flags = VM_IOREMAP | VM_ARM_EMPTY_MAPPING;
1023 vm->caller = caller;
1024 add_static_vm_early(svm);
1025}
1026
1027#ifndef CONFIG_ARM_LPAE
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042static void __init pmd_empty_section_gap(unsigned long addr)
1043{
1044 vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap);
1045}
1046
1047static void __init fill_pmd_gaps(void)
1048{
1049 struct static_vm *svm;
1050 struct vm_struct *vm;
1051 unsigned long addr, next = 0;
1052 pmd_t *pmd;
1053
1054 list_for_each_entry(svm, &static_vmlist, list) {
1055 vm = &svm->vm;
1056 addr = (unsigned long)vm->addr;
1057 if (addr < next)
1058 continue;
1059
1060
1061
1062
1063
1064
1065 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1066 pmd = pmd_off_k(addr);
1067 if (pmd_none(*pmd))
1068 pmd_empty_section_gap(addr & PMD_MASK);
1069 }
1070
1071
1072
1073
1074
1075
1076 addr += vm->size;
1077 if ((addr & ~PMD_MASK) == SECTION_SIZE) {
1078 pmd = pmd_off_k(addr) + 1;
1079 if (pmd_none(*pmd))
1080 pmd_empty_section_gap(addr);
1081 }
1082
1083
1084 next = (addr + PMD_SIZE - 1) & PMD_MASK;
1085 }
1086}
1087
1088#else
1089#define fill_pmd_gaps() do { } while (0)
1090#endif
1091
1092#if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H)
1093static void __init pci_reserve_io(void)
1094{
1095 struct static_vm *svm;
1096
1097 svm = find_static_vm_vaddr((void *)PCI_IO_VIRT_BASE);
1098 if (svm)
1099 return;
1100
1101 vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io);
1102}
1103#else
1104#define pci_reserve_io() do { } while (0)
1105#endif
1106
1107#ifdef CONFIG_DEBUG_LL
1108void __init debug_ll_io_init(void)
1109{
1110 struct map_desc map;
1111
1112 debug_ll_addr(&map.pfn, &map.virtual);
1113 if (!map.pfn || !map.virtual)
1114 return;
1115 map.pfn = __phys_to_pfn(map.pfn);
1116 map.virtual &= PAGE_MASK;
1117 map.length = PAGE_SIZE;
1118 map.type = MT_DEVICE;
1119 iotable_init(&map, 1);
1120}
1121#endif
1122
1123static void * __initdata vmalloc_min =
1124 (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
1125
1126
1127
1128
1129
1130
1131static int __init early_vmalloc(char *arg)
1132{
1133 unsigned long vmalloc_reserve = memparse(arg, NULL);
1134
1135 if (vmalloc_reserve < SZ_16M) {
1136 vmalloc_reserve = SZ_16M;
1137 pr_warn("vmalloc area too small, limiting to %luMB\n",
1138 vmalloc_reserve >> 20);
1139 }
1140
1141 if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) {
1142 vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M);
1143 pr_warn("vmalloc area is too big, limiting to %luMB\n",
1144 vmalloc_reserve >> 20);
1145 }
1146
1147 vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
1148 return 0;
1149}
1150early_param("vmalloc", early_vmalloc);
1151
1152phys_addr_t arm_lowmem_limit __initdata = 0;
1153
1154void __init sanity_check_meminfo(void)
1155{
1156 phys_addr_t memblock_limit = 0;
1157 int highmem = 0;
1158 phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
1159 struct memblock_region *reg;
1160 bool should_use_highmem = false;
1161
1162 for_each_memblock(memory, reg) {
1163 phys_addr_t block_start = reg->base;
1164 phys_addr_t block_end = reg->base + reg->size;
1165 phys_addr_t size_limit = reg->size;
1166
1167 if (reg->base >= vmalloc_limit)
1168 highmem = 1;
1169 else
1170 size_limit = vmalloc_limit - reg->base;
1171
1172
1173 if (!IS_ENABLED(CONFIG_HIGHMEM) || cache_is_vipt_aliasing()) {
1174
1175 if (highmem) {
1176 pr_notice("Ignoring RAM at %pa-%pa (!CONFIG_HIGHMEM)\n",
1177 &block_start, &block_end);
1178 memblock_remove(reg->base, reg->size);
1179 should_use_highmem = true;
1180 continue;
1181 }
1182
1183 if (reg->size > size_limit) {
1184 phys_addr_t overlap_size = reg->size - size_limit;
1185
1186 pr_notice("Truncating RAM at %pa-%pa to -%pa",
1187 &block_start, &block_end, &vmalloc_limit);
1188 memblock_remove(vmalloc_limit, overlap_size);
1189 block_end = vmalloc_limit;
1190 should_use_highmem = true;
1191 }
1192 }
1193
1194 if (!highmem) {
1195 if (block_end > arm_lowmem_limit) {
1196 if (reg->size > size_limit)
1197 arm_lowmem_limit = vmalloc_limit;
1198 else
1199 arm_lowmem_limit = block_end;
1200 }
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215 if (!memblock_limit) {
1216 if (!IS_ALIGNED(block_start, PMD_SIZE))
1217 memblock_limit = block_start;
1218 else if (!IS_ALIGNED(block_end, PMD_SIZE))
1219 memblock_limit = arm_lowmem_limit;
1220 }
1221
1222 }
1223 }
1224
1225 if (should_use_highmem)
1226 pr_notice("Consider using a HIGHMEM enabled kernel.\n");
1227
1228 high_memory = __va(arm_lowmem_limit - 1) + 1;
1229
1230
1231
1232
1233
1234
1235 if (memblock_limit)
1236 memblock_limit = round_down(memblock_limit, PMD_SIZE);
1237 if (!memblock_limit)
1238 memblock_limit = arm_lowmem_limit;
1239
1240 memblock_set_current_limit(memblock_limit);
1241}
1242
1243static inline void prepare_page_table(void)
1244{
1245 unsigned long addr;
1246 phys_addr_t end;
1247
1248
1249
1250
1251 for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE)
1252 pmd_clear(pmd_off_k(addr));
1253
1254#ifdef CONFIG_XIP_KERNEL
1255
1256 addr = ((unsigned long)_exiprom + PMD_SIZE - 1) & PMD_MASK;
1257#endif
1258 for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE)
1259 pmd_clear(pmd_off_k(addr));
1260
1261
1262
1263
1264 end = memblock.memory.regions[0].base + memblock.memory.regions[0].size;
1265 if (end >= arm_lowmem_limit)
1266 end = arm_lowmem_limit;
1267
1268
1269
1270
1271
1272 for (addr = __phys_to_virt(end);
1273 addr < VMALLOC_START; addr += PMD_SIZE)
1274 pmd_clear(pmd_off_k(addr));
1275}
1276
1277#ifdef CONFIG_ARM_LPAE
1278
1279#define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \
1280 PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t))
1281#else
1282#define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t))
1283#endif
1284
1285
1286
1287
1288void __init arm_mm_memblock_reserve(void)
1289{
1290
1291
1292
1293
1294 memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE);
1295
1296#ifdef CONFIG_SA1111
1297
1298
1299
1300
1301 memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET);
1302#endif
1303}
1304
1305
1306
1307
1308
1309
1310
1311
1312static void __init devicemaps_init(const struct machine_desc *mdesc)
1313{
1314 struct map_desc map;
1315 unsigned long addr;
1316 void *vectors;
1317
1318
1319
1320
1321 vectors = early_alloc(PAGE_SIZE * 2);
1322
1323 early_trap_init(vectors);
1324
1325
1326
1327
1328 for (addr = VMALLOC_START; addr < (FIXADDR_TOP & PMD_MASK); addr += PMD_SIZE)
1329 pmd_clear(pmd_off_k(addr));
1330
1331
1332
1333
1334
1335#ifdef CONFIG_XIP_KERNEL
1336 map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK);
1337 map.virtual = MODULES_VADDR;
1338 map.length = ((unsigned long)_exiprom - map.virtual + ~SECTION_MASK) & SECTION_MASK;
1339 map.type = MT_ROM;
1340 create_mapping(&map);
1341#endif
1342
1343
1344
1345
1346#ifdef FLUSH_BASE
1347 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS);
1348 map.virtual = FLUSH_BASE;
1349 map.length = SZ_1M;
1350 map.type = MT_CACHECLEAN;
1351 create_mapping(&map);
1352#endif
1353#ifdef FLUSH_BASE_MINICACHE
1354 map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M);
1355 map.virtual = FLUSH_BASE_MINICACHE;
1356 map.length = SZ_1M;
1357 map.type = MT_MINICLEAN;
1358 create_mapping(&map);
1359#endif
1360
1361
1362
1363
1364
1365
1366 map.pfn = __phys_to_pfn(virt_to_phys(vectors));
1367 map.virtual = 0xffff0000;
1368 map.length = PAGE_SIZE;
1369#ifdef CONFIG_KUSER_HELPERS
1370 map.type = MT_HIGH_VECTORS;
1371#else
1372 map.type = MT_LOW_VECTORS;
1373#endif
1374 create_mapping(&map);
1375
1376 if (!vectors_high()) {
1377 map.virtual = 0;
1378 map.length = PAGE_SIZE * 2;
1379 map.type = MT_LOW_VECTORS;
1380 create_mapping(&map);
1381 }
1382
1383
1384 map.pfn += 1;
1385 map.virtual = 0xffff0000 + PAGE_SIZE;
1386 map.length = PAGE_SIZE;
1387 map.type = MT_LOW_VECTORS;
1388 create_mapping(&map);
1389
1390
1391
1392
1393 if (mdesc->map_io)
1394 mdesc->map_io();
1395 else
1396 debug_ll_io_init();
1397 fill_pmd_gaps();
1398
1399
1400 pci_reserve_io();
1401
1402
1403
1404
1405
1406
1407
1408 local_flush_tlb_all();
1409 flush_cache_all();
1410
1411
1412 early_abt_enable();
1413}
1414
1415static void __init kmap_init(void)
1416{
1417#ifdef CONFIG_HIGHMEM
1418 pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE),
1419 PKMAP_BASE, _PAGE_KERNEL_TABLE);
1420#endif
1421
1422 early_pte_alloc(pmd_off_k(FIXADDR_START), FIXADDR_START,
1423 _PAGE_KERNEL_TABLE);
1424}
1425
1426static void __init map_lowmem(void)
1427{
1428 struct memblock_region *reg;
1429#ifdef CONFIG_XIP_KERNEL
1430 phys_addr_t kernel_x_start = round_down(__pa(_sdata), SECTION_SIZE);
1431#else
1432 phys_addr_t kernel_x_start = round_down(__pa(_stext), SECTION_SIZE);
1433#endif
1434 phys_addr_t kernel_x_end = round_up(__pa(__init_end), SECTION_SIZE);
1435
1436
1437 for_each_memblock(memory, reg) {
1438 phys_addr_t start = reg->base;
1439 phys_addr_t end = start + reg->size;
1440 struct map_desc map;
1441
1442 if (memblock_is_nomap(reg))
1443 continue;
1444
1445 if (end > arm_lowmem_limit)
1446 end = arm_lowmem_limit;
1447 if (start >= end)
1448 break;
1449
1450 if (end < kernel_x_start) {
1451 map.pfn = __phys_to_pfn(start);
1452 map.virtual = __phys_to_virt(start);
1453 map.length = end - start;
1454 map.type = MT_MEMORY_RWX;
1455
1456 create_mapping(&map);
1457 } else if (start >= kernel_x_end) {
1458 map.pfn = __phys_to_pfn(start);
1459 map.virtual = __phys_to_virt(start);
1460 map.length = end - start;
1461 map.type = MT_MEMORY_RW;
1462
1463 create_mapping(&map);
1464 } else {
1465
1466 if (start < kernel_x_start) {
1467 map.pfn = __phys_to_pfn(start);
1468 map.virtual = __phys_to_virt(start);
1469 map.length = kernel_x_start - start;
1470 map.type = MT_MEMORY_RW;
1471
1472 create_mapping(&map);
1473 }
1474
1475 map.pfn = __phys_to_pfn(kernel_x_start);
1476 map.virtual = __phys_to_virt(kernel_x_start);
1477 map.length = kernel_x_end - kernel_x_start;
1478 map.type = MT_MEMORY_RWX;
1479
1480 create_mapping(&map);
1481
1482 if (kernel_x_end < end) {
1483 map.pfn = __phys_to_pfn(kernel_x_end);
1484 map.virtual = __phys_to_virt(kernel_x_end);
1485 map.length = end - kernel_x_end;
1486 map.type = MT_MEMORY_RW;
1487
1488 create_mapping(&map);
1489 }
1490 }
1491 }
1492}
1493
1494#ifdef CONFIG_ARM_PV_FIXUP
1495extern unsigned long __atags_pointer;
1496typedef void pgtables_remap(long long offset, unsigned long pgd, void *bdata);
1497pgtables_remap lpae_pgtables_remap_asm;
1498
1499
1500
1501
1502
1503void __init early_paging_init(const struct machine_desc *mdesc)
1504{
1505 pgtables_remap *lpae_pgtables_remap;
1506 unsigned long pa_pgd;
1507 unsigned int cr, ttbcr;
1508 long long offset;
1509 void *boot_data;
1510
1511 if (!mdesc->pv_fixup)
1512 return;
1513
1514 offset = mdesc->pv_fixup();
1515 if (offset == 0)
1516 return;
1517
1518
1519
1520
1521
1522
1523
1524 lpae_pgtables_remap = (pgtables_remap *)(unsigned long)__pa(lpae_pgtables_remap_asm);
1525 pa_pgd = __pa(swapper_pg_dir);
1526 boot_data = __va(__atags_pointer);
1527 barrier();
1528
1529 pr_info("Switching physical address space to 0x%08llx\n",
1530 (u64)PHYS_OFFSET + offset);
1531
1532
1533 __pv_offset += offset;
1534 __pv_phys_pfn_offset += PFN_DOWN(offset);
1535
1536
1537 fixup_pv_table(&__pv_table_begin,
1538 (&__pv_table_end - &__pv_table_begin) << 2);
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549 cr = get_cr();
1550 set_cr(cr & ~(CR_I | CR_C));
1551 asm("mrc p15, 0, %0, c2, c0, 2" : "=r" (ttbcr));
1552 asm volatile("mcr p15, 0, %0, c2, c0, 2"
1553 : : "r" (ttbcr & ~(3 << 8 | 3 << 10)));
1554 flush_cache_all();
1555
1556
1557
1558
1559
1560
1561
1562 lpae_pgtables_remap(offset, pa_pgd, boot_data);
1563
1564
1565 asm volatile("mcr p15, 0, %0, c2, c0, 2" : : "r" (ttbcr));
1566 set_cr(cr);
1567}
1568
1569#else
1570
1571void __init early_paging_init(const struct machine_desc *mdesc)
1572{
1573 long long offset;
1574
1575 if (!mdesc->pv_fixup)
1576 return;
1577
1578 offset = mdesc->pv_fixup();
1579 if (offset == 0)
1580 return;
1581
1582 pr_crit("Physical address space modification is only to support Keystone2.\n");
1583 pr_crit("Please enable ARM_LPAE and ARM_PATCH_PHYS_VIRT support to use this\n");
1584 pr_crit("feature. Your kernel may crash now, have a good day.\n");
1585 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1586}
1587
1588#endif
1589
1590static void __init early_fixmap_shutdown(void)
1591{
1592 int i;
1593 unsigned long va = fix_to_virt(__end_of_permanent_fixed_addresses - 1);
1594
1595 pte_offset_fixmap = pte_offset_late_fixmap;
1596 pmd_clear(fixmap_pmd(va));
1597 local_flush_tlb_kernel_page(va);
1598
1599 for (i = 0; i < __end_of_permanent_fixed_addresses; i++) {
1600 pte_t *pte;
1601 struct map_desc map;
1602
1603 map.virtual = fix_to_virt(i);
1604 pte = pte_offset_early_fixmap(pmd_off_k(map.virtual), map.virtual);
1605
1606
1607 if (pte_none(*pte) ||
1608 (pte_val(*pte) & L_PTE_MT_MASK) != L_PTE_MT_DEV_SHARED)
1609 continue;
1610
1611 map.pfn = pte_pfn(*pte);
1612 map.type = MT_DEVICE;
1613 map.length = PAGE_SIZE;
1614
1615 create_mapping(&map);
1616 }
1617}
1618
1619
1620
1621
1622
1623void __init paging_init(const struct machine_desc *mdesc)
1624{
1625 void *zero_page;
1626
1627 build_mem_type_table();
1628 prepare_page_table();
1629 map_lowmem();
1630 memblock_set_current_limit(arm_lowmem_limit);
1631 dma_contiguous_remap();
1632 early_fixmap_shutdown();
1633 devicemaps_init(mdesc);
1634 kmap_init();
1635 tcm_init();
1636
1637 top_pmd = pmd_off_k(0xffff0000);
1638
1639
1640 zero_page = early_alloc(PAGE_SIZE);
1641
1642 bootmem_init();
1643
1644 empty_zero_page = virt_to_page(zero_page);
1645 __flush_dcache_page(NULL, empty_zero_page);
1646}
1647