LXR linux/arch/ia64/kernel/head.S

   1/*
   2 * Here is where the ball gets rolling as far as the kernel is concerned.
   3 * When control is transferred to _start, the bootload has already
   4 * loaded us to the correct address.  All that's left to do here is
   5 * to set up the kernel's global pointer and jump to the kernel
   6 * entry point.
   7 *
   8 * Copyright (C) 1998-2001, 2003, 2005 Hewlett-Packard Co
   9 *      David Mosberger-Tang <davidm@hpl.hp.com>
  10 *      Stephane Eranian <eranian@hpl.hp.com>
  11 * Copyright (C) 1999 VA Linux Systems
  12 * Copyright (C) 1999 Walt Drummond <drummond@valinux.com>
  13 * Copyright (C) 1999 Intel Corp.
  14 * Copyright (C) 1999 Asit Mallick <Asit.K.Mallick@intel.com>
  15 * Copyright (C) 1999 Don Dugger <Don.Dugger@intel.com>
  16 * Copyright (C) 2002 Fenghua Yu <fenghua.yu@intel.com>
  17 *   -Optimize __ia64_save_fpu() and __ia64_load_fpu() for Itanium 2.
  18 * Copyright (C) 2004 Ashok Raj <ashok.raj@intel.com>
  19 *   Support for CPU Hotplug
  20 */
  21
  22
  23#include <asm/asmmacro.h>
  24#include <asm/fpu.h>
  25#include <asm/kregs.h>
  26#include <asm/mmu_context.h>
  27#include <asm/asm-offsets.h>
  28#include <asm/pal.h>
  29#include <asm/pgtable.h>
  30#include <asm/processor.h>
  31#include <asm/ptrace.h>
  32#include <asm/mca_asm.h>
  33#include <linux/init.h>
  34#include <linux/linkage.h>
  35
  36#ifdef CONFIG_HOTPLUG_CPU
  37#define SAL_PSR_BITS_TO_SET                             \
  38        (IA64_PSR_AC | IA64_PSR_BN | IA64_PSR_MFH | IA64_PSR_MFL)
  39
  40#define SAVE_FROM_REG(src, ptr, dest)   \
  41        mov dest=src;;                                          \
  42        st8 [ptr]=dest,0x08
  43
  44#define RESTORE_REG(reg, ptr, _tmp)             \
  45        ld8 _tmp=[ptr],0x08;;                           \
  46        mov reg=_tmp
  47
  48#define SAVE_BREAK_REGS(ptr, _idx, _breg, _dest)\
  49        mov ar.lc=IA64_NUM_DBG_REGS-1;;                         \
  50        mov _idx=0;;                                                            \
  511:                                                                                              \
  52        SAVE_FROM_REG(_breg[_idx], ptr, _dest);;        \
  53        add _idx=1,_idx;;                                                       \
  54        br.cloop.sptk.many 1b
  55
  56#define RESTORE_BREAK_REGS(ptr, _idx, _breg, _tmp, _lbl)\
  57        mov ar.lc=IA64_NUM_DBG_REGS-1;;                 \
  58        mov _idx=0;;                                                    \
  59_lbl:  RESTORE_REG(_breg[_idx], ptr, _tmp);;    \
  60        add _idx=1, _idx;;                                              \
  61        br.cloop.sptk.many _lbl
  62
  63#define SAVE_ONE_RR(num, _reg, _tmp) \
  64        movl _tmp=(num<<61);;   \
  65        mov _reg=rr[_tmp]
  66
  67#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
  68        SAVE_ONE_RR(0,_r0, _tmp);; \
  69        SAVE_ONE_RR(1,_r1, _tmp);; \
  70        SAVE_ONE_RR(2,_r2, _tmp);; \
  71        SAVE_ONE_RR(3,_r3, _tmp);; \
  72        SAVE_ONE_RR(4,_r4, _tmp);; \
  73        SAVE_ONE_RR(5,_r5, _tmp);; \
  74        SAVE_ONE_RR(6,_r6, _tmp);; \
  75        SAVE_ONE_RR(7,_r7, _tmp);;
  76
  77#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7) \
  78        st8 [ptr]=_r0, 8;; \
  79        st8 [ptr]=_r1, 8;; \
  80        st8 [ptr]=_r2, 8;; \
  81        st8 [ptr]=_r3, 8;; \
  82        st8 [ptr]=_r4, 8;; \
  83        st8 [ptr]=_r5, 8;; \
  84        st8 [ptr]=_r6, 8;; \
  85        st8 [ptr]=_r7, 8;;
  86
  87#define RESTORE_REGION_REGS(ptr, _idx1, _idx2, _tmp) \
  88        mov             ar.lc=0x08-1;;                                          \
  89        movl    _idx1=0x00;;                                            \
  90RestRR:                                                                                 \
  91        dep.z   _idx2=_idx1,61,3;;                                      \
  92        ld8             _tmp=[ptr],8;;                                          \
  93        mov             rr[_idx2]=_tmp;;                                        \
  94        srlz.d;;                                                                        \
  95        add             _idx1=1,_idx1;;                                         \
  96        br.cloop.sptk.few       RestRR
  97
  98#define SET_AREA_FOR_BOOTING_CPU(reg1, reg2) \
  99        movl reg1=sal_state_for_booting_cpu;;   \
 100        ld8 reg2=[reg1];;
 101
 102/*
 103 * Adjust region registers saved before starting to save
 104 * break regs and rest of the states that need to be preserved.
 105 */
 106#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(_reg1,_reg2,_pred)  \
 107        SAVE_FROM_REG(b0,_reg1,_reg2);;                                         \
 108        SAVE_FROM_REG(b1,_reg1,_reg2);;                                         \
 109        SAVE_FROM_REG(b2,_reg1,_reg2);;                                         \
 110        SAVE_FROM_REG(b3,_reg1,_reg2);;                                         \
 111        SAVE_FROM_REG(b4,_reg1,_reg2);;                                         \
 112        SAVE_FROM_REG(b5,_reg1,_reg2);;                                         \
 113        st8 [_reg1]=r1,0x08;;                                                           \
 114        st8 [_reg1]=r12,0x08;;                                                          \
 115        st8 [_reg1]=r13,0x08;;                                                          \
 116        SAVE_FROM_REG(ar.fpsr,_reg1,_reg2);;                            \
 117        SAVE_FROM_REG(ar.pfs,_reg1,_reg2);;                                     \
 118        SAVE_FROM_REG(ar.rnat,_reg1,_reg2);;                            \
 119        SAVE_FROM_REG(ar.unat,_reg1,_reg2);;                            \
 120        SAVE_FROM_REG(ar.bspstore,_reg1,_reg2);;                        \
 121        SAVE_FROM_REG(cr.dcr,_reg1,_reg2);;                                     \
 122        SAVE_FROM_REG(cr.iva,_reg1,_reg2);;                                     \
 123        SAVE_FROM_REG(cr.pta,_reg1,_reg2);;                                     \
 124        SAVE_FROM_REG(cr.itv,_reg1,_reg2);;                                     \
 125        SAVE_FROM_REG(cr.pmv,_reg1,_reg2);;                                     \
 126        SAVE_FROM_REG(cr.cmcv,_reg1,_reg2);;                            \
 127        SAVE_FROM_REG(cr.lrr0,_reg1,_reg2);;                            \
 128        SAVE_FROM_REG(cr.lrr1,_reg1,_reg2);;                            \
 129        st8 [_reg1]=r4,0x08;;                                                           \
 130        st8 [_reg1]=r5,0x08;;                                                           \
 131        st8 [_reg1]=r6,0x08;;                                                           \
 132        st8 [_reg1]=r7,0x08;;                                                           \
 133        st8 [_reg1]=_pred,0x08;;                                                        \
 134        SAVE_FROM_REG(ar.lc, _reg1, _reg2);;                            \
 135        stf.spill.nta [_reg1]=f2,16;;                                           \
 136        stf.spill.nta [_reg1]=f3,16;;                                           \
 137        stf.spill.nta [_reg1]=f4,16;;                                           \
 138        stf.spill.nta [_reg1]=f5,16;;                                           \
 139        stf.spill.nta [_reg1]=f16,16;;                                          \
 140        stf.spill.nta [_reg1]=f17,16;;                                          \
 141        stf.spill.nta [_reg1]=f18,16;;                                          \
 142        stf.spill.nta [_reg1]=f19,16;;                                          \
 143        stf.spill.nta [_reg1]=f20,16;;                                          \
 144        stf.spill.nta [_reg1]=f21,16;;                                          \
 145        stf.spill.nta [_reg1]=f22,16;;                                          \
 146        stf.spill.nta [_reg1]=f23,16;;                                          \
 147        stf.spill.nta [_reg1]=f24,16;;                                          \
 148        stf.spill.nta [_reg1]=f25,16;;                                          \
 149        stf.spill.nta [_reg1]=f26,16;;                                          \
 150        stf.spill.nta [_reg1]=f27,16;;                                          \
 151        stf.spill.nta [_reg1]=f28,16;;                                          \
 152        stf.spill.nta [_reg1]=f29,16;;                                          \
 153        stf.spill.nta [_reg1]=f30,16;;                                          \
 154        stf.spill.nta [_reg1]=f31,16;;
 155
 156#else
 157#define SET_AREA_FOR_BOOTING_CPU(a1, a2)
 158#define SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(a1,a2, a3)
 159#define SAVE_REGION_REGS(_tmp, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
 160#define STORE_REGION_REGS(ptr, _r0, _r1, _r2, _r3, _r4, _r5, _r6, _r7)
 161#endif
 162
 163#define SET_ONE_RR(num, pgsize, _tmp1, _tmp2, vhpt) \
 164        movl _tmp1=(num << 61);;        \
 165        mov _tmp2=((ia64_rid(IA64_REGION_ID_KERNEL, (num<<61)) << 8) | (pgsize << 2) | vhpt);; \
 166        mov rr[_tmp1]=_tmp2
 167
 168        __PAGE_ALIGNED_DATA
 169
 170        .global empty_zero_page
 171empty_zero_page:
 172        .skip PAGE_SIZE
 173
 174        .global swapper_pg_dir
 175swapper_pg_dir:
 176        .skip PAGE_SIZE
 177
 178        .rodata
 179halt_msg:
 180        stringz "Halting kernel\n"
 181
 182        __REF
 183
 184        .global start_ap
 185
 186        /*
 187         * Start the kernel.  When the bootloader passes control to _start(), r28
 188         * points to the address of the boot parameter area.  Execution reaches
 189         * here in physical mode.
 190         */
 191GLOBAL_ENTRY(_start)
 192start_ap:
 193        .prologue
 194        .save rp, r0            // terminate unwind chain with a NULL rp
 195        .body
 196
 197        rsm psr.i | psr.ic
 198        ;;
 199        srlz.i
 200        ;;
 201 {
 202        flushrs                         // must be first insn in group
 203        srlz.i
 204 }
 205        ;;
 206        /*
 207         * Save the region registers, predicate before they get clobbered
 208         */
 209        SAVE_REGION_REGS(r2, r8,r9,r10,r11,r12,r13,r14,r15);
 210        mov r25=pr;;
 211
 212        /*
 213         * Initialize kernel region registers:
 214         *      rr[0]: VHPT enabled, page size = PAGE_SHIFT
 215         *      rr[1]: VHPT enabled, page size = PAGE_SHIFT
 216         *      rr[2]: VHPT enabled, page size = PAGE_SHIFT
 217         *      rr[3]: VHPT enabled, page size = PAGE_SHIFT
 218         *      rr[4]: VHPT enabled, page size = PAGE_SHIFT
 219         *      rr[5]: VHPT enabled, page size = PAGE_SHIFT
 220         *      rr[6]: VHPT disabled, page size = IA64_GRANULE_SHIFT
 221         *      rr[7]: VHPT disabled, page size = IA64_GRANULE_SHIFT
 222         * We initialize all of them to prevent inadvertently assuming
 223         * something about the state of address translation early in boot.
 224         */
 225        SET_ONE_RR(0, PAGE_SHIFT, r2, r16, 1);;
 226        SET_ONE_RR(1, PAGE_SHIFT, r2, r16, 1);;
 227        SET_ONE_RR(2, PAGE_SHIFT, r2, r16, 1);;
 228        SET_ONE_RR(3, PAGE_SHIFT, r2, r16, 1);;
 229        SET_ONE_RR(4, PAGE_SHIFT, r2, r16, 1);;
 230        SET_ONE_RR(5, PAGE_SHIFT, r2, r16, 1);;
 231        SET_ONE_RR(6, IA64_GRANULE_SHIFT, r2, r16, 0);;
 232        SET_ONE_RR(7, IA64_GRANULE_SHIFT, r2, r16, 0);;
 233        /*
 234         * Now pin mappings into the TLB for kernel text and data
 235         */
 236        mov r18=KERNEL_TR_PAGE_SHIFT<<2
 237        movl r17=KERNEL_START
 238        ;;
 239        mov cr.itir=r18
 240        mov cr.ifa=r17
 241        mov r16=IA64_TR_KERNEL
 242        mov r3=ip
 243        movl r18=PAGE_KERNEL
 244        ;;
 245        dep r2=0,r3,0,KERNEL_TR_PAGE_SHIFT
 246        ;;
 247        or r18=r2,r18
 248        ;;
 249        srlz.i
 250        ;;
 251        itr.i itr[r16]=r18
 252        ;;
 253        itr.d dtr[r16]=r18
 254        ;;
 255        srlz.i
 256
 257        /*
 258         * Switch into virtual mode:
 259         */
 260        movl r16=(IA64_PSR_IT|IA64_PSR_IC|IA64_PSR_DT|IA64_PSR_RT|IA64_PSR_DFH|IA64_PSR_BN \
 261                  |IA64_PSR_DI)
 262        ;;
 263        mov cr.ipsr=r16
 264        movl r17=1f
 265        ;;
 266        mov cr.iip=r17
 267        mov cr.ifs=r0
 268        ;;
 269        rfi
 270        ;;
 2711:      // now we are in virtual mode
 272
 273        SET_AREA_FOR_BOOTING_CPU(r2, r16);
 274
 275        STORE_REGION_REGS(r16, r8,r9,r10,r11,r12,r13,r14,r15);
 276        SAL_TO_OS_BOOT_HANDOFF_STATE_SAVE(r16,r17,r25)
 277        ;;
 278
 279        // set IVT entry point---can't access I/O ports without it
 280        movl r3=ia64_ivt
 281        ;;
 282        mov cr.iva=r3
 283        movl r2=FPSR_DEFAULT
 284        ;;
 285        srlz.i
 286        movl gp=__gp
 287
 288        mov ar.fpsr=r2
 289        ;;
 290
 291#define isAP    p2      // are we an Application Processor?
 292#define isBP    p3      // are we the Bootstrap Processor?
 293
 294#ifdef CONFIG_SMP
 295        /*
 296         * Find the init_task for the currently booting CPU.  At poweron, and in
 297         * UP mode, task_for_booting_cpu is NULL.
 298         */
 299        movl r3=task_for_booting_cpu
 300        ;;
 301        ld8 r3=[r3]
 302        movl r2=init_task
 303        ;;
 304        cmp.eq isBP,isAP=r3,r0
 305        ;;
 306(isAP)  mov r2=r3
 307#else
 308        movl r2=init_task
 309        cmp.eq isBP,isAP=r0,r0
 310#endif
 311        ;;
 312        tpa r3=r2               // r3 == phys addr of task struct
 313        mov r16=-1
 314(isBP)  br.cond.dpnt .load_current // BP stack is on region 5 --- no need to map it
 315
 316        // load mapping for stack (virtaddr in r2, physaddr in r3)
 317        rsm psr.ic
 318        movl r17=PAGE_KERNEL
 319        ;;
 320        srlz.d
 321        dep r18=0,r3,0,12
 322        ;;
 323        or r18=r17,r18
 324        dep r2=-1,r3,61,3       // IMVA of task
 325        ;;
 326        mov r17=rr[r2]
 327        shr.u r16=r3,IA64_GRANULE_SHIFT
 328        ;;
 329        dep r17=0,r17,8,24
 330        ;;
 331        mov cr.itir=r17
 332        mov cr.ifa=r2
 333
 334        mov r19=IA64_TR_CURRENT_STACK
 335        ;;
 336        itr.d dtr[r19]=r18
 337        ;;
 338        ssm psr.ic
 339        srlz.d
 340        ;;
 341
 342.load_current:
 343        // load the "current" pointer (r13) and ar.k6 with the current task
 344        mov IA64_KR(CURRENT)=r2         // virtual address
 345        mov IA64_KR(CURRENT_STACK)=r16
 346        mov r13=r2
 347        /*
 348         * Reserve space at the top of the stack for "struct pt_regs".  Kernel
 349         * threads don't store interesting values in that structure, but the space
 350         * still needs to be there because time-critical stuff such as the context
 351         * switching can be implemented more efficiently (for example, __switch_to()
 352         * always sets the psr.dfh bit of the task it is switching to).
 353         */
 354
 355        addl r12=IA64_STK_OFFSET-IA64_PT_REGS_SIZE-16,r2
 356        addl r2=IA64_RBS_OFFSET,r2      // initialize the RSE
 357        mov ar.rsc=0            // place RSE in enforced lazy mode
 358        ;;
 359        loadrs                  // clear the dirty partition
 360        movl r19=__phys_per_cpu_start
 361        mov r18=PERCPU_PAGE_SIZE
 362        ;;
 363#ifndef CONFIG_SMP
 364        add r19=r19,r18
 365        ;;
 366#else
 367(isAP)  br.few 2f
 368        movl r20=__cpu0_per_cpu
 369        ;;
 370        shr.u r18=r18,3
 3711:
 372        ld8 r21=[r19],8;;
 373        st8[r20]=r21,8
 374        adds r18=-1,r18;;
 375        cmp4.lt p7,p6=0,r18
 376(p7)    br.cond.dptk.few 1b
 377        mov r19=r20
 378        ;;
 3792:
 380#endif
 381        tpa r19=r19
 382        ;;
 383        .pred.rel.mutex isBP,isAP
 384(isBP)  mov IA64_KR(PER_CPU_DATA)=r19   // per-CPU base for cpu0
 385(isAP)  mov IA64_KR(PER_CPU_DATA)=r0    // clear physical per-CPU base
 386        ;;
 387        mov ar.bspstore=r2      // establish the new RSE stack
 388        ;;
 389        mov ar.rsc=0x3          // place RSE in eager mode
 390
 391(isBP)  dep r28=-1,r28,61,3     // make address virtual
 392(isBP)  movl r2=ia64_boot_param
 393        ;;
 394(isBP)  st8 [r2]=r28            // save the address of the boot param area passed by the bootloader
 395
 396#ifdef CONFIG_SMP
 397(isAP)  br.call.sptk.many rp=start_secondary
 398.ret0:
 399(isAP)  br.cond.sptk self
 400#endif
 401
 402        // This is executed by the bootstrap processor (bsp) only:
 403
 404#ifdef CONFIG_IA64_FW_EMU
 405        // initialize PAL & SAL emulator:
 406        br.call.sptk.many rp=sys_fw_init
 407.ret1:
 408#endif
 409        br.call.sptk.many rp=start_kernel
 410.ret2:  addl r3=@ltoff(halt_msg),gp
 411        ;;
 412        alloc r2=ar.pfs,8,0,2,0
 413        ;;
 414        ld8 out0=[r3]
 415        br.call.sptk.many b0=console_print
 416
 417self:   hint @pause
 418        br.sptk.many self               // endless loop
 419END(_start)
 420
 421        .text
 422
 423GLOBAL_ENTRY(ia64_save_debug_regs)
 424        alloc r16=ar.pfs,1,0,0,0
 425        mov r20=ar.lc                   // preserve ar.lc
 426        mov ar.lc=IA64_NUM_DBG_REGS-1
 427        mov r18=0
 428        add r19=IA64_NUM_DBG_REGS*8,in0
 429        ;;
 4301:      mov r16=dbr[r18]
 431#ifdef CONFIG_ITANIUM
 432        ;;
 433        srlz.d
 434#endif
 435        mov r17=ibr[r18]
 436        add r18=1,r18
 437        ;;
 438        st8.nta [in0]=r16,8
 439        st8.nta [r19]=r17,8
 440        br.cloop.sptk.many 1b
 441        ;;
 442        mov ar.lc=r20                   // restore ar.lc
 443        br.ret.sptk.many rp
 444END(ia64_save_debug_regs)
 445
 446GLOBAL_ENTRY(ia64_load_debug_regs)
 447        alloc r16=ar.pfs,1,0,0,0
 448        lfetch.nta [in0]
 449        mov r20=ar.lc                   // preserve ar.lc
 450        add r19=IA64_NUM_DBG_REGS*8,in0
 451        mov ar.lc=IA64_NUM_DBG_REGS-1
 452        mov r18=-1
 453        ;;
 4541:      ld8.nta r16=[in0],8
 455        ld8.nta r17=[r19],8
 456        add r18=1,r18
 457        ;;
 458        mov dbr[r18]=r16
 459#ifdef CONFIG_ITANIUM
 460        ;;
 461        srlz.d                          // Errata 132 (NoFix status)
 462#endif
 463        mov ibr[r18]=r17
 464        br.cloop.sptk.many 1b
 465        ;;
 466        mov ar.lc=r20                   // restore ar.lc
 467        br.ret.sptk.many rp
 468END(ia64_load_debug_regs)
 469
 470GLOBAL_ENTRY(__ia64_save_fpu)
 471        alloc r2=ar.pfs,1,4,0,0
 472        adds loc0=96*16-16,in0
 473        adds loc1=96*16-16-128,in0
 474        ;;
 475        stf.spill.nta [loc0]=f127,-256
 476        stf.spill.nta [loc1]=f119,-256
 477        ;;
 478        stf.spill.nta [loc0]=f111,-256
 479        stf.spill.nta [loc1]=f103,-256
 480        ;;
 481        stf.spill.nta [loc0]=f95,-256
 482        stf.spill.nta [loc1]=f87,-256
 483        ;;
 484        stf.spill.nta [loc0]=f79,-256
 485        stf.spill.nta [loc1]=f71,-256
 486        ;;
 487        stf.spill.nta [loc0]=f63,-256
 488        stf.spill.nta [loc1]=f55,-256
 489        adds loc2=96*16-32,in0
 490        ;;
 491        stf.spill.nta [loc0]=f47,-256
 492        stf.spill.nta [loc1]=f39,-256
 493        adds loc3=96*16-32-128,in0
 494        ;;
 495        stf.spill.nta [loc2]=f126,-256
 496        stf.spill.nta [loc3]=f118,-256
 497        ;;
 498        stf.spill.nta [loc2]=f110,-256
 499        stf.spill.nta [loc3]=f102,-256
 500        ;;
 501        stf.spill.nta [loc2]=f94,-256
 502        stf.spill.nta [loc3]=f86,-256
 503        ;;
 504        stf.spill.nta [loc2]=f78,-256
 505        stf.spill.nta [loc3]=f70,-256
 506        ;;
 507        stf.spill.nta [loc2]=f62,-256
 508        stf.spill.nta [loc3]=f54,-256
 509        adds loc0=96*16-48,in0
 510        ;;
 511        stf.spill.nta [loc2]=f46,-256
 512        stf.spill.nta [loc3]=f38,-256
 513        adds loc1=96*16-48-128,in0
 514        ;;
 515        stf.spill.nta [loc0]=f125,-256
 516        stf.spill.nta [loc1]=f117,-256
 517        ;;
 518        stf.spill.nta [loc0]=f109,-256
 519        stf.spill.nta [loc1]=f101,-256
 520        ;;
 521        stf.spill.nta [loc0]=f93,-256
 522        stf.spill.nta [loc1]=f85,-256
 523        ;;
 524        stf.spill.nta [loc0]=f77,-256
 525        stf.spill.nta [loc1]=f69,-256
 526        ;;
 527        stf.spill.nta [loc0]=f61,-256
 528        stf.spill.nta [loc1]=f53,-256
 529        adds loc2=96*16-64,in0
 530        ;;
 531        stf.spill.nta [loc0]=f45,-256
 532        stf.spill.nta [loc1]=f37,-256
 533        adds loc3=96*16-64-128,in0
 534        ;;
 535        stf.spill.nta [loc2]=f124,-256
 536        stf.spill.nta [loc3]=f116,-256
 537        ;;
 538        stf.spill.nta [loc2]=f108,-256
 539        stf.spill.nta [loc3]=f100,-256
 540        ;;
 541        stf.spill.nta [loc2]=f92,-256
 542        stf.spill.nta [loc3]=f84,-256
 543        ;;
 544        stf.spill.nta [loc2]=f76,-256
 545        stf.spill.nta [loc3]=f68,-256
 546        ;;
 547        stf.spill.nta [loc2]=f60,-256
 548        stf.spill.nta [loc3]=f52,-256
 549        adds loc0=96*16-80,in0
 550        ;;
 551        stf.spill.nta [loc2]=f44,-256
 552        stf.spill.nta [loc3]=f36,-256
 553        adds loc1=96*16-80-128,in0
 554        ;;
 555        stf.spill.nta [loc0]=f123,-256
 556        stf.spill.nta [loc1]=f115,-256
 557        ;;
 558        stf.spill.nta [loc0]=f107,-256
 559        stf.spill.nta [loc1]=f99,-256
 560        ;;
 561        stf.spill.nta [loc0]=f91,-256
 562        stf.spill.nta [loc1]=f83,-256
 563        ;;
 564        stf.spill.nta [loc0]=f75,-256
 565        stf.spill.nta [loc1]=f67,-256
 566        ;;
 567        stf.spill.nta [loc0]=f59,-256
 568        stf.spill.nta [loc1]=f51,-256
 569        adds loc2=96*16-96,in0
 570        ;;
 571        stf.spill.nta [loc0]=f43,-256
 572        stf.spill.nta [loc1]=f35,-256
 573        adds loc3=96*16-96-128,in0
 574        ;;
 575        stf.spill.nta [loc2]=f122,-256
 576        stf.spill.nta [loc3]=f114,-256
 577        ;;
 578        stf.spill.nta [loc2]=f106,-256
 579        stf.spill.nta [loc3]=f98,-256
 580        ;;
 581        stf.spill.nta [loc2]=f90,-256
 582        stf.spill.nta [loc3]=f82,-256
 583        ;;
 584        stf.spill.nta [loc2]=f74,-256
 585        stf.spill.nta [loc3]=f66,-256
 586        ;;
 587        stf.spill.nta [loc2]=f58,-256
 588        stf.spill.nta [loc3]=f50,-256
 589        adds loc0=96*16-112,in0
 590        ;;
 591        stf.spill.nta [loc2]=f42,-256
 592        stf.spill.nta [loc3]=f34,-256
 593        adds loc1=96*16-112-128,in0
 594        ;;
 595        stf.spill.nta [loc0]=f121,-256
 596        stf.spill.nta [loc1]=f113,-256
 597        ;;
 598        stf.spill.nta [loc0]=f105,-256
 599        stf.spill.nta [loc1]=f97,-256
 600        ;;
 601        stf.spill.nta [loc0]=f89,-256
 602        stf.spill.nta [loc1]=f81,-256
 603        ;;
 604        stf.spill.nta [loc0]=f73,-256
 605        stf.spill.nta [loc1]=f65,-256
 606        ;;
 607        stf.spill.nta [loc0]=f57,-256
 608        stf.spill.nta [loc1]=f49,-256
 609        adds loc2=96*16-128,in0
 610        ;;
 611        stf.spill.nta [loc0]=f41,-256
 612        stf.spill.nta [loc1]=f33,-256
 613        adds loc3=96*16-128-128,in0
 614        ;;
 615        stf.spill.nta [loc2]=f120,-256
 616        stf.spill.nta [loc3]=f112,-256
 617        ;;
 618        stf.spill.nta [loc2]=f104,-256
 619        stf.spill.nta [loc3]=f96,-256
 620        ;;
 621        stf.spill.nta [loc2]=f88,-256
 622        stf.spill.nta [loc3]=f80,-256
 623        ;;
 624        stf.spill.nta [loc2]=f72,-256
 625        stf.spill.nta [loc3]=f64,-256
 626        ;;
 627        stf.spill.nta [loc2]=f56,-256
 628        stf.spill.nta [loc3]=f48,-256
 629        ;;
 630        stf.spill.nta [loc2]=f40
 631        stf.spill.nta [loc3]=f32
 632        br.ret.sptk.many rp
 633END(__ia64_save_fpu)
 634
 635GLOBAL_ENTRY(__ia64_load_fpu)
 636        alloc r2=ar.pfs,1,2,0,0
 637        adds r3=128,in0
 638        adds r14=256,in0
 639        adds r15=384,in0
 640        mov loc0=512
 641        mov loc1=-1024+16
 642        ;;
 643        ldf.fill.nta f32=[in0],loc0
 644        ldf.fill.nta f40=[ r3],loc0
 645        ldf.fill.nta f48=[r14],loc0
 646        ldf.fill.nta f56=[r15],loc0
 647        ;;
 648        ldf.fill.nta f64=[in0],loc0
 649        ldf.fill.nta f72=[ r3],loc0
 650        ldf.fill.nta f80=[r14],loc0
 651        ldf.fill.nta f88=[r15],loc0
 652        ;;
 653        ldf.fill.nta f96=[in0],loc1
 654        ldf.fill.nta f104=[ r3],loc1
 655        ldf.fill.nta f112=[r14],loc1
 656        ldf.fill.nta f120=[r15],loc1
 657        ;;
 658        ldf.fill.nta f33=[in0],loc0
 659        ldf.fill.nta f41=[ r3],loc0
 660        ldf.fill.nta f49=[r14],loc0
 661        ldf.fill.nta f57=[r15],loc0
 662        ;;
 663        ldf.fill.nta f65=[in0],loc0
 664        ldf.fill.nta f73=[ r3],loc0
 665        ldf.fill.nta f81=[r14],loc0
 666        ldf.fill.nta f89=[r15],loc0
 667        ;;
 668        ldf.fill.nta f97=[in0],loc1
 669        ldf.fill.nta f105=[ r3],loc1
 670        ldf.fill.nta f113=[r14],loc1
 671        ldf.fill.nta f121=[r15],loc1
 672        ;;
 673        ldf.fill.nta f34=[in0],loc0
 674        ldf.fill.nta f42=[ r3],loc0
 675        ldf.fill.nta f50=[r14],loc0
 676        ldf.fill.nta f58=[r15],loc0
 677        ;;
 678        ldf.fill.nta f66=[in0],loc0
 679        ldf.fill.nta f74=[ r3],loc0
 680        ldf.fill.nta f82=[r14],loc0
 681        ldf.fill.nta f90=[r15],loc0
 682        ;;
 683        ldf.fill.nta f98=[in0],loc1
 684        ldf.fill.nta f106=[ r3],loc1
 685        ldf.fill.nta f114=[r14],loc1
 686        ldf.fill.nta f122=[r15],loc1
 687        ;;
 688        ldf.fill.nta f35=[in0],loc0
 689        ldf.fill.nta f43=[ r3],loc0
 690        ldf.fill.nta f51=[r14],loc0
 691        ldf.fill.nta f59=[r15],loc0
 692        ;;
 693        ldf.fill.nta f67=[in0],loc0
 694        ldf.fill.nta f75=[ r3],loc0
 695        ldf.fill.nta f83=[r14],loc0
 696        ldf.fill.nta f91=[r15],loc0
 697        ;;
 698        ldf.fill.nta f99=[in0],loc1
 699        ldf.fill.nta f107=[ r3],loc1
 700        ldf.fill.nta f115=[r14],loc1
 701        ldf.fill.nta f123=[r15],loc1
 702        ;;
 703        ldf.fill.nta f36=[in0],loc0
 704        ldf.fill.nta f44=[ r3],loc0
 705        ldf.fill.nta f52=[r14],loc0
 706        ldf.fill.nta f60=[r15],loc0
 707        ;;
 708        ldf.fill.nta f68=[in0],loc0
 709        ldf.fill.nta f76=[ r3],loc0
 710        ldf.fill.nta f84=[r14],loc0
 711        ldf.fill.nta f92=[r15],loc0
 712        ;;
 713        ldf.fill.nta f100=[in0],loc1
 714        ldf.fill.nta f108=[ r3],loc1
 715        ldf.fill.nta f116=[r14],loc1
 716        ldf.fill.nta f124=[r15],loc1
 717        ;;
 718        ldf.fill.nta f37=[in0],loc0
 719        ldf.fill.nta f45=[ r3],loc0
 720        ldf.fill.nta f53=[r14],loc0
 721        ldf.fill.nta f61=[r15],loc0
 722        ;;
 723        ldf.fill.nta f69=[in0],loc0
 724        ldf.fill.nta f77=[ r3],loc0
 725        ldf.fill.nta f85=[r14],loc0
 726        ldf.fill.nta f93=[r15],loc0
 727        ;;
 728        ldf.fill.nta f101=[in0],loc1
 729        ldf.fill.nta f109=[ r3],loc1
 730        ldf.fill.nta f117=[r14],loc1
 731        ldf.fill.nta f125=[r15],loc1
 732        ;;
 733        ldf.fill.nta f38 =[in0],loc0
 734        ldf.fill.nta f46 =[ r3],loc0
 735        ldf.fill.nta f54 =[r14],loc0
 736        ldf.fill.nta f62 =[r15],loc0
 737        ;;
 738        ldf.fill.nta f70 =[in0],loc0
 739        ldf.fill.nta f78 =[ r3],loc0
 740        ldf.fill.nta f86 =[r14],loc0
 741        ldf.fill.nta f94 =[r15],loc0
 742        ;;
 743        ldf.fill.nta f102=[in0],loc1
 744        ldf.fill.nta f110=[ r3],loc1
 745        ldf.fill.nta f118=[r14],loc1
 746        ldf.fill.nta f126=[r15],loc1
 747        ;;
 748        ldf.fill.nta f39 =[in0],loc0
 749        ldf.fill.nta f47 =[ r3],loc0
 750        ldf.fill.nta f55 =[r14],loc0
 751        ldf.fill.nta f63 =[r15],loc0
 752        ;;
 753        ldf.fill.nta f71 =[in0],loc0
 754        ldf.fill.nta f79 =[ r3],loc0
 755        ldf.fill.nta f87 =[r14],loc0
 756        ldf.fill.nta f95 =[r15],loc0
 757        ;;
 758        ldf.fill.nta f103=[in0]
 759        ldf.fill.nta f111=[ r3]
 760        ldf.fill.nta f119=[r14]
 761        ldf.fill.nta f127=[r15]
 762        br.ret.sptk.many rp
 763END(__ia64_load_fpu)
 764
 765GLOBAL_ENTRY(__ia64_init_fpu)
 766        stf.spill [sp]=f0               // M3
 767        mov      f32=f0                 // F
 768        nop.b    0
 769
 770        ldfps    f33,f34=[sp]           // M0
 771        ldfps    f35,f36=[sp]           // M1
 772        mov      f37=f0                 // F
 773        ;;
 774
 775        setf.s   f38=r0                 // M2
 776        setf.s   f39=r0                 // M3
 777        mov      f40=f0                 // F
 778
 779        ldfps    f41,f42=[sp]           // M0
 780        ldfps    f43,f44=[sp]           // M1
 781        mov      f45=f0                 // F
 782
 783        setf.s   f46=r0                 // M2
 784        setf.s   f47=r0                 // M3
 785        mov      f48=f0                 // F
 786
 787        ldfps    f49,f50=[sp]           // M0
 788        ldfps    f51,f52=[sp]           // M1
 789        mov      f53=f0                 // F
 790
 791        setf.s   f54=r0                 // M2
 792        setf.s   f55=r0                 // M3
 793        mov      f56=f0                 // F
 794
 795        ldfps    f57,f58=[sp]           // M0
 796        ldfps    f59,f60=[sp]           // M1
 797        mov      f61=f0                 // F
 798
 799        setf.s   f62=r0                 // M2
 800        setf.s   f63=r0                 // M3
 801        mov      f64=f0                 // F
 802
 803        ldfps    f65,f66=[sp]           // M0
 804        ldfps    f67,f68=[sp]           // M1
 805        mov      f69=f0                 // F
 806
 807        setf.s   f70=r0                 // M2
 808        setf.s   f71=r0                 // M3
 809        mov      f72=f0                 // F
 810
 811        ldfps    f73,f74=[sp]           // M0
 812        ldfps    f75,f76=[sp]           // M1
 813        mov      f77=f0                 // F
 814
 815        setf.s   f78=r0                 // M2
 816        setf.s   f79=r0                 // M3
 817        mov      f80=f0                 // F
 818
 819        ldfps    f81,f82=[sp]           // M0
 820        ldfps    f83,f84=[sp]           // M1
 821        mov      f85=f0                 // F
 822
 823        setf.s   f86=r0                 // M2
 824        setf.s   f87=r0                 // M3
 825        mov      f88=f0                 // F
 826
 827        /*
 828         * When the instructions are cached, it would be faster to initialize
 829         * the remaining registers with simply mov instructions (F-unit).
 830         * This gets the time down to ~29 cycles.  However, this would use up
 831         * 33 bundles, whereas continuing with the above pattern yields
 832         * 10 bundles and ~30 cycles.
 833         */
 834
 835        ldfps    f89,f90=[sp]           // M0
 836        ldfps    f91,f92=[sp]           // M1
 837        mov      f93=f0                 // F
 838
 839        setf.s   f94=r0                 // M2
 840        setf.s   f95=r0                 // M3
 841        mov      f96=f0                 // F
 842
 843        ldfps    f97,f98=[sp]           // M0
 844        ldfps    f99,f100=[sp]          // M1
 845        mov      f101=f0                // F
 846
 847        setf.s   f102=r0                // M2
 848        setf.s   f103=r0                // M3
 849        mov      f104=f0                // F
 850
 851        ldfps    f105,f106=[sp]         // M0
 852        ldfps    f107,f108=[sp]         // M1
 853        mov      f109=f0                // F
 854
 855        setf.s   f110=r0                // M2
 856        setf.s   f111=r0                // M3
 857        mov      f112=f0                // F
 858
 859        ldfps    f113,f114=[sp]         // M0
 860        ldfps    f115,f116=[sp]         // M1
 861        mov      f117=f0                // F
 862
 863        setf.s   f118=r0                // M2
 864        setf.s   f119=r0                // M3
 865        mov      f120=f0                // F
 866
 867        ldfps    f121,f122=[sp]         // M0
 868        ldfps    f123,f124=[sp]         // M1
 869        mov      f125=f0                // F
 870
 871        setf.s   f126=r0                // M2
 872        setf.s   f127=r0                // M3
 873        br.ret.sptk.many rp             // F
 874END(__ia64_init_fpu)
 875
 876/*
 877 * Switch execution mode from virtual to physical
 878 *
 879 * Inputs:
 880 *      r16 = new psr to establish
 881 * Output:
 882 *      r19 = old virtual address of ar.bsp
 883 *      r20 = old virtual address of sp
 884 *
 885 * Note: RSE must already be in enforced lazy mode
 886 */
 887GLOBAL_ENTRY(ia64_switch_mode_phys)
 888 {
 889        rsm psr.i | psr.ic              // disable interrupts and interrupt collection
 890        mov r15=ip
 891 }
 892        ;;
 893 {
 894        flushrs                         // must be first insn in group
 895        srlz.i
 896 }
 897        ;;
 898        mov cr.ipsr=r16                 // set new PSR
 899        add r3=1f-ia64_switch_mode_phys,r15
 900
 901        mov r19=ar.bsp
 902        mov r20=sp
 903        mov r14=rp                      // get return address into a general register
 904        ;;
 905
 906        // going to physical mode, use tpa to translate virt->phys
 907        tpa r17=r19
 908        tpa r3=r3
 909        tpa sp=sp
 910        tpa r14=r14
 911        ;;
 912
 913        mov r18=ar.rnat                 // save ar.rnat
 914        mov ar.bspstore=r17             // this steps on ar.rnat
 915        mov cr.iip=r3
 916        mov cr.ifs=r0
 917        ;;
 918        mov ar.rnat=r18                 // restore ar.rnat
 919        rfi                             // must be last insn in group
 920        ;;
 9211:      mov rp=r14
 922        br.ret.sptk.many rp
 923END(ia64_switch_mode_phys)
 924
 925/*
 926 * Switch execution mode from physical to virtual
 927 *
 928 * Inputs:
 929 *      r16 = new psr to establish
 930 *      r19 = new bspstore to establish
 931 *      r20 = new sp to establish
 932 *
 933 * Note: RSE must already be in enforced lazy mode
 934 */
 935GLOBAL_ENTRY(ia64_switch_mode_virt)
 936 {
 937        rsm psr.i | psr.ic              // disable interrupts and interrupt collection
 938        mov r15=ip
 939 }
 940        ;;
 941 {
 942        flushrs                         // must be first insn in group
 943        srlz.i
 944 }
 945        ;;
 946        mov cr.ipsr=r16                 // set new PSR
 947        add r3=1f-ia64_switch_mode_virt,r15
 948
 949        mov r14=rp                      // get return address into a general register
 950        ;;
 951
 952        // going to virtual
 953        //   - for code addresses, set upper bits of addr to KERNEL_START
 954        //   - for stack addresses, copy from input argument
 955        movl r18=KERNEL_START
 956        dep r3=0,r3,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
 957        dep r14=0,r14,KERNEL_TR_PAGE_SHIFT,64-KERNEL_TR_PAGE_SHIFT
 958        mov sp=r20
 959        ;;
 960        or r3=r3,r18
 961        or r14=r14,r18
 962        ;;
 963
 964        mov r18=ar.rnat                 // save ar.rnat
 965        mov ar.bspstore=r19             // this steps on ar.rnat
 966        mov cr.iip=r3
 967        mov cr.ifs=r0
 968        ;;
 969        mov ar.rnat=r18                 // restore ar.rnat
 970        rfi                             // must be last insn in group
 971        ;;
 9721:      mov rp=r14
 973        br.ret.sptk.many rp
 974END(ia64_switch_mode_virt)
 975
 976GLOBAL_ENTRY(ia64_delay_loop)
 977        .prologue
 978{       nop 0                   // work around GAS unwind info generation bug...
 979        .save ar.lc,r2
 980        mov r2=ar.lc
 981        .body
 982        ;;
 983        mov ar.lc=r32
 984}
 985        ;;
 986        // force loop to be 32-byte aligned (GAS bug means we cannot use .align
 987        // inside function body without corrupting unwind info).
 988{       nop 0 }
 9891:      br.cloop.sptk.few 1b
 990        ;;
 991        mov ar.lc=r2
 992        br.ret.sptk.many rp
 993END(ia64_delay_loop)
 994
 995/*
 996 * Return a CPU-local timestamp in nano-seconds.  This timestamp is
 997 * NOT synchronized across CPUs its return value must never be
 998 * compared against the values returned on another CPU.  The usage in
 999 * kernel/sched/core.c ensures that.
1000 *

1001 * The return-value of sched_clock() is NOT supposed to wrap-around.
1002 * If it did, it would cause some scheduling hiccups (at the worst).
1003 * Fortunately, with a 64-bit cycle-counter ticking at 100GHz, even
1004 * that would happen only once every 5+ years.
1005 *
1006 * The code below basically calculates:
1007 *
1008 *   (ia64_get_itc() * local_cpu_data->nsec_per_cyc) >> IA64_NSEC_PER_CYC_SHIFT
1009 *
1010 * except that the multiplication and the shift are done with 128-bit
1011 * intermediate precision so that we can produce a full 64-bit result.
1012 */
1013GLOBAL_ENTRY(ia64_native_sched_clock)
1014        addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
1015        mov.m r9=ar.itc         // fetch cycle-counter                          (35 cyc)
1016        ;;
1017        ldf8 f8=[r8]
1018        ;;
1019        setf.sig f9=r9          // certain to stall, so issue it _after_ ldf8...
1020        ;;
1021        xmpy.lu f10=f9,f8       // calculate low 64 bits of 128-bit product     (4 cyc)
1022        xmpy.hu f11=f9,f8       // calculate high 64 bits of 128-bit product
1023        ;;
1024        getf.sig r8=f10         //                                              (5 cyc)
1025        getf.sig r9=f11
1026        ;;
1027        shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
1028        br.ret.sptk.many rp
1029END(ia64_native_sched_clock)
1030
1031#ifdef CONFIG_VIRT_CPU_ACCOUNTING_NATIVE
1032GLOBAL_ENTRY(cycle_to_cputime)
1033        alloc r16=ar.pfs,1,0,0,0
1034        addl r8=THIS_CPU(ia64_cpu_info) + IA64_CPUINFO_NSEC_PER_CYC_OFFSET,r0
1035        ;;
1036        ldf8 f8=[r8]
1037        ;;
1038        setf.sig f9=r32
1039        ;;
1040        xmpy.lu f10=f9,f8       // calculate low 64 bits of 128-bit product     (4 cyc)
1041        xmpy.hu f11=f9,f8       // calculate high 64 bits of 128-bit product
1042        ;;
1043        getf.sig r8=f10         //                                              (5 cyc)
1044        getf.sig r9=f11
1045        ;;
1046        shrp r8=r9,r8,IA64_NSEC_PER_CYC_SHIFT
1047        br.ret.sptk.many rp
1048END(cycle_to_cputime)
1049#endif /* CONFIG_VIRT_CPU_ACCOUNTING_NATIVE */
1050
1051#ifdef CONFIG_IA64_BRL_EMU
1052
1053/*
1054 *  Assembly routines used by brl_emu.c to set preserved register state.
1055 */
1056
1057#define SET_REG(reg)                            \
1058 GLOBAL_ENTRY(ia64_set_##reg);                  \
1059        alloc r16=ar.pfs,1,0,0,0;               \
1060        mov reg=r32;                            \
1061        ;;                                      \
1062        br.ret.sptk.many rp;                    \
1063 END(ia64_set_##reg)
1064
1065SET_REG(b1);
1066SET_REG(b2);
1067SET_REG(b3);
1068SET_REG(b4);
1069SET_REG(b5);
1070
1071#endif /* CONFIG_IA64_BRL_EMU */
1072
1073#ifdef CONFIG_SMP
1074
1075#ifdef CONFIG_HOTPLUG_CPU
1076GLOBAL_ENTRY(ia64_jump_to_sal)
1077        alloc r16=ar.pfs,1,0,0,0;;
1078        rsm psr.i  | psr.ic
1079{
1080        flushrs
1081        srlz.i
1082}
1083        tpa r25=in0
1084        movl r18=tlb_purge_done;;
1085        DATA_VA_TO_PA(r18);;
1086        mov b1=r18      // Return location
1087        movl r18=ia64_do_tlb_purge;;
1088        DATA_VA_TO_PA(r18);;
1089        mov b2=r18      // doing tlb_flush work
1090        mov ar.rsc=0  // Put RSE  in enforced lazy, LE mode
1091        movl r17=1f;;
1092        DATA_VA_TO_PA(r17);;
1093        mov cr.iip=r17
1094        movl r16=SAL_PSR_BITS_TO_SET;;
1095        mov cr.ipsr=r16
1096        mov cr.ifs=r0;;
1097        rfi;;                   // note: this unmask MCA/INIT (psr.mc)
10981:
1099        /*
1100         * Invalidate all TLB data/inst
1101         */
1102        br.sptk.many b2;; // jump to tlb purge code
1103
1104tlb_purge_done:
1105        RESTORE_REGION_REGS(r25, r17,r18,r19);;
1106        RESTORE_REG(b0, r25, r17);;
1107        RESTORE_REG(b1, r25, r17);;
1108        RESTORE_REG(b2, r25, r17);;
1109        RESTORE_REG(b3, r25, r17);;
1110        RESTORE_REG(b4, r25, r17);;
1111        RESTORE_REG(b5, r25, r17);;
1112        ld8 r1=[r25],0x08;;
1113        ld8 r12=[r25],0x08;;
1114        ld8 r13=[r25],0x08;;
1115        RESTORE_REG(ar.fpsr, r25, r17);;
1116        RESTORE_REG(ar.pfs, r25, r17);;
1117        RESTORE_REG(ar.rnat, r25, r17);;
1118        RESTORE_REG(ar.unat, r25, r17);;
1119        RESTORE_REG(ar.bspstore, r25, r17);;
1120        RESTORE_REG(cr.dcr, r25, r17);;
1121        RESTORE_REG(cr.iva, r25, r17);;
1122        RESTORE_REG(cr.pta, r25, r17);;
1123        srlz.d;;        // required not to violate RAW dependency
1124        RESTORE_REG(cr.itv, r25, r17);;
1125        RESTORE_REG(cr.pmv, r25, r17);;
1126        RESTORE_REG(cr.cmcv, r25, r17);;
1127        RESTORE_REG(cr.lrr0, r25, r17);;
1128        RESTORE_REG(cr.lrr1, r25, r17);;
1129        ld8 r4=[r25],0x08;;
1130        ld8 r5=[r25],0x08;;
1131        ld8 r6=[r25],0x08;;
1132        ld8 r7=[r25],0x08;;
1133        ld8 r17=[r25],0x08;;
1134        mov pr=r17,-1;;
1135        RESTORE_REG(ar.lc, r25, r17);;
1136        /*
1137         * Now Restore floating point regs
1138         */
1139        ldf.fill.nta f2=[r25],16;;
1140        ldf.fill.nta f3=[r25],16;;
1141        ldf.fill.nta f4=[r25],16;;
1142        ldf.fill.nta f5=[r25],16;;
1143        ldf.fill.nta f16=[r25],16;;
1144        ldf.fill.nta f17=[r25],16;;
1145        ldf.fill.nta f18=[r25],16;;
1146        ldf.fill.nta f19=[r25],16;;
1147        ldf.fill.nta f20=[r25],16;;
1148        ldf.fill.nta f21=[r25],16;;
1149        ldf.fill.nta f22=[r25],16;;
1150        ldf.fill.nta f23=[r25],16;;
1151        ldf.fill.nta f24=[r25],16;;
1152        ldf.fill.nta f25=[r25],16;;
1153        ldf.fill.nta f26=[r25],16;;
1154        ldf.fill.nta f27=[r25],16;;
1155        ldf.fill.nta f28=[r25],16;;
1156        ldf.fill.nta f29=[r25],16;;
1157        ldf.fill.nta f30=[r25],16;;
1158        ldf.fill.nta f31=[r25],16;;
1159
1160        /*
1161         * Now that we have done all the register restores
1162         * we are now ready for the big DIVE to SAL Land
1163         */
1164        ssm psr.ic;;
1165        srlz.d;;
1166        br.ret.sptk.many b0;;
1167END(ia64_jump_to_sal)
1168#endif /* CONFIG_HOTPLUG_CPU */
1169
1170#endif /* CONFIG_SMP */
1171