1/* 2** linux/atarihw.h -- This header defines some macros and pointers for 3** the various Atari custom hardware registers. 4** 5** Copyright 1994 by Björn Brauel 6** 7** 5/1/94 Roman Hodek: 8** Added definitions for TT specific chips. 9** 10** 1996-09-13 lars brinkhoff <f93labr@dd.chalmers.se>: 11** Finally added definitions for the matrix/codec and the DSP56001 host 12** interface. 13** 14** This file is subject to the terms and conditions of the GNU General Public 15** License. See the file COPYING in the main directory of this archive 16** for more details. 17** 18*/ 19 20#ifndef _LINUX_ATARIHW_H_ 21#define _LINUX_ATARIHW_H_ 22 23#include <linux/types.h> 24#include <asm/bootinfo-atari.h> 25#include <asm/raw_io.h> 26 27extern u_long atari_mch_cookie; 28extern u_long atari_mch_type; 29extern u_long atari_switches; 30extern int atari_rtc_year_offset; 31extern int atari_dont_touch_floppy_select; 32 33extern int atari_SCC_reset_done; 34 35/* convenience macros for testing machine type */ 36#define MACH_IS_ST ((atari_mch_cookie >> 16) == ATARI_MCH_ST) 37#define MACH_IS_STE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ 38 (atari_mch_cookie & 0xffff) == 0) 39#define MACH_IS_MSTE ((atari_mch_cookie >> 16) == ATARI_MCH_STE && \ 40 (atari_mch_cookie & 0xffff) == 0x10) 41#define MACH_IS_TT ((atari_mch_cookie >> 16) == ATARI_MCH_TT) 42#define MACH_IS_FALCON ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON) 43#define MACH_IS_MEDUSA (atari_mch_type == ATARI_MACH_MEDUSA) 44#define MACH_IS_AB40 (atari_mch_type == ATARI_MACH_AB40) 45 46/* values for atari_switches */ 47#define ATARI_SWITCH_IKBD 0x01 48#define ATARI_SWITCH_MIDI 0x02 49#define ATARI_SWITCH_SND6 0x04 50#define ATARI_SWITCH_SND7 0x08 51#define ATARI_SWITCH_OVSC_SHIFT 16 52#define ATARI_SWITCH_OVSC_IKBD (ATARI_SWITCH_IKBD << ATARI_SWITCH_OVSC_SHIFT) 53#define ATARI_SWITCH_OVSC_MIDI (ATARI_SWITCH_MIDI << ATARI_SWITCH_OVSC_SHIFT) 54#define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT) 55#define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT) 56#define ATARI_SWITCH_OVSC_MASK 0xffff0000 57 58/* 59 * Define several Hardware-Chips for indication so that for the ATARI we do 60 * no longer decide whether it is a Falcon or other machine . It's just 61 * important what hardware the machine uses 62 */ 63 64/* ++roman 08/08/95: rewritten from ORing constants to a C bitfield */ 65 66#define ATARIHW_DECLARE(name) unsigned name : 1 67#define ATARIHW_SET(name) (atari_hw_present.name = 1) 68#define ATARIHW_PRESENT(name) (atari_hw_present.name) 69 70struct atari_hw_present { 71 /* video hardware */ 72 ATARIHW_DECLARE(STND_SHIFTER); /* ST-Shifter - no base low ! */ 73 ATARIHW_DECLARE(EXTD_SHIFTER); /* STe-Shifter - 24 bit address */ 74 ATARIHW_DECLARE(TT_SHIFTER); /* TT-Shifter */ 75 ATARIHW_DECLARE(VIDEL_SHIFTER); /* Falcon-Shifter */ 76 /* sound hardware */ 77 ATARIHW_DECLARE(YM_2149); /* Yamaha YM 2149 */ 78 ATARIHW_DECLARE(PCM_8BIT); /* PCM-Sound in STe-ATARI */ 79 ATARIHW_DECLARE(CODEC); /* CODEC Sound (Falcon) */ 80 /* disk storage interfaces */ 81 ATARIHW_DECLARE(TT_SCSI); /* Directly mapped NCR5380 */ 82 ATARIHW_DECLARE(ST_SCSI); /* NCR5380 via ST-DMA (Falcon) */ 83 ATARIHW_DECLARE(ACSI); /* Standard ACSI like in STs */ 84 ATARIHW_DECLARE(IDE); /* IDE Interface */ 85 ATARIHW_DECLARE(FDCSPEED); /* 8/16 MHz switch for FDC */ 86 /* other I/O hardware */ 87 ATARIHW_DECLARE(ST_MFP); /* The ST-MFP (there should be no Atari 88 without it... but who knows?) */ 89 ATARIHW_DECLARE(TT_MFP); /* 2nd MFP */ 90 ATARIHW_DECLARE(SCC); /* Serial Communications Contr. */ 91 ATARIHW_DECLARE(ST_ESCC); /* SCC Z83230 in an ST */ 92 ATARIHW_DECLARE(ANALOG_JOY); /* Paddle Interface for STe 93 and Falcon */ 94 ATARIHW_DECLARE(MICROWIRE); /* Microwire Interface */ 95 /* DMA */ 96 ATARIHW_DECLARE(STND_DMA); /* 24 Bit limited ST-DMA */ 97 ATARIHW_DECLARE(EXTD_DMA); /* 32 Bit ST-DMA */ 98 ATARIHW_DECLARE(SCSI_DMA); /* DMA for the NCR5380 */ 99 ATARIHW_DECLARE(SCC_DMA); /* DMA for the SCC */ 100 /* real time clocks */ 101 ATARIHW_DECLARE(TT_CLK); /* TT compatible clock chip */ 102 ATARIHW_DECLARE(MSTE_CLK); /* Mega ST(E) clock chip */ 103 /* supporting hardware */ 104 ATARIHW_DECLARE(SCU); /* System Control Unit */ 105 ATARIHW_DECLARE(BLITTER); /* Blitter */ 106 ATARIHW_DECLARE(VME); /* VME Bus */ 107 ATARIHW_DECLARE(DSP56K); /* DSP56k processor in Falcon */ 108}; 109 110extern struct atari_hw_present atari_hw_present; 111 112 113/* Reading the MFP port register gives a machine independent delay, since the 114 * MFP always has a 8 MHz clock. This avoids problems with the varying length 115 * of nops on various machines. Somebody claimed that the tstb takes 600 ns. 116 */ 117#define MFPDELAY() \ 118 __asm__ __volatile__ ( "tstb %0" : : "m" (st_mfp.par_dt_reg) : "cc" ); 119 120/* Do cache push/invalidate for DMA read/write. This function obeys the 121 * snooping on some machines (Medusa) and processors: The Medusa itself can 122 * snoop, but only the '040 can source data from its cache to DMA writes i.e., 123 * reads from memory). Both '040 and '060 invalidate cache entries on snooped 124 * DMA reads (i.e., writes to memory). 125 */ 126 127 128#define atari_readb raw_inb 129#define atari_writeb raw_outb 130 131#define atari_inb_p raw_inb 132#define atari_outb_p raw_outb 133 134 135 136#include <linux/mm.h> 137#include <asm/cacheflush.h> 138 139static inline void dma_cache_maintenance( unsigned long paddr, 140 unsigned long len, 141 int writeflag ) 142 143{ 144 if (writeflag) { 145 if (!MACH_IS_MEDUSA || CPU_IS_060) 146 cache_push( paddr, len ); 147 } 148 else { 149 if (!MACH_IS_MEDUSA) 150 cache_clear( paddr, len ); 151 } 152} 153 154 155/* 156** Shifter 157 */ 158#define ST_LOW 0 159#define ST_MID 1 160#define ST_HIGH 2 161#define TT_LOW 7 162#define TT_MID 4 163#define TT_HIGH 6 164 165#define SHF_BAS (0xffff8200) 166struct SHIFTER 167 { 168 u_char pad1; 169 u_char bas_hi; 170 u_char pad2; 171 u_char bas_md; 172 u_char pad3; 173 u_char volatile vcounthi; 174 u_char pad4; 175 u_char volatile vcountmid; 176 u_char pad5; 177 u_char volatile vcountlow; 178 u_char volatile syncmode; 179 u_char pad6; 180 u_char pad7; 181 u_char bas_lo; 182 }; 183# define shifter ((*(volatile struct SHIFTER *)SHF_BAS)) 184 185#define SHF_FBAS (0xffff820e) 186struct SHIFTER_F030 187 { 188 u_short off_next; 189 u_short scn_width; 190 }; 191# define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS)) 192 193 194#define SHF_TBAS (0xffff8200) 195struct SHIFTER_TT { 196 u_char char_dummy0; 197 u_char bas_hi; /* video mem base addr, high and mid byte */ 198 u_char char_dummy1; 199 u_char bas_md; 200 u_char char_dummy2; 201 u_char vcount_hi; /* pointer to currently displayed byte */ 202 u_char char_dummy3; 203 u_char vcount_md; 204 u_char char_dummy4; 205 u_char vcount_lo; 206 u_short st_sync; /* ST compatible sync mode register, unused */ 207 u_char char_dummy5; 208 u_char bas_lo; /* video mem addr, low byte */ 209 u_char char_dummy6[2+3*16]; 210 /* $ffff8240: */ 211 u_short color_reg[16]; /* 16 color registers */ 212 u_char st_shiftmode; /* ST compatible shift mode register, unused */ 213 u_char char_dummy7; 214 u_short tt_shiftmode; /* TT shift mode register */ 215 216 217}; 218#define shifter_tt ((*(volatile struct SHIFTER_TT *)SHF_TBAS)) 219 220/* values for shifter_tt->tt_shiftmode */ 221#define TT_SHIFTER_STLOW 0x0000 222#define TT_SHIFTER_STMID 0x0100 223#define TT_SHIFTER_STHIGH 0x0200 224#define TT_SHIFTER_TTLOW 0x0700 225#define TT_SHIFTER_TTMID 0x0400 226#define TT_SHIFTER_TTHIGH 0x0600 227#define TT_SHIFTER_MODEMASK 0x0700 228#define TT_SHIFTER_NUMMODE 0x0008 229#define TT_SHIFTER_PALETTE_MASK 0x000f 230#define TT_SHIFTER_GRAYMODE 0x1000 231 232/* 256 TT palette registers */ 233#define TT_PALETTE_BASE (0xffff8400) 234#define tt_palette ((volatile u_short *)TT_PALETTE_BASE) 235 236#define TT_PALETTE_RED_MASK 0x0f00 237#define TT_PALETTE_GREEN_MASK 0x00f0 238#define TT_PALETTE_BLUE_MASK 0x000f 239 240/* 241** Falcon030 VIDEL Video Controller 242** for description see File 'linux\tools\atari\hardware.txt 243 */ 244#define f030_col ((u_long *) 0xffff9800) 245#define f030_xreg ((u_short*) 0xffff8282) 246#define f030_yreg ((u_short*) 0xffff82a2) 247#define f030_creg ((u_short*) 0xffff82c0) 248#define f030_sreg ((u_short*) 0xffff8260) 249#define f030_mreg ((u_short*) 0xffff820a) 250#define f030_linewidth ((u_short*) 0xffff820e) 251#define f030_hscroll ((u_char*) 0xffff8265) 252 253#define VIDEL_BAS (0xffff8260) 254struct VIDEL { 255 u_short st_shift; 256 u_short pad1; 257 u_char xoffset_s; 258 u_char xoffset; 259 u_short f_shift; 260 u_char pad2[0x1a]; 261 u_short hht; 262 u_short hbb; 263 u_short hbe; 264 u_short hdb; 265 u_short hde; 266 u_short hss; 267 u_char pad3[0x14]; 268 u_short vft; 269 u_short vbb; 270 u_short vbe; 271 u_short vdb; 272 u_short vde; 273 u_short vss; 274 u_char pad4[0x12]; 275 u_short control; 276 u_short mode; 277}; 278#define videl ((*(volatile struct VIDEL *)VIDEL_BAS)) 279 280/* 281** DMA/WD1772 Disk Controller 282 */ 283 284#define FWD_BAS (0xffff8604) 285struct DMA_WD 286 { 287 u_short fdc_acces_seccount; 288 u_short dma_mode_status; 289 u_char dma_vhi; /* Some extended ST-DMAs can handle 32 bit addresses */ 290 u_char dma_hi; 291 u_char char_dummy2; 292 u_char dma_md; 293 u_char char_dummy3; 294 u_char dma_lo; 295 u_short fdc_speed; 296 }; 297# define dma_wd ((*(volatile struct DMA_WD *)FWD_BAS)) 298/* alias */ 299#define st_dma dma_wd 300/* The two highest bytes of an extended DMA as a short; this is a must 301 * for the Medusa. 302 */ 303#define st_dma_ext_dmahi (*((volatile unsigned short *)0xffff8608)) 304 305/* 306** YM2149 Sound Chip 307** access in bytes 308 */ 309 310#define YM_BAS (0xffff8800) 311struct SOUND_YM 312 { 313 u_char rd_data_reg_sel; 314 u_char char_dummy1; 315 u_char wd_data; 316 }; 317#define sound_ym ((*(volatile struct SOUND_YM *)YM_BAS)) 318 319/* TT SCSI DMA */ 320 321#define TT_SCSI_DMA_BAS (0xffff8700) 322struct TT_DMA { 323 u_char char_dummy0; 324 u_char dma_addr_hi; 325 u_char char_dummy1; 326 u_char dma_addr_hmd; 327 u_char char_dummy2; 328 u_char dma_addr_lmd; 329 u_char char_dummy3; 330 u_char dma_addr_lo; 331 u_char char_dummy4; 332 u_char dma_cnt_hi; 333 u_char char_dummy5; 334 u_char dma_cnt_hmd; 335 u_char char_dummy6; 336 u_char dma_cnt_lmd; 337 u_char char_dummy7; 338 u_char dma_cnt_lo; 339 u_long dma_restdata; 340 u_short dma_ctrl; 341}; 342#define tt_scsi_dma ((*(volatile struct TT_DMA *)TT_SCSI_DMA_BAS)) 343 344/* TT SCSI Controller 5380 */ 345 346#define TT_5380_BAS (0xffff8781) 347struct TT_5380 { 348 u_char scsi_data; 349 u_char char_dummy1; 350 u_char scsi_icr; 351 u_char char_dummy2; 352 u_char scsi_mode; 353 u_char char_dummy3; 354 u_char scsi_tcr; 355 u_char char_dummy4; 356 u_char scsi_idstat; 357 u_char char_dummy5; 358 u_char scsi_dmastat; 359 u_char char_dummy6; 360 u_char scsi_targrcv; 361 u_char char_dummy7; 362 u_char scsi_inircv; 363}; 364#define tt_scsi ((*(volatile struct TT_5380 *)TT_5380_BAS)) 365#define tt_scsi_regp ((volatile char *)TT_5380_BAS) 366 367 368/* 369** Falcon DMA Sound Subsystem 370 */ 371 372#define MATRIX_BASE (0xffff8930) 373struct MATRIX 374{ 375 u_short source; 376 u_short destination; 377 u_char external_frequency_divider; 378 u_char internal_frequency_divider; 379}; 380#define falcon_matrix (*(volatile struct MATRIX *)MATRIX_BASE) 381 382#define CODEC_BASE (0xffff8936) 383struct CODEC 384{ 385 u_char tracks; 386 u_char input_source; 387#define CODEC_SOURCE_ADC 1 388#define CODEC_SOURCE_MATRIX 2 389 u_char adc_source; 390#define ADC_SOURCE_RIGHT_PSG 1 391#define ADC_SOURCE_LEFT_PSG 2 392 u_char gain; 393#define CODEC_GAIN_RIGHT 0x0f 394#define CODEC_GAIN_LEFT 0xf0 395 u_char attenuation; 396#define CODEC_ATTENUATION_RIGHT 0x0f 397#define CODEC_ATTENUATION_LEFT 0xf0 398 u_char unused1; 399 u_char status; 400#define CODEC_OVERFLOW_RIGHT 1 401#define CODEC_OVERFLOW_LEFT 2 402 u_char unused2, unused3, unused4, unused5; 403 u_char gpio_directions; 404#define CODEC_GPIO_IN 0 405#define CODEC_GPIO_OUT 1 406 u_char unused6; 407 u_char gpio_data; 408}; 409#define falcon_codec (*(volatile struct CODEC *)CODEC_BASE) 410 411/* 412** Falcon Blitter 413*/ 414 415#define BLT_BAS (0xffff8a00) 416 417struct BLITTER 418 { 419 u_short halftone[16]; 420 u_short src_x_inc; 421 u_short src_y_inc; 422 u_long src_address; 423 u_short endmask1; 424 u_short endmask2; 425 u_short endmask3; 426 u_short dst_x_inc; 427 u_short dst_y_inc; 428 u_long dst_address; 429 u_short wd_per_line; 430 u_short ln_per_bb; 431 u_short hlf_op_reg; 432 u_short log_op_reg; 433 u_short lin_nm_reg; 434 u_short skew_reg; 435 }; 436# define blitter ((*(volatile struct BLITTER *)BLT_BAS)) 437 438 439/* 440** SCC Z8530 441 */ 442 443#define SCC_BAS (0xffff8c81) 444struct SCC 445 { 446 u_char cha_a_ctrl; 447 u_char char_dummy1; 448 u_char cha_a_data; 449 u_char char_dummy2; 450 u_char cha_b_ctrl; 451 u_char char_dummy3; 452 u_char cha_b_data; 453 }; 454# define atari_scc ((*(volatile struct SCC*)SCC_BAS)) 455 456/* The ESCC (Z85230) in an Atari ST. The channels are reversed! */ 457# define st_escc ((*(volatile struct SCC*)0xfffffa31)) 458# define st_escc_dsr ((*(volatile char *)0xfffffa39)) 459 460/* TT SCC DMA Controller (same chip as SCSI DMA) */ 461 462#define TT_SCC_DMA_BAS (0xffff8c00) 463#define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS)) 464 465/* 466** VIDEL Palette Register 467 */ 468 469#define FPL_BAS (0xffff9800) 470struct VIDEL_PALETTE 471 { 472 u_long reg[256]; 473 }; 474# define videl_palette ((*(volatile struct VIDEL_PALETTE*)FPL_BAS)) 475 476 477/* 478** Falcon DSP Host Interface 479 */ 480 481#define DSP56K_HOST_INTERFACE_BASE (0xffffa200) 482struct DSP56K_HOST_INTERFACE { 483 u_char icr; 484#define DSP56K_ICR_RREQ 0x01 485#define DSP56K_ICR_TREQ 0x02 486#define DSP56K_ICR_HF0 0x08 487#define DSP56K_ICR_HF1 0x10 488#define DSP56K_ICR_HM0 0x20 489#define DSP56K_ICR_HM1 0x40 490#define DSP56K_ICR_INIT 0x80 491 492 u_char cvr; 493#define DSP56K_CVR_HV_MASK 0x1f 494#define DSP56K_CVR_HC 0x80 495 496 u_char isr; 497#define DSP56K_ISR_RXDF 0x01 498#define DSP56K_ISR_TXDE 0x02 499#define DSP56K_ISR_TRDY 0x04 500#define DSP56K_ISR_HF2 0x08 501#define DSP56K_ISR_HF3 0x10 502#define DSP56K_ISR_DMA 0x40 503#define DSP56K_ISR_HREQ 0x80 504 505 u_char ivr; 506 507 union { 508 u_char b[4]; 509 u_short w[2]; 510 u_long l; 511 } data; 512}; 513#define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE)) 514 515/* 516** MFP 68901 517 */ 518 519#define MFP_BAS (0xfffffa01) 520struct MFP 521 { 522 u_char par_dt_reg; 523 u_char char_dummy1; 524 u_char active_edge; 525 u_char char_dummy2; 526 u_char data_dir; 527 u_char char_dummy3; 528 u_char int_en_a; 529 u_char char_dummy4; 530 u_char int_en_b; 531 u_char char_dummy5; 532 u_char int_pn_a; 533 u_char char_dummy6; 534 u_char int_pn_b; 535 u_char char_dummy7; 536 u_char int_sv_a; 537 u_char char_dummy8; 538 u_char int_sv_b; 539 u_char char_dummy9; 540 u_char int_mk_a; 541 u_char char_dummy10; 542 u_char int_mk_b; 543 u_char char_dummy11; 544 u_char vec_adr; 545 u_char char_dummy12; 546 u_char tim_ct_a; 547 u_char char_dummy13; 548 u_char tim_ct_b; 549 u_char char_dummy14; 550 u_char tim_ct_cd; 551 u_char char_dummy15; 552 u_char tim_dt_a; 553 u_char char_dummy16; 554 u_char tim_dt_b; 555 u_char char_dummy17; 556 u_char tim_dt_c; 557 u_char char_dummy18; 558 u_char tim_dt_d; 559 u_char char_dummy19; 560 u_char sync_char; 561 u_char char_dummy20; 562 u_char usart_ctr; 563 u_char char_dummy21; 564 u_char rcv_stat; 565 u_char char_dummy22; 566 u_char trn_stat; 567 u_char char_dummy23; 568 u_char usart_dta; 569 }; 570# define st_mfp ((*(volatile struct MFP*)MFP_BAS)) 571 572/* TT's second MFP */ 573 574#define TT_MFP_BAS (0xfffffa81) 575# define tt_mfp ((*(volatile struct MFP*)TT_MFP_BAS)) 576 577 578/* TT System Control Unit */ 579 580#define TT_SCU_BAS (0xffff8e01) 581struct TT_SCU { 582 u_char sys_mask; 583 u_char char_dummy1; 584 u_char sys_stat; 585 u_char char_dummy2; 586 u_char softint; 587 u_char char_dummy3; 588 u_char vmeint; 589 u_char char_dummy4; 590 u_char gp_reg1; 591 u_char char_dummy5; 592 u_char gp_reg2; 593 u_char char_dummy6; 594 u_char vme_mask; 595 u_char char_dummy7; 596 u_char vme_stat; 597}; 598#define tt_scu ((*(volatile struct TT_SCU *)TT_SCU_BAS)) 599 600/* TT real time clock */ 601 602#define TT_RTC_BAS (0xffff8961) 603struct TT_RTC { 604 u_char regsel; 605 u_char dummy; 606 u_char data; 607}; 608#define tt_rtc ((*(volatile struct TT_RTC *)TT_RTC_BAS)) 609 610 611/* 612** ACIA 6850 613 */ 614/* constants for the ACIA registers */ 615 616/* baudrate selection and reset (Baudrate = clock/factor) */ 617#define ACIA_DIV1 0 618#define ACIA_DIV16 1 619#define ACIA_DIV64 2 620#define ACIA_RESET 3 621 622/* character format */ 623#define ACIA_D7E2S (0<<2) /* 7 data, even parity, 2 stop */ 624#define ACIA_D7O2S (1<<2) /* 7 data, odd parity, 2 stop */ 625#define ACIA_D7E1S (2<<2) /* 7 data, even parity, 1 stop */ 626#define ACIA_D7O1S (3<<2) /* 7 data, odd parity, 1 stop */ 627#define ACIA_D8N2S (4<<2) /* 8 data, no parity, 2 stop */ 628#define ACIA_D8N1S (5<<2) /* 8 data, no parity, 1 stop */ 629#define ACIA_D8E1S (6<<2) /* 8 data, even parity, 1 stop */ 630#define ACIA_D8O1S (7<<2) /* 8 data, odd parity, 1 stop */ 631 632/* transmit control */ 633#define ACIA_RLTID (0<<5) /* RTS low, TxINT disabled */ 634#define ACIA_RLTIE (1<<5) /* RTS low, TxINT enabled */ 635#define ACIA_RHTID (2<<5) /* RTS high, TxINT disabled */ 636#define ACIA_RLTIDSB (3<<5) /* RTS low, TxINT disabled, send break */ 637 638/* receive control */ 639#define ACIA_RID (0<<7) /* RxINT disabled */ 640#define ACIA_RIE (1<<7) /* RxINT enabled */ 641 642/* status fields of the ACIA */ 643#define ACIA_RDRF 1 /* Receive Data Register Full */ 644#define ACIA_TDRE (1<<1) /* Transmit Data Register Empty */ 645#define ACIA_DCD (1<<2) /* Data Carrier Detect */ 646#define ACIA_CTS (1<<3) /* Clear To Send */ 647#define ACIA_FE (1<<4) /* Framing Error */ 648#define ACIA_OVRN (1<<5) /* Receiver Overrun */ 649#define ACIA_PE (1<<6) /* Parity Error */ 650#define ACIA_IRQ (1<<7) /* Interrupt Request */ 651 652#define ACIA_BAS (0xfffffc00) 653struct ACIA 654 { 655 u_char key_ctrl; 656 u_char char_dummy1; 657 u_char key_data; 658 u_char char_dummy2; 659 u_char mid_ctrl; 660 u_char char_dummy3; 661 u_char mid_data; 662 }; 663# define acia ((*(volatile struct ACIA*)ACIA_BAS)) 664 665#define TT_DMASND_BAS (0xffff8900) 666struct TT_DMASND { 667 u_char int_ctrl; /* Falcon: Interrupt control */ 668 u_char ctrl; 669 u_char pad2; 670 u_char bas_hi; 671 u_char pad3; 672 u_char bas_mid; 673 u_char pad4; 674 u_char bas_low; 675 u_char pad5; 676 u_char addr_hi; 677 u_char pad6; 678 u_char addr_mid; 679 u_char pad7; 680 u_char addr_low; 681 u_char pad8; 682 u_char end_hi; 683 u_char pad9; 684 u_char end_mid; 685 u_char pad10; 686 u_char end_low; 687 u_char pad11[12]; 688 u_char track_select; /* Falcon */ 689 u_char mode; 690 u_char pad12[14]; 691 /* Falcon only: */ 692 u_short cbar_src; 693 u_short cbar_dst; 694 u_char ext_div; 695 u_char int_div; 696 u_char rec_track_select; 697 u_char dac_src; 698 u_char adc_src; 699 u_char input_gain; 700 u_short output_atten; 701}; 702# define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS)) 703 704#define DMASND_MFP_INT_REPLAY 0x01 705#define DMASND_MFP_INT_RECORD 0x02 706#define DMASND_TIMERA_INT_REPLAY 0x04 707#define DMASND_TIMERA_INT_RECORD 0x08 708 709#define DMASND_CTRL_OFF 0x00 710#define DMASND_CTRL_ON 0x01 711#define DMASND_CTRL_REPEAT 0x02 712#define DMASND_CTRL_RECORD_ON 0x10 713#define DMASND_CTRL_RECORD_OFF 0x00 714#define DMASND_CTRL_RECORD_REPEAT 0x20 715#define DMASND_CTRL_SELECT_REPLAY 0x00 716#define DMASND_CTRL_SELECT_RECORD 0x80 717#define DMASND_MODE_MONO 0x80 718#define DMASND_MODE_STEREO 0x00 719#define DMASND_MODE_8BIT 0x00 720#define DMASND_MODE_16BIT 0x40 /* Falcon only */ 721#define DMASND_MODE_6KHZ 0x00 /* Falcon: mute */ 722#define DMASND_MODE_12KHZ 0x01 723#define DMASND_MODE_25KHZ 0x02 724#define DMASND_MODE_50KHZ 0x03 725 726 727#define DMASNDSetBase(bufstart) \ 728 do { \ 729 tt_dmasnd.bas_hi = (unsigned char)(((bufstart) & 0xff0000) >> 16); \ 730 tt_dmasnd.bas_mid = (unsigned char)(((bufstart) & 0x00ff00) >> 8); \ 731 tt_dmasnd.bas_low = (unsigned char) ((bufstart) & 0x0000ff); \ 732 } while( 0 ) 733 734#define DMASNDGetAdr() ((tt_dmasnd.addr_hi << 16) + \ 735 (tt_dmasnd.addr_mid << 8) + \ 736 (tt_dmasnd.addr_low)) 737 738#define DMASNDSetEnd(bufend) \ 739 do { \ 740 tt_dmasnd.end_hi = (unsigned char)(((bufend) & 0xff0000) >> 16); \ 741 tt_dmasnd.end_mid = (unsigned char)(((bufend) & 0x00ff00) >> 8); \ 742 tt_dmasnd.end_low = (unsigned char) ((bufend) & 0x0000ff); \ 743 } while( 0 ) 744 745 746#define TT_MICROWIRE_BAS (0xffff8922) 747struct TT_MICROWIRE { 748 u_short data; 749 u_short mask; 750}; 751# define tt_microwire ((*(volatile struct TT_MICROWIRE *)TT_MICROWIRE_BAS)) 752 753#define MW_LM1992_ADDR 0x0400 754 755#define MW_LM1992_VOLUME(dB) \ 756 (0x0c0 | ((dB) < -80 ? 0 : (dB) > 0 ? 40 : (((dB) + 80) / 2))) 757#define MW_LM1992_BALLEFT(dB) \ 758 (0x140 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2))) 759#define MW_LM1992_BALRIGHT(dB) \ 760 (0x100 | ((dB) < -40 ? 0 : (dB) > 0 ? 20 : (((dB) + 40) / 2))) 761#define MW_LM1992_TREBLE(dB) \ 762 (0x080 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6))) 763#define MW_LM1992_BASS(dB) \ 764 (0x040 | ((dB) < -12 ? 0 : (dB) > 12 ? 12 : (((dB) / 2) + 6))) 765 766#define MW_LM1992_PSG_LOW 0x000 767#define MW_LM1992_PSG_HIGH 0x001 768#define MW_LM1992_PSG_OFF 0x002 769 770#define MSTE_RTC_BAS (0xfffffc21) 771 772struct MSTE_RTC { 773 u_char sec_ones; 774 u_char dummy1; 775 u_char sec_tens; 776 u_char dummy2; 777 u_char min_ones; 778 u_char dummy3; 779 u_char min_tens; 780 u_char dummy4; 781 u_char hr_ones; 782 u_char dummy5; 783 u_char hr_tens; 784 u_char dummy6; 785 u_char weekday; 786 u_char dummy7; 787 u_char day_ones; 788 u_char dummy8; 789 u_char day_tens; 790 u_char dummy9; 791 u_char mon_ones; 792 u_char dummy10; 793 u_char mon_tens; 794 u_char dummy11; 795 u_char year_ones; 796 u_char dummy12; 797 u_char year_tens; 798 u_char dummy13; 799 u_char mode; 800 u_char dummy14; 801 u_char test; 802 u_char dummy15; 803 u_char reset; 804}; 805 806#define mste_rtc ((*(volatile struct MSTE_RTC *)MSTE_RTC_BAS)) 807 808/* 809** EtherNAT add-on card for Falcon - combined ethernet and USB adapter 810*/ 811 812#define ATARI_ETHERNAT_PHYS_ADDR 0x80000000 813 814#endif /* linux/atarihw.h */ 815 816