LXR linux/arch/m68k/kernel/pcibios.c

   1/*
   2 * pci.c -- basic PCI support code
   3 *
   4 * This program is free software; you can redistribute  it and/or modify it
   5 * under  the terms of  the GNU General  Public License as published by the
   6 * Free Software Foundation;  either version 2 of the  License, or (at your
   7 * option) any later version.
   8 *
   9 * (C) Copyright 2011, Greg Ungerer <gerg@uclinux.org>
  10 */
  11
  12#include <linux/kernel.h>
  13#include <linux/types.h>
  14#include <linux/mm.h>
  15#include <linux/init.h>
  16#include <linux/pci.h>
  17
  18/*
  19 * From arch/i386/kernel/pci-i386.c:
  20 *
  21 * We need to avoid collisions with `mirrored' VGA ports
  22 * and other strange ISA hardware, so we always want the
  23 * addresses to be allocated in the 0x000-0x0ff region
  24 * modulo 0x400.
  25 *
  26 * Why? Because some silly external IO cards only decode
  27 * the low 10 bits of the IO address. The 0x00-0xff region
  28 * is reserved for motherboard devices that decode all 16
  29 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
  30 * but we want to try to avoid allocating at 0x2900-0x2bff
  31 * which might be mirrored at 0x0100-0x03ff..
  32 */
  33resource_size_t pcibios_align_resource(void *data, const struct resource *res,
  34        resource_size_t size, resource_size_t align)
  35{
  36        resource_size_t start = res->start;
  37
  38        if ((res->flags & IORESOURCE_IO) && (start & 0x300))
  39                start = (start + 0x3ff) & ~0x3ff;
  40
  41        start = (start + align - 1) & ~(align - 1);
  42
  43        return start;
  44}
  45
  46/*
  47 * This is taken from the ARM code for this.
  48 */
  49int pcibios_enable_device(struct pci_dev *dev, int mask)
  50{
  51        struct resource *r;
  52        u16 cmd, newcmd;
  53        int idx;
  54
  55        pci_read_config_word(dev, PCI_COMMAND, &cmd);
  56        newcmd = cmd;
  57
  58        for (idx = 0; idx < 6; idx++) {
  59                /* Only set up the requested stuff */
  60                if (!(mask & (1 << idx)))
  61                        continue;
  62
  63                r = dev->resource + idx;
  64                if (!r->start && r->end) {
  65                        pr_err("PCI: Device %s not available because of resource collisions\n",
  66                                pci_name(dev));
  67                        return -EINVAL;
  68                }
  69                if (r->flags & IORESOURCE_IO)
  70                        newcmd |= PCI_COMMAND_IO;
  71                if (r->flags & IORESOURCE_MEM)
  72                        newcmd |= PCI_COMMAND_MEMORY;
  73        }
  74
  75        /*
  76         * Bridges (eg, cardbus bridges) need to be fully enabled
  77         */
  78        if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
  79                newcmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
  80
  81
  82        if (newcmd != cmd) {
  83                pr_info("PCI: enabling device %s (0x%04x -> 0x%04x)\n",
  84                        pci_name(dev), cmd, newcmd);
  85                pci_write_config_word(dev, PCI_COMMAND, newcmd);
  86        }
  87        return 0;
  88}
  89
  90void pcibios_fixup_bus(struct pci_bus *bus)
  91{
  92        struct pci_dev *dev;
  93
  94        list_for_each_entry(dev, &bus->devices, bus_list) {
  95                pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 8);
  96                pci_write_config_byte(dev, PCI_LATENCY_TIMER, 32);
  97        }
  98}
  99
 100char *pcibios_setup(char *str)
 101{
 102        return str;
 103}
 104
 105