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19#include <linux/kernel.h>
20#include <linux/pci.h>
21#include <linux/string.h>
22#include <linux/init.h>
23#include <linux/bootmem.h>
24#include <linux/mm.h>
25#include <linux/list.h>
26#include <linux/syscalls.h>
27#include <linux/irq.h>
28#include <linux/vmalloc.h>
29#include <linux/slab.h>
30#include <linux/of.h>
31#include <linux/of_address.h>
32#include <linux/of_irq.h>
33#include <linux/of_pci.h>
34#include <linux/export.h>
35
36#include <asm/processor.h>
37#include <linux/io.h>
38#include <asm/pci-bridge.h>
39#include <asm/byteorder.h>
40
41static DEFINE_SPINLOCK(hose_spinlock);
42LIST_HEAD(hose_list);
43
44
45static int global_phb_number;
46
47
48resource_size_t isa_mem_base;
49
50unsigned long isa_io_base;
51static int pci_bus_count;
52
53struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
54{
55 struct pci_controller *phb;
56
57 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
58 if (!phb)
59 return NULL;
60 spin_lock(&hose_spinlock);
61 phb->global_number = global_phb_number++;
62 list_add_tail(&phb->list_node, &hose_list);
63 spin_unlock(&hose_spinlock);
64 phb->dn = dev;
65 phb->is_dynamic = mem_init_done;
66 return phb;
67}
68
69void pcibios_free_controller(struct pci_controller *phb)
70{
71 spin_lock(&hose_spinlock);
72 list_del(&phb->list_node);
73 spin_unlock(&hose_spinlock);
74
75 if (phb->is_dynamic)
76 kfree(phb);
77}
78
79static resource_size_t pcibios_io_size(const struct pci_controller *hose)
80{
81 return resource_size(&hose->io_resource);
82}
83
84int pcibios_vaddr_is_ioport(void __iomem *address)
85{
86 int ret = 0;
87 struct pci_controller *hose;
88 resource_size_t size;
89
90 spin_lock(&hose_spinlock);
91 list_for_each_entry(hose, &hose_list, list_node) {
92 size = pcibios_io_size(hose);
93 if (address >= hose->io_base_virt &&
94 address < (hose->io_base_virt + size)) {
95 ret = 1;
96 break;
97 }
98 }
99 spin_unlock(&hose_spinlock);
100 return ret;
101}
102
103unsigned long pci_address_to_pio(phys_addr_t address)
104{
105 struct pci_controller *hose;
106 resource_size_t size;
107 unsigned long ret = ~0;
108
109 spin_lock(&hose_spinlock);
110 list_for_each_entry(hose, &hose_list, list_node) {
111 size = pcibios_io_size(hose);
112 if (address >= hose->io_base_phys &&
113 address < (hose->io_base_phys + size)) {
114 unsigned long base =
115 (unsigned long)hose->io_base_virt - _IO_BASE;
116 ret = base + (address - hose->io_base_phys);
117 break;
118 }
119 }
120 spin_unlock(&hose_spinlock);
121
122 return ret;
123}
124EXPORT_SYMBOL_GPL(pci_address_to_pio);
125
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132
133struct pci_controller *pci_find_hose_for_OF_device(struct device_node *node)
134{
135 while (node) {
136 struct pci_controller *hose, *tmp;
137 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
138 if (hose->dn == node)
139 return hose;
140 node = node->parent;
141 }
142 return NULL;
143}
144
145void __weak pcibios_set_master(struct pci_dev *dev)
146{
147
148}
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166
167static struct resource *__pci_mmap_make_offset(struct pci_dev *dev,
168 resource_size_t *offset,
169 enum pci_mmap_state mmap_state)
170{
171 struct pci_controller *hose = pci_bus_to_host(dev->bus);
172 unsigned long io_offset = 0;
173 int i, res_bit;
174
175 if (!hose)
176 return NULL;
177
178
179 if (mmap_state == pci_mmap_mem) {
180#if 0
181 *offset += hose->pci_mem_offset;
182#endif
183 res_bit = IORESOURCE_MEM;
184 } else {
185 io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
186 *offset += io_offset;
187 res_bit = IORESOURCE_IO;
188 }
189
190
191
192
193
194 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
195 struct resource *rp = &dev->resource[i];
196 int flags = rp->flags;
197
198
199 if (i == PCI_ROM_RESOURCE)
200 flags |= IORESOURCE_MEM;
201
202
203 if ((flags & res_bit) == 0)
204 continue;
205
206
207 if (*offset < (rp->start & PAGE_MASK) || *offset > rp->end)
208 continue;
209
210
211 if (mmap_state == pci_mmap_io)
212 *offset += hose->io_base_phys - io_offset;
213 return rp;
214 }
215
216 return NULL;
217}
218
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221
222
223static pgprot_t __pci_mmap_set_pgprot(struct pci_dev *dev, struct resource *rp,
224 pgprot_t protection,
225 enum pci_mmap_state mmap_state,
226 int write_combine)
227{
228 pgprot_t prot = protection;
229
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235
236 if (mmap_state != pci_mmap_mem)
237 write_combine = 0;
238 else if (write_combine == 0) {
239 if (rp->flags & IORESOURCE_PREFETCH)
240 write_combine = 1;
241 }
242
243 return pgprot_noncached(prot);
244}
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250
251pgprot_t pci_phys_mem_access_prot(struct file *file,
252 unsigned long pfn,
253 unsigned long size,
254 pgprot_t prot)
255{
256 struct pci_dev *pdev = NULL;
257 struct resource *found = NULL;
258 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
259 int i;
260
261 if (page_is_ram(pfn))
262 return prot;
263
264 prot = pgprot_noncached(prot);
265 for_each_pci_dev(pdev) {
266 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
267 struct resource *rp = &pdev->resource[i];
268 int flags = rp->flags;
269
270
271 if ((flags & IORESOURCE_MEM) == 0)
272 continue;
273
274 if (offset < (rp->start & PAGE_MASK) ||
275 offset > rp->end)
276 continue;
277 found = rp;
278 break;
279 }
280 if (found)
281 break;
282 }
283 if (found) {
284 if (found->flags & IORESOURCE_PREFETCH)
285 prot = pgprot_noncached_wc(prot);
286 pci_dev_put(pdev);
287 }
288
289 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
290 (unsigned long long)offset, pgprot_val(prot));
291
292 return prot;
293}
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304
305int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
306 enum pci_mmap_state mmap_state, int write_combine)
307{
308 resource_size_t offset =
309 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
310 struct resource *rp;
311 int ret;
312
313 rp = __pci_mmap_make_offset(dev, &offset, mmap_state);
314 if (rp == NULL)
315 return -EINVAL;
316
317 vma->vm_pgoff = offset >> PAGE_SHIFT;
318 vma->vm_page_prot = __pci_mmap_set_pgprot(dev, rp,
319 vma->vm_page_prot,
320 mmap_state, write_combine);
321
322 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
323 vma->vm_end - vma->vm_start, vma->vm_page_prot);
324
325 return ret;
326}
327
328
329int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
330{
331 unsigned long offset;
332 struct pci_controller *hose = pci_bus_to_host(bus);
333 struct resource *rp = &hose->io_resource;
334 void __iomem *addr;
335
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339
340
341 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
342 offset += port;
343
344 if (!(rp->flags & IORESOURCE_IO))
345 return -ENXIO;
346 if (offset < rp->start || (offset + size) > rp->end)
347 return -ENXIO;
348 addr = hose->io_base_virt + port;
349
350 switch (size) {
351 case 1:
352 *((u8 *)val) = in_8(addr);
353 return 1;
354 case 2:
355 if (port & 1)
356 return -EINVAL;
357 *((u16 *)val) = in_le16(addr);
358 return 2;
359 case 4:
360 if (port & 3)
361 return -EINVAL;
362 *((u32 *)val) = in_le32(addr);
363 return 4;
364 }
365 return -EINVAL;
366}
367
368
369int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
370{
371 unsigned long offset;
372 struct pci_controller *hose = pci_bus_to_host(bus);
373 struct resource *rp = &hose->io_resource;
374 void __iomem *addr;
375
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380
381 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
382 offset += port;
383
384 if (!(rp->flags & IORESOURCE_IO))
385 return -ENXIO;
386 if (offset < rp->start || (offset + size) > rp->end)
387 return -ENXIO;
388 addr = hose->io_base_virt + port;
389
390
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392
393
394
395 switch (size) {
396 case 1:
397 out_8(addr, val >> 24);
398 return 1;
399 case 2:
400 if (port & 1)
401 return -EINVAL;
402 out_le16(addr, val >> 16);
403 return 2;
404 case 4:
405 if (port & 3)
406 return -EINVAL;
407 out_le32(addr, val);
408 return 4;
409 }
410 return -EINVAL;
411}
412
413
414int pci_mmap_legacy_page_range(struct pci_bus *bus,
415 struct vm_area_struct *vma,
416 enum pci_mmap_state mmap_state)
417{
418 struct pci_controller *hose = pci_bus_to_host(bus);
419 resource_size_t offset =
420 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
421 resource_size_t size = vma->vm_end - vma->vm_start;
422 struct resource *rp;
423
424 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
425 pci_domain_nr(bus), bus->number,
426 mmap_state == pci_mmap_mem ? "MEM" : "IO",
427 (unsigned long long)offset,
428 (unsigned long long)(offset + size - 1));
429
430 if (mmap_state == pci_mmap_mem) {
431
432
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436
437
438 if ((offset + size) > hose->isa_mem_size) {
439#ifdef CONFIG_MMU
440 pr_debug("Process %s (pid:%d) mapped non-existing PCI",
441 current->comm, current->pid);
442 pr_debug("legacy memory for 0%04x:%02x\n",
443 pci_domain_nr(bus), bus->number);
444#endif
445 if (vma->vm_flags & VM_SHARED)
446 return shmem_zero_setup(vma);
447 return 0;
448 }
449 offset += hose->isa_mem_phys;
450 } else {
451 unsigned long io_offset = (unsigned long)hose->io_base_virt -
452 _IO_BASE;
453 unsigned long roffset = offset + io_offset;
454 rp = &hose->io_resource;
455 if (!(rp->flags & IORESOURCE_IO))
456 return -ENXIO;
457 if (roffset < rp->start || (roffset + size) > rp->end)
458 return -ENXIO;
459 offset += hose->io_base_phys;
460 }
461 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
462
463 vma->vm_pgoff = offset >> PAGE_SHIFT;
464 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
465 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
466 vma->vm_end - vma->vm_start,
467 vma->vm_page_prot);
468}
469
470void pci_resource_to_user(const struct pci_dev *dev, int bar,
471 const struct resource *rsrc,
472 resource_size_t *start, resource_size_t *end)
473{
474 struct pci_controller *hose = pci_bus_to_host(dev->bus);
475 resource_size_t offset = 0;
476
477 if (hose == NULL)
478 return;
479
480 if (rsrc->flags & IORESOURCE_IO)
481 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
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500#if 0
501 else if (rsrc->flags & IORESOURCE_MEM)
502 offset = hose->pci_mem_offset;
503#endif
504
505 *start = rsrc->start - offset;
506 *end = rsrc->end - offset;
507}
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541
542void pci_process_bridge_OF_ranges(struct pci_controller *hose,
543 struct device_node *dev, int primary)
544{
545 int memno = 0, isa_hole = -1;
546 unsigned long long isa_mb = 0;
547 struct resource *res;
548 struct of_pci_range range;
549 struct of_pci_range_parser parser;
550
551 pr_info("PCI host bridge %s %s ranges:\n",
552 dev->full_name, primary ? "(primary)" : "");
553
554
555 if (of_pci_range_parser_init(&parser, dev))
556 return;
557
558 pr_debug("Parsing ranges property...\n");
559 for_each_of_pci_range(&parser, &range) {
560
561 pr_debug("pci_space: 0x%08x pci_addr:0x%016llx ",
562 range.pci_space, range.pci_addr);
563 pr_debug("cpu_addr:0x%016llx size:0x%016llx\n",
564 range.cpu_addr, range.size);
565
566
567
568
569
570
571 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
572 continue;
573
574
575 res = NULL;
576 switch (range.flags & IORESOURCE_TYPE_BITS) {
577 case IORESOURCE_IO:
578 pr_info(" IO 0x%016llx..0x%016llx -> 0x%016llx\n",
579 range.cpu_addr, range.cpu_addr + range.size - 1,
580 range.pci_addr);
581
582
583 if (hose->pci_io_size) {
584 pr_info(" \\--> Skipped (too many) !\n");
585 continue;
586 }
587
588 if (range.size > 0x01000000)
589 range.size = 0x01000000;
590
591
592 hose->io_base_virt = ioremap(range.cpu_addr,
593 range.size);
594
595
596 if (primary)
597 isa_io_base =
598 (unsigned long)hose->io_base_virt;
599
600
601
602 hose->pci_io_size = range.pci_addr + range.size;
603 hose->io_base_phys = range.cpu_addr - range.pci_addr;
604
605
606 res = &hose->io_resource;
607 range.cpu_addr = range.pci_addr;
608
609 break;
610 case IORESOURCE_MEM:
611 pr_info(" MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
612 range.cpu_addr, range.cpu_addr + range.size - 1,
613 range.pci_addr,
614 (range.pci_space & 0x40000000) ?
615 "Prefetch" : "");
616
617
618 if (memno >= 3) {
619 pr_info(" \\--> Skipped (too many) !\n");
620 continue;
621 }
622
623 if (range.pci_addr == 0) {
624 isa_mb = range.cpu_addr;
625 isa_hole = memno;
626 if (primary || isa_mem_base == 0)
627 isa_mem_base = range.cpu_addr;
628 hose->isa_mem_phys = range.cpu_addr;
629 hose->isa_mem_size = range.size;
630 }
631
632
633
634
635
636 if (memno == 0 ||
637 (isa_hole >= 0 && range.pci_addr != 0 &&
638 hose->pci_mem_offset == isa_mb))
639 hose->pci_mem_offset = range.cpu_addr -
640 range.pci_addr;
641 else if (range.pci_addr != 0 &&
642 hose->pci_mem_offset != range.cpu_addr -
643 range.pci_addr) {
644 pr_info(" \\--> Skipped (offset mismatch) !\n");
645 continue;
646 }
647
648
649 res = &hose->mem_resources[memno++];
650 break;
651 }
652 if (res != NULL) {
653 res->name = dev->full_name;
654 res->flags = range.flags;
655 res->start = range.cpu_addr;
656 res->end = range.cpu_addr + range.size - 1;
657 res->parent = res->child = res->sibling = NULL;
658 }
659 }
660
661
662
663
664
665 if (isa_hole >= 0 && hose->pci_mem_offset != isa_mb) {
666 unsigned int next = isa_hole + 1;
667 pr_info(" Removing ISA hole at 0x%016llx\n", isa_mb);
668 if (next < memno)
669 memmove(&hose->mem_resources[isa_hole],
670 &hose->mem_resources[next],
671 sizeof(struct resource) * (memno - next));
672 hose->mem_resources[--memno].flags = 0;
673 }
674}
675
676
677int pci_proc_domain(struct pci_bus *bus)
678{
679 return pci_domain_nr(bus);
680}
681
682
683
684
685static void pcibios_fixup_resources(struct pci_dev *dev)
686{
687
688}
689DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
690
691
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694
695
696static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
697 struct resource *res)
698{
699 struct pci_controller *hose = pci_bus_to_host(bus);
700 struct pci_dev *dev = bus->self;
701 resource_size_t offset;
702 u16 command;
703 int i;
704
705
706 if (res->flags & IORESOURCE_MEM) {
707
708
709
710 if (res->start != hose->pci_mem_offset)
711 return 0;
712
713
714
715
716 pci_read_config_word(dev, PCI_COMMAND, &command);
717 if ((command & PCI_COMMAND_MEMORY) == 0)
718 return 1;
719
720
721
722
723
724 for (i = 0; i < 3; i++) {
725 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
726 hose->mem_resources[i].start == hose->pci_mem_offset)
727 return 0;
728 }
729
730
731
732
733 return 1;
734 } else {
735
736 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
737 if (((res->start - offset) & 0xfffffffful) != 0)
738 return 0;
739
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741
742
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745
746 pci_read_config_word(dev, PCI_COMMAND, &command);
747 if (command & PCI_COMMAND_IO)
748 return 0;
749
750
751
752
753 return 1;
754 }
755}
756
757
758static void pcibios_fixup_bridge(struct pci_bus *bus)
759{
760 struct resource *res;
761 int i;
762
763 struct pci_dev *dev = bus->self;
764
765 pci_bus_for_each_resource(bus, res, i) {
766 if (!res)
767 continue;
768 if (!res->flags)
769 continue;
770 if (i >= 3 && bus->self->transparent)
771 continue;
772
773 pr_debug("PCI:%s Bus rsrc %d %016llx-%016llx [%x] fixup...\n",
774 pci_name(dev), i,
775 (unsigned long long)res->start,
776 (unsigned long long)res->end,
777 (unsigned int)res->flags);
778
779
780
781
782 if (pcibios_uninitialized_bridge_resource(bus, res)) {
783 res->flags = 0;
784 pr_debug("PCI:%s (unassigned)\n",
785 pci_name(dev));
786 } else {
787 pr_debug("PCI:%s %016llx-%016llx\n",
788 pci_name(dev),
789 (unsigned long long)res->start,
790 (unsigned long long)res->end);
791 }
792 }
793}
794
795void pcibios_setup_bus_self(struct pci_bus *bus)
796{
797
798 if (bus->self != NULL)
799 pcibios_fixup_bridge(bus);
800}
801
802void pcibios_setup_bus_devices(struct pci_bus *bus)
803{
804 struct pci_dev *dev;
805
806 pr_debug("PCI: Fixup bus devices %d (%s)\n",
807 bus->number, bus->self ? pci_name(bus->self) : "PHB");
808
809 list_for_each_entry(dev, &bus->devices, bus_list) {
810
811 dev->dev.of_node = pci_device_to_OF_node(dev);
812
813
814
815
816 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
817
818
819 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
820 }
821}
822
823void pcibios_fixup_bus(struct pci_bus *bus)
824{
825
826}
827EXPORT_SYMBOL(pcibios_fixup_bus);
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842resource_size_t pcibios_align_resource(void *data, const struct resource *res,
843 resource_size_t size, resource_size_t align)
844{
845 return res->start;
846}
847EXPORT_SYMBOL(pcibios_align_resource);
848
849int pcibios_add_device(struct pci_dev *dev)
850{
851 dev->irq = of_irq_parse_and_map_pci(dev, 0, 0);
852
853 return 0;
854}
855EXPORT_SYMBOL(pcibios_add_device);
856
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859
860
861static int __init reparent_resources(struct resource *parent,
862 struct resource *res)
863{
864 struct resource *p, **pp;
865 struct resource **firstpp = NULL;
866
867 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
868 if (p->end < res->start)
869 continue;
870 if (res->end < p->start)
871 break;
872 if (p->start < res->start || p->end > res->end)
873 return -1;
874 if (firstpp == NULL)
875 firstpp = pp;
876 }
877 if (firstpp == NULL)
878 return -1;
879 res->parent = parent;
880 res->child = *firstpp;
881 res->sibling = *pp;
882 *firstpp = res;
883 *pp = NULL;
884 for (p = res->child; p != NULL; p = p->sibling) {
885 p->parent = res;
886 pr_debug("PCI: Reparented %s [%llx..%llx] under %s\n",
887 p->name,
888 (unsigned long long)p->start,
889 (unsigned long long)p->end, res->name);
890 }
891 return 0;
892}
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927static void pcibios_allocate_bus_resources(struct pci_bus *bus)
928{
929 struct pci_bus *b;
930 int i;
931 struct resource *res, *pr;
932
933 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
934 pci_domain_nr(bus), bus->number);
935
936 pci_bus_for_each_resource(bus, res, i) {
937 if (!res || !res->flags
938 || res->start > res->end || res->parent)
939 continue;
940 if (bus->parent == NULL)
941 pr = (res->flags & IORESOURCE_IO) ?
942 &ioport_resource : &iomem_resource;
943 else {
944
945
946
947
948
949
950 pr = pci_find_parent_resource(bus->self, res);
951 if (pr == res) {
952
953
954
955
956 continue;
957 }
958 }
959
960 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %016llx-%016llx ",
961 bus->self ? pci_name(bus->self) : "PHB",
962 bus->number, i,
963 (unsigned long long)res->start,
964 (unsigned long long)res->end);
965 pr_debug("[0x%x], parent %p (%s)\n",
966 (unsigned int)res->flags,
967 pr, (pr && pr->name) ? pr->name : "nil");
968
969 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
970 struct pci_dev *dev = bus->self;
971
972 if (request_resource(pr, res) == 0)
973 continue;
974
975
976
977
978
979 if (reparent_resources(pr, res) == 0)
980 continue;
981
982 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
983 pci_claim_bridge_resource(dev,
984 i + PCI_BRIDGE_RESOURCES) == 0)
985 continue;
986
987 }
988 pr_warn("PCI: Cannot allocate resource region ");
989 pr_cont("%d of PCI bridge %d, will remap\n", i, bus->number);
990 res->start = res->end = 0;
991 res->flags = 0;
992 }
993
994 list_for_each_entry(b, &bus->children, node)
995 pcibios_allocate_bus_resources(b);
996}
997
998static inline void alloc_resource(struct pci_dev *dev, int idx)
999{
1000 struct resource *pr, *r = &dev->resource[idx];
1001
1002 pr_debug("PCI: Allocating %s: Resource %d: %016llx..%016llx [%x]\n",
1003 pci_name(dev), idx,
1004 (unsigned long long)r->start,
1005 (unsigned long long)r->end,
1006 (unsigned int)r->flags);
1007
1008 pr = pci_find_parent_resource(dev, r);
1009 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1010 request_resource(pr, r) < 0) {
1011 pr_warn("PCI: Cannot allocate resource region %d ", idx);
1012 pr_cont("of device %s, will remap\n", pci_name(dev));
1013 if (pr)
1014 pr_debug("PCI: parent is %p: %016llx-%016llx [%x]\n",
1015 pr,
1016 (unsigned long long)pr->start,
1017 (unsigned long long)pr->end,
1018 (unsigned int)pr->flags);
1019
1020 r->flags |= IORESOURCE_UNSET;
1021 r->end -= r->start;
1022 r->start = 0;
1023 }
1024}
1025
1026static void __init pcibios_allocate_resources(int pass)
1027{
1028 struct pci_dev *dev = NULL;
1029 int idx, disabled;
1030 u16 command;
1031 struct resource *r;
1032
1033 for_each_pci_dev(dev) {
1034 pci_read_config_word(dev, PCI_COMMAND, &command);
1035 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1036 r = &dev->resource[idx];
1037 if (r->parent)
1038 continue;
1039 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1040 continue;
1041
1042
1043
1044 if (idx == PCI_ROM_RESOURCE)
1045 disabled = 1;
1046 if (r->flags & IORESOURCE_IO)
1047 disabled = !(command & PCI_COMMAND_IO);
1048 else
1049 disabled = !(command & PCI_COMMAND_MEMORY);
1050 if (pass == disabled)
1051 alloc_resource(dev, idx);
1052 }
1053 if (pass)
1054 continue;
1055 r = &dev->resource[PCI_ROM_RESOURCE];
1056 if (r->flags) {
1057
1058
1059
1060 u32 reg;
1061 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1062 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1063 pr_debug("PCI: Switching off ROM of %s\n",
1064 pci_name(dev));
1065 r->flags &= ~IORESOURCE_ROM_ENABLE;
1066 pci_write_config_dword(dev, dev->rom_base_reg,
1067 reg & ~PCI_ROM_ADDRESS_ENABLE);
1068 }
1069 }
1070 }
1071}
1072
1073static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1074{
1075 struct pci_controller *hose = pci_bus_to_host(bus);
1076 resource_size_t offset;
1077 struct resource *res, *pres;
1078 int i;
1079
1080 pr_debug("Reserving legacy ranges for domain %04x\n",
1081 pci_domain_nr(bus));
1082
1083
1084 if (!(hose->io_resource.flags & IORESOURCE_IO))
1085 goto no_io;
1086 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1087 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1088 BUG_ON(res == NULL);
1089 res->name = "Legacy IO";
1090 res->flags = IORESOURCE_IO;
1091 res->start = offset;
1092 res->end = (offset + 0xfff) & 0xfffffffful;
1093 pr_debug("Candidate legacy IO: %pR\n", res);
1094 if (request_resource(&hose->io_resource, res)) {
1095 pr_debug("PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1096 pci_domain_nr(bus), bus->number, res);
1097 kfree(res);
1098 }
1099
1100 no_io:
1101
1102 offset = hose->pci_mem_offset;
1103 pr_debug("hose mem offset: %016llx\n", (unsigned long long)offset);
1104 for (i = 0; i < 3; i++) {
1105 pres = &hose->mem_resources[i];
1106 if (!(pres->flags & IORESOURCE_MEM))
1107 continue;
1108 pr_debug("hose mem res: %pR\n", pres);
1109 if ((pres->start - offset) <= 0xa0000 &&
1110 (pres->end - offset) >= 0xbffff)
1111 break;
1112 }
1113 if (i >= 3)
1114 return;
1115 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1116 BUG_ON(res == NULL);
1117 res->name = "Legacy VGA memory";
1118 res->flags = IORESOURCE_MEM;
1119 res->start = 0xa0000 + offset;
1120 res->end = 0xbffff + offset;
1121 pr_debug("Candidate VGA memory: %pR\n", res);
1122 if (request_resource(pres, res)) {
1123 pr_debug("PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1124 pci_domain_nr(bus), bus->number, res);
1125 kfree(res);
1126 }
1127}
1128
1129void __init pcibios_resource_survey(void)
1130{
1131 struct pci_bus *b;
1132
1133
1134
1135
1136 list_for_each_entry(b, &pci_root_buses, node)
1137 pcibios_allocate_bus_resources(b);
1138
1139 pcibios_allocate_resources(0);
1140 pcibios_allocate_resources(1);
1141
1142
1143
1144
1145
1146 list_for_each_entry(b, &pci_root_buses, node)
1147 pcibios_reserve_legacy_regions(b);
1148
1149
1150 pr_debug("PCI: Assigning unassigned resources...\n");
1151 pci_assign_unassigned_resources();
1152}
1153
1154
1155
1156
1157
1158
1159void pcibios_claim_one_bus(struct pci_bus *bus)
1160{
1161 struct pci_dev *dev;
1162 struct pci_bus *child_bus;
1163
1164 list_for_each_entry(dev, &bus->devices, bus_list) {
1165 int i;
1166
1167 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1168 struct resource *r = &dev->resource[i];
1169
1170 if (r->parent || !r->start || !r->flags)
1171 continue;
1172
1173 pr_debug("PCI: Claiming %s: ", pci_name(dev));
1174 pr_debug("Resource %d: %016llx..%016llx [%x]\n",
1175 i, (unsigned long long)r->start,
1176 (unsigned long long)r->end,
1177 (unsigned int)r->flags);
1178
1179 if (pci_claim_resource(dev, i) == 0)
1180 continue;
1181
1182 pci_claim_bridge_resource(dev, i);
1183 }
1184 }
1185
1186 list_for_each_entry(child_bus, &bus->children, node)
1187 pcibios_claim_one_bus(child_bus);
1188}
1189EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1190
1191
1192
1193
1194
1195
1196
1197
1198void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1199{
1200 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1201 pci_domain_nr(bus), bus->number);
1202
1203
1204 pcibios_allocate_bus_resources(bus);
1205 pcibios_claim_one_bus(bus);
1206
1207
1208 pci_bus_add_devices(bus);
1209
1210
1211
1212}
1213EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1214
1215static void pcibios_setup_phb_resources(struct pci_controller *hose,
1216 struct list_head *resources)
1217{
1218 unsigned long io_offset;
1219 struct resource *res;
1220 int i;
1221
1222
1223 res = &hose->io_resource;
1224
1225
1226 io_offset = (unsigned long)hose->io_base_virt - isa_io_base;
1227 res->start = (res->start + io_offset) & 0xffffffffu;
1228 res->end = (res->end + io_offset) & 0xffffffffu;
1229
1230 if (!res->flags) {
1231 pr_warn("PCI: I/O resource not set for host ");
1232 pr_cont("bridge %s (domain %d)\n",
1233 hose->dn->full_name, hose->global_number);
1234
1235 res->start = (unsigned long)hose->io_base_virt - isa_io_base;
1236 res->end = res->start + IO_SPACE_LIMIT;
1237 res->flags = IORESOURCE_IO;
1238 }
1239 pci_add_resource_offset(resources, res,
1240 (__force resource_size_t)(hose->io_base_virt - _IO_BASE));
1241
1242 pr_debug("PCI: PHB IO resource = %016llx-%016llx [%lx]\n",
1243 (unsigned long long)res->start,
1244 (unsigned long long)res->end,
1245 (unsigned long)res->flags);
1246
1247
1248 for (i = 0; i < 3; ++i) {
1249 res = &hose->mem_resources[i];
1250 if (!res->flags) {
1251 if (i > 0)
1252 continue;
1253 pr_err("PCI: Memory resource 0 not set for ");
1254 pr_cont("host bridge %s (domain %d)\n",
1255 hose->dn->full_name, hose->global_number);
1256
1257
1258 res->start = hose->pci_mem_offset;
1259 res->end = (resource_size_t)-1LL;
1260 res->flags = IORESOURCE_MEM;
1261
1262 }
1263 pci_add_resource_offset(resources, res, hose->pci_mem_offset);
1264
1265 pr_debug("PCI: PHB MEM resource %d = %016llx-%016llx [%lx]\n",
1266 i, (unsigned long long)res->start,
1267 (unsigned long long)res->end,
1268 (unsigned long)res->flags);
1269 }
1270
1271 pr_debug("PCI: PHB MEM offset = %016llx\n",
1272 (unsigned long long)hose->pci_mem_offset);
1273 pr_debug("PCI: PHB IO offset = %08lx\n",
1274 (unsigned long)hose->io_base_virt - _IO_BASE);
1275}
1276
1277static void pcibios_scan_phb(struct pci_controller *hose)
1278{
1279 LIST_HEAD(resources);
1280 struct pci_bus *bus;
1281 struct device_node *node = hose->dn;
1282
1283 pr_debug("PCI: Scanning PHB %s\n", of_node_full_name(node));
1284
1285 pcibios_setup_phb_resources(hose, &resources);
1286
1287 bus = pci_scan_root_bus(hose->parent, hose->first_busno,
1288 hose->ops, hose, &resources);
1289 if (bus == NULL) {
1290 pr_err("Failed to create bus for PCI domain %04x\n",
1291 hose->global_number);
1292 pci_free_resource_list(&resources);
1293 return;
1294 }
1295 bus->busn_res.start = hose->first_busno;
1296 hose->bus = bus;
1297
1298 hose->last_busno = bus->busn_res.end;
1299}
1300
1301static int __init pcibios_init(void)
1302{
1303 struct pci_controller *hose, *tmp;
1304 int next_busno = 0;
1305
1306 pr_info("PCI: Probing PCI hardware\n");
1307
1308
1309 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1310 hose->last_busno = 0xff;
1311 pcibios_scan_phb(hose);
1312 if (next_busno <= hose->last_busno)
1313 next_busno = hose->last_busno + 1;
1314 }
1315 pci_bus_count = next_busno;
1316
1317
1318 pcibios_resource_survey();
1319 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
1320 if (hose->bus)
1321 pci_bus_add_devices(hose->bus);
1322 }
1323
1324 return 0;
1325}
1326
1327subsys_initcall(pcibios_init);
1328
1329static struct pci_controller *pci_bus_to_hose(int bus)
1330{
1331 struct pci_controller *hose, *tmp;
1332
1333 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
1334 if (bus >= hose->first_busno && bus <= hose->last_busno)
1335 return hose;
1336 return NULL;
1337}
1338
1339
1340
1341
1342
1343
1344
1345long sys_pciconfig_iobase(long which, unsigned long bus, unsigned long devfn)
1346{
1347 struct pci_controller *hose;
1348 long result = -EOPNOTSUPP;
1349
1350 hose = pci_bus_to_hose(bus);
1351 if (!hose)
1352 return -ENODEV;
1353
1354 switch (which) {
1355 case IOBASE_BRIDGE_NUMBER:
1356 return (long)hose->first_busno;
1357 case IOBASE_MEMORY:
1358 return (long)hose->pci_mem_offset;
1359 case IOBASE_IO:
1360 return (long)hose->io_base_phys;
1361 case IOBASE_ISA_IO:
1362 return (long)isa_io_base;
1363 case IOBASE_ISA_MEM:
1364 return (long)isa_mem_base;
1365 }
1366
1367 return result;
1368}
1369
1370
1371
1372
1373
1374#define NULL_PCI_OP(rw, size, type) \
1375static int \
1376null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1377{ \
1378 return PCIBIOS_DEVICE_NOT_FOUND; \
1379}
1380
1381static int
1382null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1383 int len, u32 *val)
1384{
1385 return PCIBIOS_DEVICE_NOT_FOUND;
1386}
1387
1388static int
1389null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1390 int len, u32 val)
1391{
1392 return PCIBIOS_DEVICE_NOT_FOUND;
1393}
1394
1395static struct pci_ops null_pci_ops = {
1396 .read = null_read_config,
1397 .write = null_write_config,
1398};
1399
1400
1401
1402
1403
1404static struct pci_bus *
1405fake_pci_bus(struct pci_controller *hose, int busnr)
1406{
1407 static struct pci_bus bus;
1408
1409 if (!hose)
1410 pr_err("Can't find hose for PCI bus %d!\n", busnr);
1411
1412 bus.number = busnr;
1413 bus.sysdata = hose;
1414 bus.ops = hose ? hose->ops : &null_pci_ops;
1415 return &bus;
1416}
1417
1418#define EARLY_PCI_OP(rw, size, type) \
1419int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1420 int devfn, int offset, type value) \
1421{ \
1422 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1423 devfn, offset, value); \
1424}
1425
1426EARLY_PCI_OP(read, byte, u8 *)
1427EARLY_PCI_OP(read, word, u16 *)
1428EARLY_PCI_OP(read, dword, u32 *)
1429EARLY_PCI_OP(write, byte, u8)
1430EARLY_PCI_OP(write, word, u16)
1431EARLY_PCI_OP(write, dword, u32)
1432
1433int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1434 int cap)
1435{
1436 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1437}
1438
1439