LXR linux/arch/mips/include/asm/dma.h

   1/*
   2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
   3 * Written by Hennus Bergman, 1992.
   4 * High DMA channel support & info by Hannu Savolainen
   5 * and John Boyd, Nov. 1992.
   6 *
   7 * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
   8 * and can only be used for expansion cards. Onboard DMA controllers, such
   9 * as the R4030 on Jazz boards behave totally different!
  10 */
  11
  12#ifndef _ASM_DMA_H
  13#define _ASM_DMA_H
  14
  15#include <asm/io.h>                     /* need byte IO */
  16#include <linux/spinlock.h>             /* And spinlocks */
  17#include <linux/delay.h>
  18
  19
  20#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
  21#define dma_outb        outb_p
  22#else
  23#define dma_outb        outb
  24#endif
  25
  26#define dma_inb         inb
  27
  28/*
  29 * NOTES about DMA transfers:
  30 *
  31 *  controller 1: channels 0-3, byte operations, ports 00-1F
  32 *  controller 2: channels 4-7, word operations, ports C0-DF
  33 *
  34 *  - ALL registers are 8 bits only, regardless of transfer size
  35 *  - channel 4 is not used - cascades 1 into 2.
  36 *  - channels 0-3 are byte - addresses/counts are for physical bytes
  37 *  - channels 5-7 are word - addresses/counts are for physical words
  38 *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
  39 *  - transfer count loaded to registers is 1 less than actual count
  40 *  - controller 2 offsets are all even (2x offsets for controller 1)
  41 *  - page registers for 5-7 don't use data bit 0, represent 128K pages
  42 *  - page registers for 0-3 use bit 0, represent 64K pages
  43 *
  44 * DMA transfers are limited to the lower 16MB of _physical_ memory.
  45 * Note that addresses loaded into registers must be _physical_ addresses,
  46 * not logical addresses (which may differ if paging is active).
  47 *
  48 *  Address mapping for channels 0-3:
  49 *
  50 *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
  51 *    |  ...  |   |  ... |   |  ... |
  52 *    |  ...  |   |  ... |   |  ... |
  53 *    |  ...  |   |  ... |   |  ... |
  54 *   P7  ...  P0  A7 ... A0  A7 ... A0
  55 * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
  56 *
  57 *  Address mapping for channels 5-7:
  58 *
  59 *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
  60 *    |  ...  |   \   \   ... \  \  \  ... \  \
  61 *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
  62 *    |  ...  |     \   \   ... \  \  \  ... \
  63 *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
  64 * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
  65 *
  66 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
  67 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
  68 * the hardware level, so odd-byte transfers aren't possible).
  69 *
  70 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
  71 * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
  72 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
  73 *
  74 */
  75
  76#ifndef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN
  77#define MAX_DMA_CHANNELS        8
  78#endif
  79
  80/*
  81 * The maximum address in KSEG0 that we can perform a DMA transfer to on this
  82 * platform.  This describes only the PC style part of the DMA logic like on
  83 * Deskstations or Acer PICA but not the much more versatile DMA logic used
  84 * for the local devices on Acer PICA or Magnums.
  85 */
  86#if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP28)
  87/* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */
  88#define MAX_DMA_ADDRESS         PAGE_OFFSET
  89#else
  90#define MAX_DMA_ADDRESS         (PAGE_OFFSET + 0x01000000)
  91#endif
  92#define MAX_DMA_PFN             PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
  93
  94#ifndef MAX_DMA32_PFN
  95#define MAX_DMA32_PFN           (1UL << (32 - PAGE_SHIFT))
  96#endif
  97
  98/* 8237 DMA controllers */
  99#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
 100#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
 101
 102/* DMA controller registers */
 103#define DMA1_CMD_REG            0x08    /* command register (w) */
 104#define DMA1_STAT_REG           0x08    /* status register (r) */
 105#define DMA1_REQ_REG            0x09    /* request register (w) */
 106#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
 107#define DMA1_MODE_REG           0x0B    /* mode register (w) */
 108#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
 109#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
 110#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
 111#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
 112#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
 113
 114#define DMA2_CMD_REG            0xD0    /* command register (w) */
 115#define DMA2_STAT_REG           0xD0    /* status register (r) */
 116#define DMA2_REQ_REG            0xD2    /* request register (w) */
 117#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
 118#define DMA2_MODE_REG           0xD6    /* mode register (w) */
 119#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
 120#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
 121#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
 122#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
 123#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
 124
 125#define DMA_ADDR_0              0x00    /* DMA address registers */
 126#define DMA_ADDR_1              0x02
 127#define DMA_ADDR_2              0x04
 128#define DMA_ADDR_3              0x06
 129#define DMA_ADDR_4              0xC0
 130#define DMA_ADDR_5              0xC4
 131#define DMA_ADDR_6              0xC8
 132#define DMA_ADDR_7              0xCC
 133
 134#define DMA_CNT_0               0x01    /* DMA count registers */
 135#define DMA_CNT_1               0x03
 136#define DMA_CNT_2               0x05
 137#define DMA_CNT_3               0x07
 138#define DMA_CNT_4               0xC2
 139#define DMA_CNT_5               0xC6
 140#define DMA_CNT_6               0xCA
 141#define DMA_CNT_7               0xCE
 142
 143#define DMA_PAGE_0              0x87    /* DMA page registers */
 144#define DMA_PAGE_1              0x83
 145#define DMA_PAGE_2              0x81
 146#define DMA_PAGE_3              0x82
 147#define DMA_PAGE_5              0x8B
 148#define DMA_PAGE_6              0x89
 149#define DMA_PAGE_7              0x8A
 150
 151#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
 152#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
 153#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
 154
 155#define DMA_AUTOINIT    0x10
 156
 157extern spinlock_t  dma_spin_lock;
 158
 159static __inline__ unsigned long claim_dma_lock(void)
 160{
 161        unsigned long flags;
 162        spin_lock_irqsave(&dma_spin_lock, flags);
 163        return flags;
 164}
 165
 166static __inline__ void release_dma_lock(unsigned long flags)
 167{
 168        spin_unlock_irqrestore(&dma_spin_lock, flags);
 169}
 170
 171/* enable/disable a specific DMA channel */
 172static __inline__ void enable_dma(unsigned int dmanr)
 173{
 174        if (dmanr<=3)
 175                dma_outb(dmanr,  DMA1_MASK_REG);
 176        else
 177                dma_outb(dmanr & 3,  DMA2_MASK_REG);
 178}
 179
 180static __inline__ void disable_dma(unsigned int dmanr)
 181{
 182        if (dmanr<=3)
 183                dma_outb(dmanr | 4,  DMA1_MASK_REG);
 184        else
 185                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
 186}
 187
 188/* Clear the 'DMA Pointer Flip Flop'.
 189 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
 190 * Use this once to initialize the FF to a known state.
 191 * After that, keep track of it. :-)
 192 * --- In order to do that, the DMA routines below should ---
 193 * --- only be used while holding the DMA lock ! ---
 194 */
 195static __inline__ void clear_dma_ff(unsigned int dmanr)
 196{
 197        if (dmanr<=3)
 198                dma_outb(0,  DMA1_CLEAR_FF_REG);
 199        else
 200                dma_outb(0,  DMA2_CLEAR_FF_REG);
 201}
 202
 203/* set mode (above) for a specific DMA channel */
 204static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
 205{
 206        if (dmanr<=3)
 207                dma_outb(mode | dmanr,  DMA1_MODE_REG);
 208        else
 209                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
 210}
 211
 212/* Set only the page register bits of the transfer address.
 213 * This is used for successive transfers when we know the contents of
 214 * the lower 16 bits of the DMA current address register, but a 64k boundary
 215 * may have been crossed.
 216 */
 217static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
 218{
 219        switch(dmanr) {
 220                case 0:
 221                        dma_outb(pagenr, DMA_PAGE_0);
 222                        break;
 223                case 1:
 224                        dma_outb(pagenr, DMA_PAGE_1);
 225                        break;
 226                case 2:
 227                        dma_outb(pagenr, DMA_PAGE_2);
 228                        break;
 229                case 3:
 230                        dma_outb(pagenr, DMA_PAGE_3);
 231                        break;
 232                case 5:
 233                        dma_outb(pagenr & 0xfe, DMA_PAGE_5);
 234                        break;
 235                case 6:
 236                        dma_outb(pagenr & 0xfe, DMA_PAGE_6);
 237                        break;
 238                case 7:
 239                        dma_outb(pagenr & 0xfe, DMA_PAGE_7);
 240                        break;
 241        }
 242}
 243
 244
 245/* Set transfer address & page bits for specific DMA channel.
 246 * Assumes dma flipflop is clear.
 247 */
 248static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
 249{
 250        set_dma_page(dmanr, a>>16);
 251        if (dmanr <= 3)  {
 252            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 253            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
 254        }  else  {
 255            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 256            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
 257        }
 258}
 259
 260
 261/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
 262 * a specific DMA channel.
 263 * You must ensure the parameters are valid.
 264 * NOTE: from a manual: "the number of transfers is one more
 265 * than the initial word count"! This is taken into account.
 266 * Assumes dma flip-flop is clear.
 267 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
 268 */
 269static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
 270{
 271        count--;
 272        if (dmanr <= 3)  {
 273            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 274            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
 275        } else {
 276            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 277            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
 278        }
 279}
 280
 281
 282/* Get DMA residue count. After a DMA transfer, this
 283 * should return zero. Reading this while a DMA transfer is
 284 * still in progress will return unpredictable results.
 285 * If called before the channel has been used, it may return 1.
 286 * Otherwise, it returns the number of _bytes_ left to transfer.
 287 *
 288 * Assumes DMA flip-flop is clear.
 289 */
 290static __inline__ int get_dma_residue(unsigned int dmanr)
 291{
 292        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
 293                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
 294
 295        /* using short to get 16-bit wrap around */
 296        unsigned short count;
 297
 298        count = 1 + dma_inb(io_port);
 299        count += dma_inb(io_port) << 8;
 300
 301        return (dmanr<=3)? count : (count<<1);
 302}
 303
 304
 305/* These are in kernel/dma.c: */
 306extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
 307extern void free_dma(unsigned int dmanr);       /* release it again */
 308
 309/* From PCI */
 310
 311#ifdef CONFIG_PCI
 312extern int isa_dma_bridge_buggy;
 313#else
 314#define isa_dma_bridge_buggy    (0)
 315#endif
 316
 317#endif /* _ASM_DMA_H */
 318