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12#include <linux/types.h>
13#include <linux/pci.h>
14#include <linux/io.h>
15#include <linux/init.h>
16#include <linux/delay.h>
17#include <linux/interrupt.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/of_irq.h>
21#include <linux/of_pci.h>
22#include <linux/reset.h>
23#include <linux/platform_device.h>
24
25#include <asm/mach-ralink/ralink_regs.h>
26#include <asm/mach-ralink/mt7620.h>
27
28#define RALINK_PCI_IO_MAP_BASE 0x10160000
29#define RALINK_PCI_MEMORY_BASE 0x0
30
31#define RALINK_INT_PCIE0 4
32
33#define RALINK_CLKCFG1 0x30
34#define RALINK_GPIOMODE 0x60
35
36#define PPLL_CFG1 0x9c
37#define PDRV_SW_SET BIT(23)
38
39#define PPLL_DRV 0xa0
40#define PDRV_SW_SET (1<<31)
41#define LC_CKDRVPD (1<<19)
42#define LC_CKDRVOHZ (1<<18)
43#define LC_CKDRVHZ (1<<17)
44#define LC_CKTEST (1<<16)
45
46
47#define RALINK_PCI_PCICFG_ADDR 0x00
48#define PCIRST BIT(1)
49
50#define RALINK_PCI_PCIENA 0x0C
51#define PCIINT2 BIT(20)
52
53#define RALINK_PCI_CONFIG_ADDR 0x20
54#define RALINK_PCI_CONFIG_DATA_VIRT_REG 0x24
55#define RALINK_PCI_MEMBASE 0x28
56#define RALINK_PCI_IOBASE 0x2C
57
58
59#define RALINK_PCI0_BAR0SETUP_ADDR 0x10
60#define RALINK_PCI0_IMBASEBAR0_ADDR 0x18
61#define RALINK_PCI0_ID 0x30
62#define RALINK_PCI0_CLASS 0x34
63#define RALINK_PCI0_SUBID 0x38
64#define RALINK_PCI0_STATUS 0x50
65#define PCIE_LINK_UP_ST BIT(0)
66
67#define PCIEPHY0_CFG 0x90
68
69#define RALINK_PCIEPHY_P0_CTL_OFFSET 0x7498
70#define RALINK_PCIE0_CLK_EN (1 << 26)
71
72#define BUSY 0x80000000
73#define WAITRETRY_MAX 10
74#define WRITE_MODE (1UL << 23)
75#define DATA_SHIFT 0
76#define ADDR_SHIFT 8
77
78
79static void __iomem *bridge_base;
80static void __iomem *pcie_base;
81
82static struct reset_control *rstpcie0;
83
84static inline void bridge_w32(u32 val, unsigned reg)
85{
86 iowrite32(val, bridge_base + reg);
87}
88
89static inline u32 bridge_r32(unsigned reg)
90{
91 return ioread32(bridge_base + reg);
92}
93
94static inline void pcie_w32(u32 val, unsigned reg)
95{
96 iowrite32(val, pcie_base + reg);
97}
98
99static inline u32 pcie_r32(unsigned reg)
100{
101 return ioread32(pcie_base + reg);
102}
103
104static inline void pcie_m32(u32 clr, u32 set, unsigned reg)
105{
106 u32 val = pcie_r32(reg);
107
108 val &= ~clr;
109 val |= set;
110 pcie_w32(val, reg);
111}
112
113static int wait_pciephy_busy(void)
114{
115 unsigned long reg_value = 0x0, retry = 0;
116
117 while (1) {
118 reg_value = pcie_r32(PCIEPHY0_CFG);
119
120 if (reg_value & BUSY)
121 mdelay(100);
122 else
123 break;
124 if (retry++ > WAITRETRY_MAX) {
125 printk(KERN_WARN "PCIE-PHY retry failed.\n");
126 return -1;
127 }
128 }
129 return 0;
130}
131
132static void pcie_phy(unsigned long addr, unsigned long val)
133{
134 wait_pciephy_busy();
135 pcie_w32(WRITE_MODE | (val << DATA_SHIFT) | (addr << ADDR_SHIFT),
136 PCIEPHY0_CFG);
137 mdelay(1);
138 wait_pciephy_busy();
139}
140
141static int pci_config_read(struct pci_bus *bus, unsigned int devfn, int where,
142 int size, u32 *val)
143{
144 unsigned int slot = PCI_SLOT(devfn);
145 u8 func = PCI_FUNC(devfn);
146 u32 address;
147 u32 data;
148 u32 num = 0;
149
150 if (bus)
151 num = bus->number;
152
153 address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
154 (func << 8) | (where & 0xfc) | 0x80000000;
155 bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
156 data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
157
158 switch (size) {
159 case 1:
160 *val = (data >> ((where & 3) << 3)) & 0xff;
161 break;
162 case 2:
163 *val = (data >> ((where & 3) << 3)) & 0xffff;
164 break;
165 case 4:
166 *val = data;
167 break;
168 }
169
170 return PCIBIOS_SUCCESSFUL;
171}
172
173static int pci_config_write(struct pci_bus *bus, unsigned int devfn, int where,
174 int size, u32 val)
175{
176 unsigned int slot = PCI_SLOT(devfn);
177 u8 func = PCI_FUNC(devfn);
178 u32 address;
179 u32 data;
180 u32 num = 0;
181
182 if (bus)
183 num = bus->number;
184
185 address = (((where & 0xF00) >> 8) << 24) | (num << 16) | (slot << 11) |
186 (func << 8) | (where & 0xfc) | 0x80000000;
187 bridge_w32(address, RALINK_PCI_CONFIG_ADDR);
188 data = bridge_r32(RALINK_PCI_CONFIG_DATA_VIRT_REG);
189
190 switch (size) {
191 case 1:
192 data = (data & ~(0xff << ((where & 3) << 3))) |
193 (val << ((where & 3) << 3));
194 break;
195 case 2:
196 data = (data & ~(0xffff << ((where & 3) << 3))) |
197 (val << ((where & 3) << 3));
198 break;
199 case 4:
200 data = val;
201 break;
202 }
203
204 bridge_w32(data, RALINK_PCI_CONFIG_DATA_VIRT_REG);
205
206 return PCIBIOS_SUCCESSFUL;
207}
208
209struct pci_ops mt7620_pci_ops = {
210 .read = pci_config_read,
211 .write = pci_config_write,
212};
213
214static struct resource mt7620_res_pci_mem1;
215static struct resource mt7620_res_pci_io1;
216struct pci_controller mt7620_controller = {
217 .pci_ops = &mt7620_pci_ops,
218 .mem_resource = &mt7620_res_pci_mem1,
219 .mem_offset = 0x00000000UL,
220 .io_resource = &mt7620_res_pci_io1,
221 .io_offset = 0x00000000UL,
222 .io_map_base = 0xa0000000,
223};
224
225static int mt7620_pci_hw_init(struct platform_device *pdev)
226{
227
228 pcie_phy(0x0, 0x80);
229 pcie_phy(0x1, 0x04);
230
231
232 pcie_phy(0x68, 0xB4);
233
234
235 pcie_m32(0, PCIRST, RALINK_PCI_PCICFG_ADDR);
236 reset_control_assert(rstpcie0);
237
238
239 rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
240 rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
241
242
243 reset_control_deassert(rstpcie0);
244 rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
245 mdelay(100);
246
247 if (!(rt_sysc_r32(PPLL_CFG1) & PDRV_SW_SET)) {
248 dev_err(&pdev->dev, "MT7620 PPLL unlock\n");
249 reset_control_assert(rstpcie0);
250 rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
251 return -1;
252 }
253
254
255 rt_sysc_m32(LC_CKDRVHZ | LC_CKDRVOHZ, LC_CKDRVPD | PDRV_SW_SET,
256 PPLL_DRV);
257
258 return 0;
259}
260
261static int mt7628_pci_hw_init(struct platform_device *pdev)
262{
263 u32 val = 0;
264
265
266 rt_sysc_m32(BIT(16), 0, RALINK_GPIOMODE);
267 reset_control_deassert(rstpcie0);
268
269
270 rt_sysc_m32(0, RALINK_PCIE0_CLK_EN, RALINK_CLKCFG1);
271 mdelay(100);
272
273
274 pcie_m32(~0xff, 0x5, RALINK_PCIEPHY_P0_CTL_OFFSET);
275
276 pci_config_read(NULL, 0, 0x70c, 4, &val);
277 val &= ~(0xff) << 8;
278 val |= 0x50 << 8;
279 pci_config_write(NULL, 0, 0x70c, 4, val);
280
281 pci_config_read(NULL, 0, 0x70c, 4, &val);
282 dev_err(&pdev->dev, "Port 0 N_FTS = %x\n", (unsigned int) val);
283
284 return 0;
285}
286
287static int mt7620_pci_probe(struct platform_device *pdev)
288{
289 struct resource *bridge_res = platform_get_resource(pdev,
290 IORESOURCE_MEM, 0);
291 struct resource *pcie_res = platform_get_resource(pdev,
292 IORESOURCE_MEM, 1);
293 u32 val = 0;
294
295 rstpcie0 = devm_reset_control_get(&pdev->dev, "pcie0");
296 if (IS_ERR(rstpcie0))
297 return PTR_ERR(rstpcie0);
298
299 bridge_base = devm_ioremap_resource(&pdev->dev, bridge_res);
300 if (IS_ERR(bridge_base))
301 return PTR_ERR(bridge_base);
302
303 pcie_base = devm_ioremap_resource(&pdev->dev, pcie_res);
304 if (IS_ERR(pcie_base))
305 return PTR_ERR(pcie_base);
306
307 iomem_resource.start = 0;
308 iomem_resource.end = ~0;
309 ioport_resource.start = 0;
310 ioport_resource.end = ~0;
311
312
313 switch (ralink_soc) {
314 case MT762X_SOC_MT7620A:
315 if (mt7620_pci_hw_init(pdev))
316 return -1;
317 break;
318
319 case MT762X_SOC_MT7628AN:
320 if (mt7628_pci_hw_init(pdev))
321 return -1;
322 break;
323
324 default:
325 dev_err(&pdev->dev, "pcie is not supported on this hardware\n");
326 return -1;
327 }
328 mdelay(50);
329
330
331 pcie_m32(PCIRST, 0, RALINK_PCI_PCICFG_ADDR);
332 mdelay(100);
333
334
335 if ((pcie_r32(RALINK_PCI0_STATUS) & PCIE_LINK_UP_ST) == 0) {
336 reset_control_assert(rstpcie0);
337 rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
338 if (ralink_soc == MT762X_SOC_MT7620A)
339 rt_sysc_m32(LC_CKDRVPD, PDRV_SW_SET, PPLL_DRV);
340 dev_err(&pdev->dev, "PCIE0 no card, disable it(RST&CLK)\n");
341 return -1;
342 }
343
344
345 bridge_w32(0xffffffff, RALINK_PCI_MEMBASE);
346 bridge_w32(RALINK_PCI_IO_MAP_BASE, RALINK_PCI_IOBASE);
347
348 pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
349 pcie_w32(RALINK_PCI_MEMORY_BASE, RALINK_PCI0_IMBASEBAR0_ADDR);
350 pcie_w32(0x06040001, RALINK_PCI0_CLASS);
351
352
353 pcie_m32(0, PCIINT2, RALINK_PCI_PCIENA);
354
355
356 pci_config_read(NULL, 0, 4, 4, &val);
357 pci_config_write(NULL, 0, 4, 4, val | 0x7);
358
359 pci_load_of_ranges(&mt7620_controller, pdev->dev.of_node);
360 register_pci_controller(&mt7620_controller);
361
362 return 0;
363}
364
365int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
366{
367 u16 cmd;
368 u32 val;
369 int irq = 0;
370
371 if ((dev->bus->number == 0) && (slot == 0)) {
372 pcie_w32(0x7FFF0001, RALINK_PCI0_BAR0SETUP_ADDR);
373 pci_config_write(dev->bus, 0, PCI_BASE_ADDRESS_0, 4,
374 RALINK_PCI_MEMORY_BASE);
375 pci_config_read(dev->bus, 0, PCI_BASE_ADDRESS_0, 4, &val);
376 } else if ((dev->bus->number == 1) && (slot == 0x0)) {
377 irq = RALINK_INT_PCIE0;
378 } else {
379 dev_err(&dev->dev, "no irq found - bus=0x%x, slot = 0x%x\n",
380 dev->bus->number, slot);
381 return 0;
382 }
383 dev_err(&dev->dev, "card - bus=0x%x, slot = 0x%x irq=%d\n",
384 dev->bus->number, slot, irq);
385
386
387 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 0x14);
388
389
390 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xff);
391 pci_read_config_word(dev, PCI_COMMAND, &cmd);
392
393
394 cmd = cmd | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
395 pci_write_config_word(dev, PCI_COMMAND, cmd);
396 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
397
398 return irq;
399}
400
401int pcibios_plat_dev_init(struct pci_dev *dev)
402{
403 return 0;
404}
405
406static const struct of_device_id mt7620_pci_ids[] = {
407 { .compatible = "mediatek,mt7620-pci" },
408 {},
409};
410MODULE_DEVICE_TABLE(of, mt7620_pci_ids);
411
412static struct platform_driver mt7620_pci_driver = {
413 .probe = mt7620_pci_probe,
414 .driver = {
415 .name = "mt7620-pci",
416 .owner = THIS_MODULE,
417 .of_match_table = of_match_ptr(mt7620_pci_ids),
418 },
419};
420
421static int __init mt7620_pci_init(void)
422{
423 return platform_driver_register(&mt7620_pci_driver);
424}
425
426arch_initcall(mt7620_pci_init);
427
