1/* asm/dma.h: Defines for using and allocating dma channels. 2 * Written by Hennus Bergman, 1992. 3 * High DMA channel support & info by Hannu Savolainen 4 * and John Boyd, Nov. 1992. 5 * (c) Copyright 2000, Grant Grundler 6 */ 7 8#ifndef _ASM_DMA_H 9#define _ASM_DMA_H 10 11#include <asm/io.h> /* need byte IO */ 12 13#define dma_outb outb 14#define dma_inb inb 15 16/* 17** DMA_CHUNK_SIZE is used by the SCSI mid-layer to break up 18** (or rather not merge) DMAs into manageable chunks. 19** On parisc, this is more of the software/tuning constraint 20** rather than the HW. I/O MMU allocation algorithms can be 21** faster with smaller sizes (to some degree). 22*/ 23#define DMA_CHUNK_SIZE (BITS_PER_LONG*PAGE_SIZE) 24 25/* The maximum address that we can perform a DMA transfer to on this platform 26** New dynamic DMA interfaces should obsolete this.... 27*/ 28#define MAX_DMA_ADDRESS (~0UL) 29 30/* 31** We don't have DMA channels... well V-class does but the 32** Dynamic DMA Mapping interface will support them... right? :^) 33** Note: this is not relevant right now for PA-RISC, but we cannot 34** leave this as undefined because some things (e.g. sound) 35** won't compile :-( 36*/ 37#define MAX_DMA_CHANNELS 8 38#define DMA_MODE_READ 0x44 /* I/O to memory, no autoinit, increment, single mode */ 39#define DMA_MODE_WRITE 0x48 /* memory to I/O, no autoinit, increment, single mode */ 40#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ 41 42#define DMA_AUTOINIT 0x10 43 44/* 8237 DMA controllers */ 45#define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */ 46#define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */ 47 48/* DMA controller registers */ 49#define DMA1_CMD_REG 0x08 /* command register (w) */ 50#define DMA1_STAT_REG 0x08 /* status register (r) */ 51#define DMA1_REQ_REG 0x09 /* request register (w) */ 52#define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ 53#define DMA1_MODE_REG 0x0B /* mode register (w) */ 54#define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ 55#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ 56#define DMA1_RESET_REG 0x0D /* Master Clear (w) */ 57#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ 58#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ 59#define DMA1_EXT_MODE_REG (0x400 | DMA1_MODE_REG) 60 61#define DMA2_CMD_REG 0xD0 /* command register (w) */ 62#define DMA2_STAT_REG 0xD0 /* status register (r) */ 63#define DMA2_REQ_REG 0xD2 /* request register (w) */ 64#define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ 65#define DMA2_MODE_REG 0xD6 /* mode register (w) */ 66#define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ 67#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ 68#define DMA2_RESET_REG 0xDA /* Master Clear (w) */ 69#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ 70#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ 71#define DMA2_EXT_MODE_REG (0x400 | DMA2_MODE_REG) 72 73static __inline__ unsigned long claim_dma_lock(void) 74{ 75 return 0; 76} 77 78static __inline__ void release_dma_lock(unsigned long flags) 79{ 80} 81 82 83/* Get DMA residue count. After a DMA transfer, this 84 * should return zero. Reading this while a DMA transfer is 85 * still in progress will return unpredictable results. 86 * If called before the channel has been used, it may return 1. 87 * Otherwise, it returns the number of _bytes_ left to transfer. 88 * 89 * Assumes DMA flip-flop is clear. 90 */ 91static __inline__ int get_dma_residue(unsigned int dmanr) 92{ 93 unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE 94 : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; 95 96 /* using short to get 16-bit wrap around */ 97 unsigned short count; 98 99 count = 1 + dma_inb(io_port); 100 count += dma_inb(io_port) << 8; 101 102 return (dmanr<=3)? count : (count<<1); 103} 104 105/* enable/disable a specific DMA channel */ 106static __inline__ void enable_dma(unsigned int dmanr) 107{ 108#ifdef CONFIG_SUPERIO 109 if (dmanr<=3) 110 dma_outb(dmanr, DMA1_MASK_REG); 111 else 112 dma_outb(dmanr & 3, DMA2_MASK_REG); 113#endif 114} 115 116static __inline__ void disable_dma(unsigned int dmanr) 117{ 118#ifdef CONFIG_SUPERIO 119 if (dmanr<=3) 120 dma_outb(dmanr | 4, DMA1_MASK_REG); 121 else 122 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); 123#endif 124} 125 126/* reserve a DMA channel */ 127#define request_dma(dmanr, device_id) (0) 128 129/* Clear the 'DMA Pointer Flip Flop'. 130 * Write 0 for LSB/MSB, 1 for MSB/LSB access. 131 * Use this once to initialize the FF to a known state. 132 * After that, keep track of it. :-) 133 * --- In order to do that, the DMA routines below should --- 134 * --- only be used while holding the DMA lock ! --- 135 */ 136static __inline__ void clear_dma_ff(unsigned int dmanr) 137{ 138} 139 140/* set mode (above) for a specific DMA channel */ 141static __inline__ void set_dma_mode(unsigned int dmanr, char mode) 142{ 143} 144 145/* Set only the page register bits of the transfer address. 146 * This is used for successive transfers when we know the contents of 147 * the lower 16 bits of the DMA current address register, but a 64k boundary 148 * may have been crossed. 149 */ 150static __inline__ void set_dma_page(unsigned int dmanr, char pagenr) 151{ 152} 153 154 155/* Set transfer address & page bits for specific DMA channel. 156 * Assumes dma flipflop is clear. 157 */ 158static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a) 159{ 160} 161 162 163/* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for 164 * a specific DMA channel. 165 * You must ensure the parameters are valid. 166 * NOTE: from a manual: "the number of transfers is one more 167 * than the initial word count"! This is taken into account. 168 * Assumes dma flip-flop is clear. 169 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7. 170 */ 171static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) 172{ 173} 174 175 176#define free_dma(dmanr) 177 178#ifdef CONFIG_PCI 179extern int isa_dma_bridge_buggy; 180#else 181#define isa_dma_bridge_buggy (0) 182#endif 183 184#endif /* _ASM_DMA_H */ 185