LXR linux/arch/powerpc/include/asm/cputable.h

   1#ifndef __ASM_POWERPC_CPUTABLE_H
   2#define __ASM_POWERPC_CPUTABLE_H
   3
   4
   5#include <asm/asm-compat.h>
   6#include <asm/feature-fixups.h>
   7#include <uapi/asm/cputable.h>
   8
   9#ifndef __ASSEMBLY__
  10
  11/* This structure can grow, it's real size is used by head.S code
  12 * via the mkdefs mechanism.
  13 */
  14struct cpu_spec;
  15
  16typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
  17typedef void (*cpu_restore_t)(void);
  18
  19enum powerpc_oprofile_type {
  20        PPC_OPROFILE_INVALID = 0,
  21        PPC_OPROFILE_RS64 = 1,
  22        PPC_OPROFILE_POWER4 = 2,
  23        PPC_OPROFILE_G4 = 3,
  24        PPC_OPROFILE_FSL_EMB = 4,
  25        PPC_OPROFILE_CELL = 5,
  26        PPC_OPROFILE_PA6T = 6,
  27};
  28
  29enum powerpc_pmc_type {
  30        PPC_PMC_DEFAULT = 0,
  31        PPC_PMC_IBM = 1,
  32        PPC_PMC_PA6T = 2,
  33        PPC_PMC_G4 = 3,
  34};
  35
  36struct pt_regs;
  37
  38extern int machine_check_generic(struct pt_regs *regs);
  39extern int machine_check_4xx(struct pt_regs *regs);
  40extern int machine_check_440A(struct pt_regs *regs);
  41extern int machine_check_e500mc(struct pt_regs *regs);
  42extern int machine_check_e500(struct pt_regs *regs);
  43extern int machine_check_e200(struct pt_regs *regs);
  44extern int machine_check_47x(struct pt_regs *regs);
  45
  46extern void cpu_down_flush_e500v2(void);
  47extern void cpu_down_flush_e500mc(void);
  48extern void cpu_down_flush_e5500(void);
  49extern void cpu_down_flush_e6500(void);
  50
  51/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
  52struct cpu_spec {
  53        /* CPU is matched via (PVR & pvr_mask) == pvr_value */
  54        unsigned int    pvr_mask;
  55        unsigned int    pvr_value;
  56
  57        char            *cpu_name;
  58        unsigned long   cpu_features;           /* Kernel features */
  59        unsigned int    cpu_user_features;      /* Userland features */
  60        unsigned int    cpu_user_features2;     /* Userland features v2 */
  61        unsigned int    mmu_features;           /* MMU features */
  62
  63        /* cache line sizes */
  64        unsigned int    icache_bsize;
  65        unsigned int    dcache_bsize;
  66
  67        /* flush caches inside the current cpu */
  68        void (*cpu_down_flush)(void);
  69
  70        /* number of performance monitor counters */
  71        unsigned int    num_pmcs;
  72        enum powerpc_pmc_type pmc_type;
  73
  74        /* this is called to initialize various CPU bits like L1 cache,
  75         * BHT, SPD, etc... from head.S before branching to identify_machine
  76         */
  77        cpu_setup_t     cpu_setup;
  78        /* Used to restore cpu setup on secondary processors and at resume */
  79        cpu_restore_t   cpu_restore;
  80
  81        /* Used by oprofile userspace to select the right counters */
  82        char            *oprofile_cpu_type;
  83
  84        /* Processor specific oprofile operations */
  85        enum powerpc_oprofile_type oprofile_type;
  86
  87        /* Bit locations inside the mmcra change */
  88        unsigned long   oprofile_mmcra_sihv;
  89        unsigned long   oprofile_mmcra_sipr;
  90
  91        /* Bits to clear during an oprofile exception */
  92        unsigned long   oprofile_mmcra_clear;
  93
  94        /* Name of processor class, for the ELF AT_PLATFORM entry */
  95        char            *platform;
  96
  97        /* Processor specific machine check handling. Return negative
  98         * if the error is fatal, 1 if it was fully recovered and 0 to
  99         * pass up (not CPU originated) */
 100        int             (*machine_check)(struct pt_regs *regs);
 101
 102        /*
 103         * Processor specific early machine check handler which is
 104         * called in real mode to handle SLB and TLB errors.
 105         */
 106        long            (*machine_check_early)(struct pt_regs *regs);
 107
 108        /*
 109         * Processor specific routine to flush tlbs.
 110         */
 111        void            (*flush_tlb)(unsigned int action);
 112
 113};
 114
 115extern struct cpu_spec          *cur_cpu_spec;
 116
 117extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
 118
 119extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
 120extern void do_feature_fixups(unsigned long value, void *fixup_start,
 121                              void *fixup_end);
 122
 123extern const char *powerpc_base_platform;
 124
 125/* TLB flush actions. Used as argument to cpu_spec.flush_tlb() hook */
 126enum {
 127        TLB_INVAL_SCOPE_GLOBAL = 0,     /* invalidate all TLBs */
 128        TLB_INVAL_SCOPE_LPID = 1,       /* invalidate TLBs for current LPID */
 129};
 130
 131#endif /* __ASSEMBLY__ */
 132
 133/* CPU kernel features */
 134
 135/* Retain the 32b definitions all use bottom half of word */
 136#define CPU_FTR_COHERENT_ICACHE         ASM_CONST(0x00000001)
 137#define CPU_FTR_L2CR                    ASM_CONST(0x00000002)
 138#define CPU_FTR_SPEC7450                ASM_CONST(0x00000004)
 139#define CPU_FTR_ALTIVEC                 ASM_CONST(0x00000008)
 140#define CPU_FTR_TAU                     ASM_CONST(0x00000010)
 141#define CPU_FTR_CAN_DOZE                ASM_CONST(0x00000020)
 142#define CPU_FTR_USE_TB                  ASM_CONST(0x00000040)
 143#define CPU_FTR_L2CSR                   ASM_CONST(0x00000080)
 144#define CPU_FTR_601                     ASM_CONST(0x00000100)
 145#define CPU_FTR_DBELL                   ASM_CONST(0x00000200)
 146#define CPU_FTR_CAN_NAP                 ASM_CONST(0x00000400)
 147#define CPU_FTR_L3CR                    ASM_CONST(0x00000800)
 148#define CPU_FTR_L3_DISABLE_NAP          ASM_CONST(0x00001000)
 149#define CPU_FTR_NAP_DISABLE_L2_PR       ASM_CONST(0x00002000)
 150#define CPU_FTR_DUAL_PLL_750FX          ASM_CONST(0x00004000)
 151#define CPU_FTR_NO_DPM                  ASM_CONST(0x00008000)
 152#define CPU_FTR_476_DD2                 ASM_CONST(0x00010000)
 153#define CPU_FTR_NEED_COHERENT           ASM_CONST(0x00020000)
 154#define CPU_FTR_NO_BTIC                 ASM_CONST(0x00040000)
 155#define CPU_FTR_DEBUG_LVL_EXC           ASM_CONST(0x00080000)
 156#define CPU_FTR_NODSISRALIGN            ASM_CONST(0x00100000)
 157#define CPU_FTR_PPC_LE                  ASM_CONST(0x00200000)
 158#define CPU_FTR_REAL_LE                 ASM_CONST(0x00400000)
 159#define CPU_FTR_FPU_UNAVAILABLE         ASM_CONST(0x00800000)
 160#define CPU_FTR_UNIFIED_ID_CACHE        ASM_CONST(0x01000000)
 161#define CPU_FTR_SPE                     ASM_CONST(0x02000000)
 162#define CPU_FTR_NEED_PAIRED_STWCX       ASM_CONST(0x04000000)
 163#define CPU_FTR_LWSYNC                  ASM_CONST(0x08000000)
 164#define CPU_FTR_NOEXECUTE               ASM_CONST(0x10000000)
 165#define CPU_FTR_INDEXED_DCR             ASM_CONST(0x20000000)
 166#define CPU_FTR_EMB_HV                  ASM_CONST(0x40000000)
 167
 168/*
 169 * Add the 64-bit processor unique features in the top half of the word;
 170 * on 32-bit, make the names available but defined to be 0.
 171 */
 172#ifdef __powerpc64__
 173#define LONG_ASM_CONST(x)               ASM_CONST(x)
 174#else
 175#define LONG_ASM_CONST(x)               0
 176#endif
 177
 178#define CPU_FTR_HVMODE                  LONG_ASM_CONST(0x0000000100000000)
 179#define CPU_FTR_ARCH_201                LONG_ASM_CONST(0x0000000200000000)
 180#define CPU_FTR_ARCH_206                LONG_ASM_CONST(0x0000000400000000)
 181#define CPU_FTR_ARCH_207S               LONG_ASM_CONST(0x0000000800000000)
 182#define CPU_FTR_ARCH_300                LONG_ASM_CONST(0x0000001000000000)
 183#define CPU_FTR_MMCRA                   LONG_ASM_CONST(0x0000002000000000)
 184#define CPU_FTR_CTRL                    LONG_ASM_CONST(0x0000004000000000)
 185#define CPU_FTR_SMT                     LONG_ASM_CONST(0x0000008000000000)
 186#define CPU_FTR_PAUSE_ZERO              LONG_ASM_CONST(0x0000010000000000)
 187#define CPU_FTR_PURR                    LONG_ASM_CONST(0x0000020000000000)
 188#define CPU_FTR_CELL_TB_BUG             LONG_ASM_CONST(0x0000040000000000)
 189#define CPU_FTR_SPURR                   LONG_ASM_CONST(0x0000080000000000)
 190#define CPU_FTR_DSCR                    LONG_ASM_CONST(0x0000100000000000)
 191#define CPU_FTR_VSX                     LONG_ASM_CONST(0x0000200000000000)
 192#define CPU_FTR_SAO                     LONG_ASM_CONST(0x0000400000000000)
 193#define CPU_FTR_CP_USE_DCBTZ            LONG_ASM_CONST(0x0000800000000000)
 194#define CPU_FTR_UNALIGNED_LD_STD        LONG_ASM_CONST(0x0001000000000000)
 195#define CPU_FTR_ASYM_SMT                LONG_ASM_CONST(0x0002000000000000)
 196#define CPU_FTR_STCX_CHECKS_ADDRESS     LONG_ASM_CONST(0x0004000000000000)
 197#define CPU_FTR_POPCNTB                 LONG_ASM_CONST(0x0008000000000000)
 198#define CPU_FTR_POPCNTD                 LONG_ASM_CONST(0x0010000000000000)
 199#define CPU_FTR_ICSWX                   LONG_ASM_CONST(0x0020000000000000)
 200#define CPU_FTR_VMX_COPY                LONG_ASM_CONST(0x0040000000000000)
 201#define CPU_FTR_TM                      LONG_ASM_CONST(0x0080000000000000)
 202#define CPU_FTR_CFAR                    LONG_ASM_CONST(0x0100000000000000)
 203#define CPU_FTR_HAS_PPR                 LONG_ASM_CONST(0x0200000000000000)
 204#define CPU_FTR_DAWR                    LONG_ASM_CONST(0x0400000000000000)
 205#define CPU_FTR_DABRX                   LONG_ASM_CONST(0x0800000000000000)
 206#define CPU_FTR_PMAO_BUG                LONG_ASM_CONST(0x1000000000000000)
 207#define CPU_FTR_SUBCORE                 LONG_ASM_CONST(0x2000000000000000)
 208
 209#ifndef __ASSEMBLY__
 210
 211#define CPU_FTR_PPCAS_ARCH_V2   (CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
 212
 213#define MMU_FTR_PPCAS_ARCH_V2   (MMU_FTR_TLBIEL | MMU_FTR_16M_PAGE)
 214
 215/* We only set the altivec features if the kernel was compiled with altivec
 216 * support
 217 */
 218#ifdef CONFIG_ALTIVEC
 219#define CPU_FTR_ALTIVEC_COMP    CPU_FTR_ALTIVEC
 220#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
 221#else
 222#define CPU_FTR_ALTIVEC_COMP    0
 223#define PPC_FEATURE_HAS_ALTIVEC_COMP    0
 224#endif
 225
 226/* We only set the VSX features if the kernel was compiled with VSX
 227 * support
 228 */
 229#ifdef CONFIG_VSX
 230#define CPU_FTR_VSX_COMP        CPU_FTR_VSX
 231#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
 232#else
 233#define CPU_FTR_VSX_COMP        0
 234#define PPC_FEATURE_HAS_VSX_COMP    0
 235#endif
 236
 237/* We only set the spe features if the kernel was compiled with spe
 238 * support
 239 */
 240#ifdef CONFIG_SPE
 241#define CPU_FTR_SPE_COMP        CPU_FTR_SPE
 242#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
 243#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
 244#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
 245#else
 246#define CPU_FTR_SPE_COMP        0
 247#define PPC_FEATURE_HAS_SPE_COMP    0
 248#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
 249#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
 250#endif
 251
 252/* We only set the TM feature if the kernel was compiled with TM supprt */
 253#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 254#define CPU_FTR_TM_COMP                 CPU_FTR_TM
 255#define PPC_FEATURE2_HTM_COMP           PPC_FEATURE2_HTM
 256#define PPC_FEATURE2_HTM_NOSC_COMP      PPC_FEATURE2_HTM_NOSC
 257#else
 258#define CPU_FTR_TM_COMP                 0
 259#define PPC_FEATURE2_HTM_COMP           0
 260#define PPC_FEATURE2_HTM_NOSC_COMP      0
 261#endif
 262
 263/* We need to mark all pages as being coherent if we're SMP or we have a
 264 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
 265 * require it for PCI "streaming/prefetch" to work properly.
 266 * This is also required by 52xx family.
 267 */
 268#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
 269        || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260) \
 270        || defined(CONFIG_PPC_MPC52xx)
 271#define CPU_FTR_COMMON                  CPU_FTR_NEED_COHERENT
 272#else
 273#define CPU_FTR_COMMON                  0
 274#endif
 275
 276/* The powersave features NAP & DOZE seems to confuse BDI when
 277   debugging. So if a BDI is used, disable theses
 278 */
 279#ifndef CONFIG_BDI_SWITCH
 280#define CPU_FTR_MAYBE_CAN_DOZE  CPU_FTR_CAN_DOZE
 281#define CPU_FTR_MAYBE_CAN_NAP   CPU_FTR_CAN_NAP
 282#else
 283#define CPU_FTR_MAYBE_CAN_DOZE  0
 284#define CPU_FTR_MAYBE_CAN_NAP   0
 285#endif
 286
 287#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \
 288        CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
 289#define CPU_FTRS_603    (CPU_FTR_COMMON | \
 290            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 291            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 292#define CPU_FTRS_604    (CPU_FTR_COMMON | \
 293            CPU_FTR_USE_TB | CPU_FTR_PPC_LE)
 294#define CPU_FTRS_740_NOTAU      (CPU_FTR_COMMON | \
 295            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 296            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 297#define CPU_FTRS_740    (CPU_FTR_COMMON | \
 298            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 299            CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
 300            CPU_FTR_PPC_LE)
 301#define CPU_FTRS_750    (CPU_FTR_COMMON | \
 302            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 303            CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \
 304            CPU_FTR_PPC_LE)
 305#define CPU_FTRS_750CL  (CPU_FTRS_750)
 306#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
 307#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
 308#define CPU_FTRS_750FX  (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX)
 309#define CPU_FTRS_750GX  (CPU_FTRS_750FX)
 310#define CPU_FTRS_7400_NOTAU     (CPU_FTR_COMMON | \
 311            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 312            CPU_FTR_ALTIVEC_COMP | \
 313            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 314#define CPU_FTRS_7400   (CPU_FTR_COMMON | \
 315            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
 316            CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \
 317            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
 318#define CPU_FTRS_7450_20        (CPU_FTR_COMMON | \
 319            CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 320            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 321            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 322#define CPU_FTRS_7450_21        (CPU_FTR_COMMON | \
 323            CPU_FTR_USE_TB | \
 324            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 325            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 326            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 327            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 328#define CPU_FTRS_7450_23        (CPU_FTR_COMMON | \
 329            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 330            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 331            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 332            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 333#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
 334            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 335            CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
 336            CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 337#define CPU_FTRS_7455_20        (CPU_FTR_COMMON | \
 338            CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
 339            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 340            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \
 341            CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
 342            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
 343#define CPU_FTRS_7455   (CPU_FTR_COMMON | \
 344            CPU_FTR_USE_TB | \
 345            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 346            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 347            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 348#define CPU_FTRS_7447_10        (CPU_FTR_COMMON | \
 349            CPU_FTR_USE_TB | \
 350            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 351            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 352            CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
 353            CPU_FTR_NEED_PAIRED_STWCX)
 354#define CPU_FTRS_7447   (CPU_FTR_COMMON | \
 355            CPU_FTR_USE_TB | \
 356            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 357            CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 358            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 359#define CPU_FTRS_7447A  (CPU_FTR_COMMON | \
 360            CPU_FTR_USE_TB | \
 361            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 362            CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 363            CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 364#define CPU_FTRS_7448   (CPU_FTR_COMMON | \
 365            CPU_FTR_USE_TB | \
 366            CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
 367            CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \
 368            CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
 369#define CPU_FTRS_82XX   (CPU_FTR_COMMON | \
 370            CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
 371#define CPU_FTRS_G2_LE  (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
 372            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP)
 373#define CPU_FTRS_E300   (CPU_FTR_MAYBE_CAN_DOZE | \
 374            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
 375            CPU_FTR_COMMON)
 376#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
 377            CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \
 378            CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
 379#define CPU_FTRS_CLASSIC32      (CPU_FTR_COMMON | CPU_FTR_USE_TB)
 380#define CPU_FTRS_8XX    (CPU_FTR_USE_TB | CPU_FTR_NOEXECUTE)
 381#define CPU_FTRS_40X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 382#define CPU_FTRS_44X    (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 383#define CPU_FTRS_440x6  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE | \
 384            CPU_FTR_INDEXED_DCR)
 385#define CPU_FTRS_47X    (CPU_FTRS_440x6)
 386#define CPU_FTRS_E200   (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
 387            CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
 388            CPU_FTR_UNIFIED_ID_CACHE | CPU_FTR_NOEXECUTE | \
 389            CPU_FTR_DEBUG_LVL_EXC)
 390#define CPU_FTRS_E500   (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 391            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \
 392            CPU_FTR_NOEXECUTE)
 393#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
 394            CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \
 395            CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE)
 396#define CPU_FTRS_E500MC (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 397            CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 398            CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
 399/*
 400 * e5500/e6500 erratum A-006958 is a timebase bug that can use the
 401 * same workaround as CPU_FTR_CELL_TB_BUG.
 402 */
 403#define CPU_FTRS_E5500  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 404            CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 405            CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 406            CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG)
 407#define CPU_FTRS_E6500  (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
 408            CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
 409            CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 410            CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \
 411            CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT)
 412#define CPU_FTRS_GENERIC_32     (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
 413
 414/* 64-bit CPUs */
 415#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 416            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 417            CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
 418            CPU_FTR_STCX_CHECKS_ADDRESS)
 419#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 420            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_201 | \
 421            CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
 422            CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS | \
 423            CPU_FTR_HVMODE | CPU_FTR_DABRX)
 424#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 425            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 426            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 427            CPU_FTR_COHERENT_ICACHE | CPU_FTR_PURR | \
 428            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_DABRX)
 429#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 430            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 431            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 432            CPU_FTR_COHERENT_ICACHE | \
 433            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 434            CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
 435            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_CFAR | \
 436            CPU_FTR_DABRX)
 437#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 438            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
 439            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 440            CPU_FTR_COHERENT_ICACHE | \
 441            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 442            CPU_FTR_DSCR | CPU_FTR_SAO  | CPU_FTR_ASYM_SMT | \
 443            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 444            CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | \
 445            CPU_FTR_VMX_COPY | CPU_FTR_HAS_PPR | CPU_FTR_DABRX)
 446#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 447            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
 448            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 449            CPU_FTR_COHERENT_ICACHE | \
 450            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 451            CPU_FTR_DSCR | CPU_FTR_SAO  | \
 452            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 453            CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
 454            CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
 455            CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_SUBCORE)
 456#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 | CPU_FTR_PMAO_BUG)
 457#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
 458#define CPU_FTRS_POWER9 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 459            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | CPU_FTR_ARCH_206 |\
 460            CPU_FTR_MMCRA | CPU_FTR_SMT | \
 461            CPU_FTR_COHERENT_ICACHE | \
 462            CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
 463            CPU_FTR_DSCR | CPU_FTR_SAO  | \
 464            CPU_FTR_STCX_CHECKS_ADDRESS | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
 465            CPU_FTR_ICSWX | CPU_FTR_CFAR | CPU_FTR_HVMODE | CPU_FTR_VMX_COPY | \
 466            CPU_FTR_DBELL | CPU_FTR_HAS_PPR | CPU_FTR_DAWR | \
 467            CPU_FTR_ARCH_207S | CPU_FTR_TM_COMP | CPU_FTR_ARCH_300)
 468#define CPU_FTRS_CELL   (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 469            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
 470            CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
 471            CPU_FTR_PAUSE_ZERO  | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \
 472            CPU_FTR_UNALIGNED_LD_STD | CPU_FTR_DABRX)
 473#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
 474            CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP | \
 475            CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_DABRX)
 476#define CPU_FTRS_COMPATIBLE     (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
 477
 478#ifdef __powerpc64__
 479#ifdef CONFIG_PPC_BOOK3E
 480#define CPU_FTRS_POSSIBLE       (CPU_FTRS_E6500 | CPU_FTRS_E5500)
 481#else
 482#define CPU_FTRS_POSSIBLE       \
 483            (CPU_FTRS_POWER4 | CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | \
 484             CPU_FTRS_POWER6 | CPU_FTRS_POWER7 | CPU_FTRS_POWER8E | \
 485             CPU_FTRS_POWER8 | CPU_FTRS_POWER8_DD1 | CPU_FTRS_CELL | \
 486             CPU_FTRS_PA6T | CPU_FTR_VSX | CPU_FTRS_POWER9)
 487#endif
 488#else
 489enum {
 490        CPU_FTRS_POSSIBLE =
 491#ifdef CONFIG_PPC_BOOK3S_32
 492            CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
 493            CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
 494            CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
 495            CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
 496            CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
 497            CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
 498            CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
 499            CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
 500            CPU_FTRS_CLASSIC32 |
 501#else
 502            CPU_FTRS_GENERIC_32 |
 503#endif
 504#ifdef CONFIG_8xx
 505            CPU_FTRS_8XX |
 506#endif
 507#ifdef CONFIG_40x
 508            CPU_FTRS_40X |
 509#endif
 510#ifdef CONFIG_44x
 511            CPU_FTRS_44X | CPU_FTRS_440x6 |
 512#endif
 513#ifdef CONFIG_PPC_47x
 514            CPU_FTRS_47X | CPU_FTR_476_DD2 |
 515#endif
 516#ifdef CONFIG_E200
 517            CPU_FTRS_E200 |
 518#endif
 519#ifdef CONFIG_E500
 520            CPU_FTRS_E500 | CPU_FTRS_E500_2 |
 521#endif
 522#ifdef CONFIG_PPC_E500MC
 523            CPU_FTRS_E500MC | CPU_FTRS_E5500 | CPU_FTRS_E6500 |
 524#endif
 525            0,
 526};
 527#endif /* __powerpc64__ */
 528
 529#ifdef __powerpc64__
 530#ifdef CONFIG_PPC_BOOK3E
 531#define CPU_FTRS_ALWAYS         (CPU_FTRS_E6500 & CPU_FTRS_E5500)
 532#else
 533#define CPU_FTRS_ALWAYS         \
 534            (CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
 535             CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
 536             CPU_FTRS_PA6T & CPU_FTRS_POWER8 & CPU_FTRS_POWER8E & \
 537             CPU_FTRS_POWER8_DD1 & ~CPU_FTR_HVMODE & CPU_FTRS_POSSIBLE & \
 538             CPU_FTRS_POWER9)
 539#endif
 540#else
 541enum {
 542        CPU_FTRS_ALWAYS =
 543#ifdef CONFIG_PPC_BOOK3S_32
 544            CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
 545            CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
 546            CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
 547            CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
 548            CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
 549            CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
 550            CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
 551            CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
 552            CPU_FTRS_CLASSIC32 &
 553#else
 554            CPU_FTRS_GENERIC_32 &
 555#endif
 556#ifdef CONFIG_8xx
 557            CPU_FTRS_8XX &
 558#endif
 559#ifdef CONFIG_40x
 560            CPU_FTRS_40X &
 561#endif
 562#ifdef CONFIG_44x
 563            CPU_FTRS_44X & CPU_FTRS_440x6 &
 564#endif
 565#ifdef CONFIG_E200
 566            CPU_FTRS_E200 &
 567#endif
 568#ifdef CONFIG_E500
 569            CPU_FTRS_E500 & CPU_FTRS_E500_2 &
 570#endif
 571#ifdef CONFIG_PPC_E500MC
 572            CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
 573#endif
 574            ~CPU_FTR_EMB_HV &   /* can be removed at runtime */
 575            CPU_FTRS_POSSIBLE,
 576};
 577#endif /* __powerpc64__ */
 578
 579static inline int cpu_has_feature(unsigned long feature)
 580{
 581        return (CPU_FTRS_ALWAYS & feature) ||
 582               (CPU_FTRS_POSSIBLE
 583                & cur_cpu_spec->cpu_features
 584                & feature);
 585}
 586
 587#define HBP_NUM 1
 588
 589#endif /* !__ASSEMBLY__ */
 590
 591#endif /* __ASM_POWERPC_CPUTABLE_H */
 592