1#ifndef _ASM_SCORE_SCOREREGS_H 2#define _ASM_SCORE_SCOREREGS_H 3 4#include <linux/linkage.h> 5 6/* TIMER register */ 7#define TIME0BASE 0x96080000 8#define P_TIMER0_CTRL (TIME0BASE + 0x00) 9#define P_TIMER0_CPP_CTRL (TIME0BASE + 0x04) 10#define P_TIMER0_PRELOAD (TIME0BASE + 0x08) 11#define P_TIMER0_CPP_REG (TIME0BASE + 0x0C) 12#define P_TIMER0_UPCNT (TIME0BASE + 0x10) 13 14/* Timer Controller Register */ 15/* bit 0 Timer enable */ 16#define TMR_DISABLE 0x0000 17#define TMR_ENABLE 0x0001 18 19/* bit 1 Interrupt enable */ 20#define TMR_IE_DISABLE 0x0000 21#define TMR_IE_ENABLE 0x0002 22 23/* bit 2 Output enable */ 24#define TMR_OE_DISABLE 0x0004 25#define TMR_OE_ENABLE 0x0000 26 27/* bit4 Up/Down counting selection */ 28#define TMR_UD_DOWN 0x0000 29#define TMR_UD_UP 0x0010 30 31/* bit5 Up/Down counting control selection */ 32#define TMR_UDS_UD 0x0000 33#define TMR_UDS_EXTUD 0x0020 34 35/* bit6 Time output mode */ 36#define TMR_OM_TOGGLE 0x0000 37#define TMR_OM_PILSE 0x0040 38 39/* bit 8..9 External input active edge selection */ 40#define TMR_ES_PE 0x0000 41#define TMR_ES_NE 0x0100 42#define TMR_ES_BOTH 0x0200 43 44/* bit 10..11 Operating mode */ 45#define TMR_M_FREE 0x0000 /* free running timer mode */ 46#define TMR_M_PERIODIC 0x0400 /* periodic timer mode */ 47#define TMR_M_FC 0x0800 /* free running counter mode */ 48#define TMR_M_PC 0x0c00 /* periodic counter mode */ 49 50#define SYSTEM_CLOCK (27*1000000/4) /* 27 MHz */ 51#endif /* _ASM_SCORE_SCOREREGS_H */ 52