1/* 2 * Copyright 2012 Tilera Corporation. All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation, version 2. 7 * 8 * This program is distributed in the hope that it will be useful, but 9 * WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or 11 * NON INFRINGEMENT. See the GNU General Public License for 12 * more details. 13 */ 14 15/* Machine-generated file; do not edit. */ 16 17 18#ifndef __ARCH_MPIPE_SHM_H__ 19#define __ARCH_MPIPE_SHM_H__ 20 21#include <arch/abi.h> 22#include <arch/mpipe_shm_def.h> 23 24#ifndef __ASSEMBLER__ 25/** 26 * MPIPE eDMA Descriptor. 27 * The eDMA descriptor is written by software and consumed by hardware. It 28 * is used to specify the location of egress packet data to be sent out of 29 * the chip via one of the packet interfaces. 30 */ 31 32__extension__ 33typedef union 34{ 35 struct 36 { 37 /* Word 0 */ 38 39#ifndef __BIG_ENDIAN__ 40 /** 41 * Generation number. Used to indicate a valid descriptor in ring. When 42 * a new descriptor is written into the ring, software must toggle this 43 * bit. The net effect is that the GEN bit being written into new 44 * descriptors toggles each time the ring tail pointer wraps. 45 */ 46 uint_reg_t gen : 1; 47 /** 48 * For devices with EDMA reorder support, this field allows the 49 * descriptor to select the egress FIFO. The associated DMA ring must 50 * have ALLOW_EFIFO_SEL enabled. 51 */ 52 uint_reg_t efifo_sel : 6; 53 /** Reserved. Must be zero. */ 54 uint_reg_t r0 : 1; 55 /** Checksum generation enabled for this transfer. */ 56 uint_reg_t csum : 1; 57 /** 58 * Nothing to be sent. Used, for example, when software has dropped a 59 * packet but still wishes to return all of the associated buffers. 60 */ 61 uint_reg_t ns : 1; 62 /** 63 * Notification interrupt will be delivered when packet has been egressed. 64 */ 65 uint_reg_t notif : 1; 66 /** 67 * Boundary indicator. When 1, this transfer includes the EOP for this 68 * command. Must be clear on all but the last descriptor for an egress 69 * packet. 70 */ 71 uint_reg_t bound : 1; 72 /** Reserved. Must be zero. */ 73 uint_reg_t r1 : 4; 74 /** 75 * Number of bytes to be sent for this descriptor. When zero, no data 76 * will be moved and the buffer descriptor will be ignored. If the 77 * buffer descriptor indicates that it is chained, the low 7 bits of the 78 * VA indicate the offset within the first buffer (e.g. 127 bytes is the 79 * maximum offset into the first buffer). If the size exceeds a single 80 * buffer, subsequent buffer descriptors will be fetched prior to 81 * processing the next eDMA descriptor in the ring. 82 */ 83 uint_reg_t xfer_size : 14; 84 /** Reserved. Must be zero. */ 85 uint_reg_t r2 : 2; 86 /** 87 * Destination of checksum relative to CSUM_START relative to the first 88 * byte moved by this descriptor. Must be zero if CSUM=0 in this 89 * descriptor. Must be less than XFER_SIZE (e.g. the first byte of the 90 * CSUM_DEST must be within the span of this descriptor). 91 */ 92 uint_reg_t csum_dest : 8; 93 /** 94 * Start byte of checksum relative to the first byte moved by this 95 * descriptor. If this is not the first descriptor for the egress 96 * packet, CSUM_START is still relative to the first byte in this 97 * descriptor. Must be zero if CSUM=0 in this descriptor. 98 */ 99 uint_reg_t csum_start : 8; 100 /** 101 * Initial value for 16-bit 1's compliment checksum if enabled via CSUM. 102 * Specified in network order. That is, bits[7:0] will be added to the 103 * byte pointed to by CSUM_START and bits[15:8] will be added to the byte 104 * pointed to by CSUM_START+1 (with appropriate 1's compliment carries). 105 * Must be zero if CSUM=0 in this descriptor. 106 */ 107 uint_reg_t csum_seed : 16; 108#else /* __BIG_ENDIAN__ */ 109 uint_reg_t csum_seed : 16; 110 uint_reg_t csum_start : 8; 111 uint_reg_t csum_dest : 8; 112 uint_reg_t r2 : 2; 113 uint_reg_t xfer_size : 14; 114 uint_reg_t r1 : 4; 115 uint_reg_t bound : 1; 116 uint_reg_t notif : 1; 117 uint_reg_t ns : 1; 118 uint_reg_t csum : 1; 119 uint_reg_t r0 : 1; 120 uint_reg_t efifo_sel : 6; 121 uint_reg_t gen : 1; 122#endif 123 124 /* Word 1 */ 125 126#ifndef __BIG_ENDIAN__ 127 /** Virtual address. Must be sign extended by consumer. */ 128 int_reg_t va : 42; 129 /** Reserved. */ 130 uint_reg_t __reserved_0 : 6; 131 /** Index of the buffer stack to which this buffer belongs. */ 132 uint_reg_t stack_idx : 5; 133 /** Reserved. */ 134 uint_reg_t __reserved_1 : 3; 135 /** 136 * Instance ID. For devices that support automatic buffer return between 137 * mPIPE instances, this field indicates the buffer owner. If the INST 138 * field does not match the mPIPE's instance number when a packet is 139 * egressed, buffers with HWB set will be returned to the other mPIPE 140 * instance. Note that not all devices support multi-mPIPE buffer 141 * return. The MPIPE_EDMA_INFO.REMOTE_BUFF_RTN_SUPPORT bit indicates 142 * whether the INST field in the buffer descriptor is populated by iDMA 143 * hardware. 144 */ 145 uint_reg_t inst : 2; 146 /** 147 * Always set to one by hardware in iDMA packet descriptors. For eDMA, 148 * indicates whether the buffer will be released to the buffer stack 149 * manager. When 0, software is responsible for releasing the buffer. 150 */ 151 uint_reg_t hwb : 1; 152 /** 153 * Encoded size of buffer. Set by the ingress hardware for iDMA packet 154 * descriptors. For eDMA descriptors, indicates the buffer size if .c 155 * indicates a chained packet. If an eDMA descriptor is not chained and 156 * the .hwb bit is not set, this field is ignored and the size is 157 * specified by the .xfer_size field. 158 * 0 = 128 bytes 159 * 1 = 256 bytes 160 * 2 = 512 bytes 161 * 3 = 1024 bytes 162 * 4 = 1664 bytes 163 * 5 = 4096 bytes 164 * 6 = 10368 bytes 165 * 7 = 16384 bytes 166 */ 167 uint_reg_t size : 3; 168 /** 169 * Chaining configuration for the buffer. Indicates that an ingress 170 * packet or egress command is chained across multiple buffers, with each 171 * buffer's size indicated by the .size field. 172 */ 173 uint_reg_t c : 2; 174#else /* __BIG_ENDIAN__ */ 175 uint_reg_t c : 2; 176 uint_reg_t size : 3; 177 uint_reg_t hwb : 1; 178 uint_reg_t inst : 2; 179 uint_reg_t __reserved_1 : 3; 180 uint_reg_t stack_idx : 5; 181 uint_reg_t __reserved_0 : 6; 182 int_reg_t va : 42; 183#endif 184 185 }; 186 187 /** Word access */ 188 uint_reg_t words[2]; 189} MPIPE_EDMA_DESC_t; 190 191/** 192 * MPIPE Packet Descriptor. 193 * The packet descriptor is filled by the mPIPE's classification, 194 * load-balancing, and buffer management services. Some fields are consumed 195 * by mPIPE hardware, and others are consumed by Tile software. 196 */ 197 198__extension__ 199typedef union 200{ 201 struct 202 { 203 /* Word 0 */ 204 205#ifndef __BIG_ENDIAN__ 206 /** 207 * Notification ring into which this packet descriptor is written. 208 * Typically written by load balancer, but can be overridden by 209 * classification program if NR is asserted. 210 */ 211 uint_reg_t notif_ring : 8; 212 /** Source channel for this packet. Written by mPIPE DMA hardware. */ 213 uint_reg_t channel : 5; 214 /** Reserved. */ 215 uint_reg_t __reserved_0 : 1; 216 /** 217 * MAC Error. 218 * Generated by the MAC interface. Asserted if there was an overrun of 219 * the MAC's receive FIFO. This condition generally only occurs if the 220 * mPIPE clock is running too slowly. 221 */ 222 uint_reg_t me : 1; 223 /** 224 * Truncation Error. 225 * Written by the iDMA hardware. Asserted if packet was truncated due to 226 * insufficient space in iPkt buffer 227 */ 228 uint_reg_t tr : 1; 229 /** 230 * Written by the iDMA hardware. Indicates the number of bytes written 231 * to Tile memory. In general, this is the actual size of the packet as 232 * received from the MAC. But if the packet is truncated due to running 233 * out of buffers or due to the iPkt buffer filling up, then the L2_SIZE 234 * will be reduced to reflect the actual number of valid bytes written to 235 * Tile memory. 236 */ 237 uint_reg_t l2_size : 14; 238 /** 239 * CRC Error. 240 * Generated by the MAC. Asserted if MAC indicated an L2 CRC error or 241 * other L2 error (bad length etc.) on the packet. 242 */ 243 uint_reg_t ce : 1; 244 /** 245 * Cut Through. 246 * Written by the iDMA hardware. Asserted if packet was not completely 247 * received before being sent to classifier. L2_Size will indicate 248 * number of bytes received so far. 249 */ 250 uint_reg_t ct : 1; 251 /** 252 * Written by the classification program. Used by the load balancer to 253 * select the ring into which this packet descriptor is written. 254 */ 255 uint_reg_t bucket_id : 13; 256 /** Reserved. */ 257 uint_reg_t __reserved_1 : 3; 258 /** 259 * Checksum. 260 * Written by classification program. When 1, the checksum engine will 261 * perform checksum based on the CSUM_SEED, CSUM_START, and CSUM_BYTES 262 * fields. The result will be placed in CSUM_VAL. 263 */ 264 uint_reg_t cs : 1; 265 /** 266 * Notification Ring Select. 267 * Written by the classification program. When 1, the NotifRingIDX is 268 * set by classification program rather than being set by load balancer. 269 */ 270 uint_reg_t nr : 1; 271 /** 272 * Written by classification program. Indicates whether packet and 273 * descriptor should both be dropped, both be delivered, or only the 274 * descriptor should be delivered. 275 */ 276 uint_reg_t dest : 2; 277 /** 278 * General Purpose Sequence Number Enable. 279 * Written by the classification program. When 1, the GP_SQN_SEL field 280 * contains the sequence number selector and the GP_SQN field will be 281 * replaced with the associated sequence number. When clear, the GP_SQN 282 * field is left intact and be used as "Custom" bytes. 283 */ 284 uint_reg_t sq : 1; 285 /** 286 * TimeStamp Enable. 287 * Enable TimeStamp insertion. When clear, timestamp field may be filled 288 * with custom data by classifier. When set, hardware inserts the 289 * timestamp when the start of packet is received from the MAC. 290 */ 291 uint_reg_t ts : 1; 292 /** 293 * Packet Sequence Number Enable. 294 * Enable PacketSQN insertion. When clear, PacketSQN field may be filled 295 * with custom data by classifier. When set, hardware inserts the packet 296 * sequence number when the packet descriptor is written to a 297 * notification ring. 298 */ 299 uint_reg_t ps : 1; 300 /** 301 * Buffer Error. 302 * Written by the iDMA hardware. Asserted if iDMA ran out of buffers 303 * while writing the packet. Software must still return any buffer 304 * descriptors whose C field indicates a valid descriptor was consumed. 305 */ 306 uint_reg_t be : 1; 307 /** 308 * Written by the classification program. The associated counter is 309 * incremented when the packet is sent. 310 */ 311 uint_reg_t ctr0 : 5; 312 /** Reserved. */ 313 uint_reg_t __reserved_2 : 3; 314#else /* __BIG_ENDIAN__ */ 315 uint_reg_t __reserved_2 : 3; 316 uint_reg_t ctr0 : 5; 317 uint_reg_t be : 1; 318 uint_reg_t ps : 1; 319 uint_reg_t ts : 1; 320 uint_reg_t sq : 1; 321 uint_reg_t dest : 2; 322 uint_reg_t nr : 1; 323 uint_reg_t cs : 1; 324 uint_reg_t __reserved_1 : 3; 325 uint_reg_t bucket_id : 13; 326 uint_reg_t ct : 1; 327 uint_reg_t ce : 1; 328 uint_reg_t l2_size : 14; 329 uint_reg_t tr : 1; 330 uint_reg_t me : 1; 331 uint_reg_t __reserved_0 : 1; 332 uint_reg_t channel : 5; 333 uint_reg_t notif_ring : 8; 334#endif 335 336 /* Word 1 */ 337 338#ifndef __BIG_ENDIAN__ 339 /** 340 * Written by the classification program. The associated counter is 341 * incremented when the packet is sent. 342 */ 343 uint_reg_t ctr1 : 5; 344 /** Reserved. */ 345 uint_reg_t __reserved_3 : 3; 346 /** 347 * Written by classification program. Indicates the start byte for 348 * checksum. Relative to 1st byte received from MAC. 349 */ 350 uint_reg_t csum_start : 8; 351 /** 352 * Checksum seed written by classification program. Overwritten with 353 * resultant checksum if CS bit is asserted. The endianness of the CSUM 354 * value bits when viewed by Tile software match the packet byte order. 355 * That is, bits[7:0] of the resulting checksum value correspond to 356 * earlier (more significant) bytes in the packet. To avoid classifier 357 * software from having to byte swap the CSUM_SEED, the iDMA checksum 358 * engine byte swaps the classifier's result before seeding the checksum 359 * calculation. Thus, the CSUM_START byte of packet data is added to 360 * bits[15:8] of the CSUM_SEED field generated by the classifier. This 361 * byte swap will be visible to Tile software if the CS bit is clear. 362 */ 363 uint_reg_t csum_seed_val : 16; 364 /** 365 * Written by the classification program. Not interpreted by mPIPE 366 * hardware. 367 */ 368 uint_reg_t custom0 : 32; 369#else /* __BIG_ENDIAN__ */ 370 uint_reg_t custom0 : 32; 371 uint_reg_t csum_seed_val : 16; 372 uint_reg_t csum_start : 8; 373 uint_reg_t __reserved_3 : 3; 374 uint_reg_t ctr1 : 5; 375#endif 376 377 /* Word 2 */ 378 379#ifndef __BIG_ENDIAN__ 380 /** 381 * Written by the classification program. Not interpreted by mPIPE 382 * hardware. 383 */ 384 uint_reg_t custom1 : 64; 385#else /* __BIG_ENDIAN__ */ 386 uint_reg_t custom1 : 64; 387#endif 388 389 /* Word 3 */ 390 391#ifndef __BIG_ENDIAN__ 392 /** 393 * Written by the classification program. Not interpreted by mPIPE 394 * hardware. 395 */ 396 uint_reg_t custom2 : 64; 397#else /* __BIG_ENDIAN__ */ 398 uint_reg_t custom2 : 64; 399#endif 400 401 /* Word 4 */ 402 403#ifndef __BIG_ENDIAN__ 404 /** 405 * Written by the classification program. Not interpreted by mPIPE 406 * hardware. 407 */ 408 uint_reg_t custom3 : 64; 409#else /* __BIG_ENDIAN__ */ 410 uint_reg_t custom3 : 64; 411#endif 412 413 /* Word 5 */ 414 415#ifndef __BIG_ENDIAN__ 416 /** 417 * Sequence number applied when packet is distributed. Classifier 418 * selects which sequence number is to be applied by writing the 13-bit 419 * SQN-selector into this field. For devices that support EXT_SQN (as 420 * indicated in IDMA_INFO.EXT_SQN_SUPPORT), the GP_SQN can be extended to 421 * 32-bits via the IDMA_CTL.EXT_SQN register. In this case the 422 * PACKET_SQN will be reduced to 32 bits. 423 */ 424 uint_reg_t gp_sqn : 16; 425 /** 426 * Written by notification hardware. The packet sequence number is 427 * incremented for each packet that wasn't dropped. 428 */ 429 uint_reg_t packet_sqn : 48; 430#else /* __BIG_ENDIAN__ */ 431 uint_reg_t packet_sqn : 48; 432 uint_reg_t gp_sqn : 16; 433#endif 434 435 /* Word 6 */ 436 437#ifndef __BIG_ENDIAN__ 438 /** 439 * Written by hardware when the start-of-packet is received by the mPIPE 440 * from the MAC. This is the nanoseconds part of the packet timestamp. 441 */ 442 uint_reg_t time_stamp_ns : 32; 443 /** 444 * Written by hardware when the start-of-packet is received by the mPIPE 445 * from the MAC. This is the seconds part of the packet timestamp. 446 */ 447 uint_reg_t time_stamp_sec : 32; 448#else /* __BIG_ENDIAN__ */ 449 uint_reg_t time_stamp_sec : 32; 450 uint_reg_t time_stamp_ns : 32; 451#endif 452 453 /* Word 7 */ 454 455#ifndef __BIG_ENDIAN__ 456 /** Virtual address. Must be sign extended by consumer. */ 457 int_reg_t va : 42; 458 /** Reserved. */ 459 uint_reg_t __reserved_4 : 6; 460 /** Index of the buffer stack to which this buffer belongs. */ 461 uint_reg_t stack_idx : 5; 462 /** Reserved. */ 463 uint_reg_t __reserved_5 : 3; 464 /** 465 * Instance ID. For devices that support automatic buffer return between 466 * mPIPE instances, this field indicates the buffer owner. If the INST 467 * field does not match the mPIPE's instance number when a packet is 468 * egressed, buffers with HWB set will be returned to the other mPIPE 469 * instance. Note that not all devices support multi-mPIPE buffer 470 * return. The MPIPE_EDMA_INFO.REMOTE_BUFF_RTN_SUPPORT bit indicates 471 * whether the INST field in the buffer descriptor is populated by iDMA 472 * hardware. 473 */ 474 uint_reg_t inst : 2; 475 /** 476 * Always set to one by hardware in iDMA packet descriptors. For eDMA, 477 * indicates whether the buffer will be released to the buffer stack 478 * manager. When 0, software is responsible for releasing the buffer. 479 */ 480 uint_reg_t hwb : 1; 481 /** 482 * Encoded size of buffer. Set by the ingress hardware for iDMA packet 483 * descriptors. For eDMA descriptors, indicates the buffer size if .c 484 * indicates a chained packet. If an eDMA descriptor is not chained and 485 * the .hwb bit is not set, this field is ignored and the size is 486 * specified by the .xfer_size field. 487 * 0 = 128 bytes 488 * 1 = 256 bytes 489 * 2 = 512 bytes 490 * 3 = 1024 bytes 491 * 4 = 1664 bytes 492 * 5 = 4096 bytes 493 * 6 = 10368 bytes 494 * 7 = 16384 bytes 495 */ 496 uint_reg_t size : 3; 497 /** 498 * Chaining configuration for the buffer. Indicates that an ingress 499 * packet or egress command is chained across multiple buffers, with each 500 * buffer's size indicated by the .size field. 501 */ 502 uint_reg_t c : 2; 503#else /* __BIG_ENDIAN__ */ 504 uint_reg_t c : 2; 505 uint_reg_t size : 3; 506 uint_reg_t hwb : 1; 507 uint_reg_t inst : 2; 508 uint_reg_t __reserved_5 : 3; 509 uint_reg_t stack_idx : 5; 510 uint_reg_t __reserved_4 : 6; 511 int_reg_t va : 42; 512#endif 513 514 }; 515 516 /** Word access */ 517 uint_reg_t words[8]; 518} MPIPE_PDESC_t; 519#endif /* !defined(__ASSEMBLER__) */ 520 521#endif /* !defined(__ARCH_MPIPE_SHM_H__) */ 522