1#include <linux/bitops.h>
2#include <linux/types.h>
3#include <linux/slab.h>
4
5#include <asm/perf_event.h>
6#include <asm/insn.h>
7
8#include "../perf_event.h"
9
10
11#define BTS_RECORD_SIZE 24
12
13#define BTS_BUFFER_SIZE (PAGE_SIZE << 4)
14#define PEBS_BUFFER_SIZE (PAGE_SIZE << 4)
15#define PEBS_FIXUP_SIZE PAGE_SIZE
16
17
18
19
20
21
22
23
24
25
26
27
28union intel_x86_pebs_dse {
29 u64 val;
30 struct {
31 unsigned int ld_dse:4;
32 unsigned int ld_stlb_miss:1;
33 unsigned int ld_locked:1;
34 unsigned int ld_reserved:26;
35 };
36 struct {
37 unsigned int st_l1d_hit:1;
38 unsigned int st_reserved1:3;
39 unsigned int st_stlb_miss:1;
40 unsigned int st_locked:1;
41 unsigned int st_reserved2:26;
42 };
43};
44
45
46
47
48
49
50#define P(a, b) PERF_MEM_S(a, b)
51#define OP_LH (P(OP, LOAD) | P(LVL, HIT))
52#define SNOOP_NONE_MISS (P(SNOOP, NONE) | P(SNOOP, MISS))
53
54
55static u64 pebs_data_source[] = {
56 P(OP, LOAD) | P(LVL, MISS) | P(LVL, L3) | P(SNOOP, NA),
57 OP_LH | P(LVL, L1) | P(SNOOP, NONE),
58 OP_LH | P(LVL, LFB) | P(SNOOP, NONE),
59 OP_LH | P(LVL, L2) | P(SNOOP, NONE),
60 OP_LH | P(LVL, L3) | P(SNOOP, NONE),
61 OP_LH | P(LVL, L3) | P(SNOOP, MISS),
62 OP_LH | P(LVL, L3) | P(SNOOP, HIT),
63 OP_LH | P(LVL, L3) | P(SNOOP, HITM),
64 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HIT),
65 OP_LH | P(LVL, REM_CCE1) | P(SNOOP, HITM),
66 OP_LH | P(LVL, LOC_RAM) | P(SNOOP, HIT),
67 OP_LH | P(LVL, REM_RAM1) | P(SNOOP, HIT),
68 OP_LH | P(LVL, LOC_RAM) | SNOOP_NONE_MISS,
69 OP_LH | P(LVL, REM_RAM1) | SNOOP_NONE_MISS,
70 OP_LH | P(LVL, IO) | P(SNOOP, NONE),
71 OP_LH | P(LVL, UNC) | P(SNOOP, NONE),
72};
73
74
75void __init intel_pmu_pebs_data_source_nhm(void)
76{
77 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | P(SNOOP, HIT);
78 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | P(SNOOP, HITM);
79 pebs_data_source[0x07] = OP_LH | P(LVL, L3) | P(SNOOP, HITM);
80}
81
82static u64 precise_store_data(u64 status)
83{
84 union intel_x86_pebs_dse dse;
85 u64 val = P(OP, STORE) | P(SNOOP, NA) | P(LVL, L1) | P(TLB, L2);
86
87 dse.val = status;
88
89
90
91
92
93
94
95
96 if (dse.st_stlb_miss)
97 val |= P(TLB, MISS);
98 else
99 val |= P(TLB, HIT);
100
101
102
103
104
105
106 if (dse.st_l1d_hit)
107 val |= P(LVL, HIT);
108 else
109 val |= P(LVL, MISS);
110
111
112
113
114 if (dse.st_locked)
115 val |= P(LOCK, LOCKED);
116
117 return val;
118}
119
120static u64 precise_datala_hsw(struct perf_event *event, u64 status)
121{
122 union perf_mem_data_src dse;
123
124 dse.val = PERF_MEM_NA;
125
126 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW)
127 dse.mem_op = PERF_MEM_OP_STORE;
128 else if (event->hw.flags & PERF_X86_EVENT_PEBS_LD_HSW)
129 dse.mem_op = PERF_MEM_OP_LOAD;
130
131
132
133
134
135
136
137
138
139 if (event->hw.flags & PERF_X86_EVENT_PEBS_ST_HSW) {
140 if (status & 1)
141 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_HIT;
142 else
143 dse.mem_lvl = PERF_MEM_LVL_L1 | PERF_MEM_LVL_MISS;
144 }
145 return dse.val;
146}
147
148static u64 load_latency_data(u64 status)
149{
150 union intel_x86_pebs_dse dse;
151 u64 val;
152 int model = boot_cpu_data.x86_model;
153 int fam = boot_cpu_data.x86;
154
155 dse.val = status;
156
157
158
159
160 val = pebs_data_source[dse.ld_dse];
161
162
163
164
165 if (fam == 0x6 && (model == 26 || model == 30
166 || model == 31 || model == 46)) {
167 val |= P(TLB, NA) | P(LOCK, NA);
168 return val;
169 }
170
171
172
173
174
175 if (dse.ld_stlb_miss)
176 val |= P(TLB, MISS) | P(TLB, L2);
177 else
178 val |= P(TLB, HIT) | P(TLB, L1) | P(TLB, L2);
179
180
181
182
183 if (dse.ld_locked)
184 val |= P(LOCK, LOCKED);
185
186 return val;
187}
188
189struct pebs_record_core {
190 u64 flags, ip;
191 u64 ax, bx, cx, dx;
192 u64 si, di, bp, sp;
193 u64 r8, r9, r10, r11;
194 u64 r12, r13, r14, r15;
195};
196
197struct pebs_record_nhm {
198 u64 flags, ip;
199 u64 ax, bx, cx, dx;
200 u64 si, di, bp, sp;
201 u64 r8, r9, r10, r11;
202 u64 r12, r13, r14, r15;
203 u64 status, dla, dse, lat;
204};
205
206
207
208
209struct pebs_record_hsw {
210 u64 flags, ip;
211 u64 ax, bx, cx, dx;
212 u64 si, di, bp, sp;
213 u64 r8, r9, r10, r11;
214 u64 r12, r13, r14, r15;
215 u64 status, dla, dse, lat;
216 u64 real_ip, tsx_tuning;
217};
218
219union hsw_tsx_tuning {
220 struct {
221 u32 cycles_last_block : 32,
222 hle_abort : 1,
223 rtm_abort : 1,
224 instruction_abort : 1,
225 non_instruction_abort : 1,
226 retry : 1,
227 data_conflict : 1,
228 capacity_writes : 1,
229 capacity_reads : 1;
230 };
231 u64 value;
232};
233
234#define PEBS_HSW_TSX_FLAGS 0xff00000000ULL
235
236
237
238struct pebs_record_skl {
239 u64 flags, ip;
240 u64 ax, bx, cx, dx;
241 u64 si, di, bp, sp;
242 u64 r8, r9, r10, r11;
243 u64 r12, r13, r14, r15;
244 u64 status, dla, dse, lat;
245 u64 real_ip, tsx_tuning;
246 u64 tsc;
247};
248
249void init_debug_store_on_cpu(int cpu)
250{
251 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
252
253 if (!ds)
254 return;
255
256 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA,
257 (u32)((u64)(unsigned long)ds),
258 (u32)((u64)(unsigned long)ds >> 32));
259}
260
261void fini_debug_store_on_cpu(int cpu)
262{
263 if (!per_cpu(cpu_hw_events, cpu).ds)
264 return;
265
266 wrmsr_on_cpu(cpu, MSR_IA32_DS_AREA, 0, 0);
267}
268
269static DEFINE_PER_CPU(void *, insn_buffer);
270
271static int alloc_pebs_buffer(int cpu)
272{
273 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
274 int node = cpu_to_node(cpu);
275 int max;
276 void *buffer, *ibuffer;
277
278 if (!x86_pmu.pebs)
279 return 0;
280
281 buffer = kzalloc_node(x86_pmu.pebs_buffer_size, GFP_KERNEL, node);
282 if (unlikely(!buffer))
283 return -ENOMEM;
284
285
286
287
288
289 if (x86_pmu.intel_cap.pebs_format < 2) {
290 ibuffer = kzalloc_node(PEBS_FIXUP_SIZE, GFP_KERNEL, node);
291 if (!ibuffer) {
292 kfree(buffer);
293 return -ENOMEM;
294 }
295 per_cpu(insn_buffer, cpu) = ibuffer;
296 }
297
298 max = x86_pmu.pebs_buffer_size / x86_pmu.pebs_record_size;
299
300 ds->pebs_buffer_base = (u64)(unsigned long)buffer;
301 ds->pebs_index = ds->pebs_buffer_base;
302 ds->pebs_absolute_maximum = ds->pebs_buffer_base +
303 max * x86_pmu.pebs_record_size;
304
305 return 0;
306}
307
308static void release_pebs_buffer(int cpu)
309{
310 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
311
312 if (!ds || !x86_pmu.pebs)
313 return;
314
315 kfree(per_cpu(insn_buffer, cpu));
316 per_cpu(insn_buffer, cpu) = NULL;
317
318 kfree((void *)(unsigned long)ds->pebs_buffer_base);
319 ds->pebs_buffer_base = 0;
320}
321
322static int alloc_bts_buffer(int cpu)
323{
324 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
325 int node = cpu_to_node(cpu);
326 int max, thresh;
327 void *buffer;
328
329 if (!x86_pmu.bts)
330 return 0;
331
332 buffer = kzalloc_node(BTS_BUFFER_SIZE, GFP_KERNEL | __GFP_NOWARN, node);
333 if (unlikely(!buffer)) {
334 WARN_ONCE(1, "%s: BTS buffer allocation failure\n", __func__);
335 return -ENOMEM;
336 }
337
338 max = BTS_BUFFER_SIZE / BTS_RECORD_SIZE;
339 thresh = max / 16;
340
341 ds->bts_buffer_base = (u64)(unsigned long)buffer;
342 ds->bts_index = ds->bts_buffer_base;
343 ds->bts_absolute_maximum = ds->bts_buffer_base +
344 max * BTS_RECORD_SIZE;
345 ds->bts_interrupt_threshold = ds->bts_absolute_maximum -
346 thresh * BTS_RECORD_SIZE;
347
348 return 0;
349}
350
351static void release_bts_buffer(int cpu)
352{
353 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
354
355 if (!ds || !x86_pmu.bts)
356 return;
357
358 kfree((void *)(unsigned long)ds->bts_buffer_base);
359 ds->bts_buffer_base = 0;
360}
361
362static int alloc_ds_buffer(int cpu)
363{
364 int node = cpu_to_node(cpu);
365 struct debug_store *ds;
366
367 ds = kzalloc_node(sizeof(*ds), GFP_KERNEL, node);
368 if (unlikely(!ds))
369 return -ENOMEM;
370
371 per_cpu(cpu_hw_events, cpu).ds = ds;
372
373 return 0;
374}
375
376static void release_ds_buffer(int cpu)
377{
378 struct debug_store *ds = per_cpu(cpu_hw_events, cpu).ds;
379
380 if (!ds)
381 return;
382
383 per_cpu(cpu_hw_events, cpu).ds = NULL;
384 kfree(ds);
385}
386
387void release_ds_buffers(void)
388{
389 int cpu;
390
391 if (!x86_pmu.bts && !x86_pmu.pebs)
392 return;
393
394 get_online_cpus();
395 for_each_online_cpu(cpu)
396 fini_debug_store_on_cpu(cpu);
397
398 for_each_possible_cpu(cpu) {
399 release_pebs_buffer(cpu);
400 release_bts_buffer(cpu);
401 release_ds_buffer(cpu);
402 }
403 put_online_cpus();
404}
405
406void reserve_ds_buffers(void)
407{
408 int bts_err = 0, pebs_err = 0;
409 int cpu;
410
411 x86_pmu.bts_active = 0;
412 x86_pmu.pebs_active = 0;
413
414 if (!x86_pmu.bts && !x86_pmu.pebs)
415 return;
416
417 if (!x86_pmu.bts)
418 bts_err = 1;
419
420 if (!x86_pmu.pebs)
421 pebs_err = 1;
422
423 get_online_cpus();
424
425 for_each_possible_cpu(cpu) {
426 if (alloc_ds_buffer(cpu)) {
427 bts_err = 1;
428 pebs_err = 1;
429 }
430
431 if (!bts_err && alloc_bts_buffer(cpu))
432 bts_err = 1;
433
434 if (!pebs_err && alloc_pebs_buffer(cpu))
435 pebs_err = 1;
436
437 if (bts_err && pebs_err)
438 break;
439 }
440
441 if (bts_err) {
442 for_each_possible_cpu(cpu)
443 release_bts_buffer(cpu);
444 }
445
446 if (pebs_err) {
447 for_each_possible_cpu(cpu)
448 release_pebs_buffer(cpu);
449 }
450
451 if (bts_err && pebs_err) {
452 for_each_possible_cpu(cpu)
453 release_ds_buffer(cpu);
454 } else {
455 if (x86_pmu.bts && !bts_err)
456 x86_pmu.bts_active = 1;
457
458 if (x86_pmu.pebs && !pebs_err)
459 x86_pmu.pebs_active = 1;
460
461 for_each_online_cpu(cpu)
462 init_debug_store_on_cpu(cpu);
463 }
464
465 put_online_cpus();
466}
467
468
469
470
471
472struct event_constraint bts_constraint =
473 EVENT_CONSTRAINT(0, 1ULL << INTEL_PMC_IDX_FIXED_BTS, 0);
474
475void intel_pmu_enable_bts(u64 config)
476{
477 unsigned long debugctlmsr;
478
479 debugctlmsr = get_debugctlmsr();
480
481 debugctlmsr |= DEBUGCTLMSR_TR;
482 debugctlmsr |= DEBUGCTLMSR_BTS;
483 if (config & ARCH_PERFMON_EVENTSEL_INT)
484 debugctlmsr |= DEBUGCTLMSR_BTINT;
485
486 if (!(config & ARCH_PERFMON_EVENTSEL_OS))
487 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_OS;
488
489 if (!(config & ARCH_PERFMON_EVENTSEL_USR))
490 debugctlmsr |= DEBUGCTLMSR_BTS_OFF_USR;
491
492 update_debugctlmsr(debugctlmsr);
493}
494
495void intel_pmu_disable_bts(void)
496{
497 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
498 unsigned long debugctlmsr;
499
500 if (!cpuc->ds)
501 return;
502
503 debugctlmsr = get_debugctlmsr();
504
505 debugctlmsr &=
506 ~(DEBUGCTLMSR_TR | DEBUGCTLMSR_BTS | DEBUGCTLMSR_BTINT |
507 DEBUGCTLMSR_BTS_OFF_OS | DEBUGCTLMSR_BTS_OFF_USR);
508
509 update_debugctlmsr(debugctlmsr);
510}
511
512int intel_pmu_drain_bts_buffer(void)
513{
514 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
515 struct debug_store *ds = cpuc->ds;
516 struct bts_record {
517 u64 from;
518 u64 to;
519 u64 flags;
520 };
521 struct perf_event *event = cpuc->events[INTEL_PMC_IDX_FIXED_BTS];
522 struct bts_record *at, *base, *top;
523 struct perf_output_handle handle;
524 struct perf_event_header header;
525 struct perf_sample_data data;
526 unsigned long skip = 0;
527 struct pt_regs regs;
528
529 if (!event)
530 return 0;
531
532 if (!x86_pmu.bts_active)
533 return 0;
534
535 base = (struct bts_record *)(unsigned long)ds->bts_buffer_base;
536 top = (struct bts_record *)(unsigned long)ds->bts_index;
537
538 if (top <= base)
539 return 0;
540
541 memset(®s, 0, sizeof(regs));
542
543 ds->bts_index = ds->bts_buffer_base;
544
545 perf_sample_data_init(&data, 0, event->hw.last_period);
546
547
548
549
550
551
552
553
554
555
556
557 for (at = base; at < top; at++) {
558
559
560
561
562
563 if (event->attr.exclude_kernel &&
564 (kernel_ip(at->from) || kernel_ip(at->to)))
565 skip++;
566 }
567
568
569
570
571
572
573 rcu_read_lock();
574 perf_prepare_sample(&header, &data, event, ®s);
575
576 if (perf_output_begin(&handle, event, header.size *
577 (top - base - skip)))
578 goto unlock;
579
580 for (at = base; at < top; at++) {
581
582 if (event->attr.exclude_kernel &&
583 (kernel_ip(at->from) || kernel_ip(at->to)))
584 continue;
585
586 data.ip = at->from;
587 data.addr = at->to;
588
589 perf_output_sample(&handle, &header, &data, event);
590 }
591
592 perf_output_end(&handle);
593
594
595 event->hw.interrupts++;
596 event->pending_kill = POLL_IN;
597unlock:
598 rcu_read_unlock();
599 return 1;
600}
601
602static inline void intel_pmu_drain_pebs_buffer(void)
603{
604 struct pt_regs regs;
605
606 x86_pmu.drain_pebs(®s);
607}
608
609void intel_pmu_pebs_sched_task(struct perf_event_context *ctx, bool sched_in)
610{
611 if (!sched_in)
612 intel_pmu_drain_pebs_buffer();
613}
614
615
616
617
618struct event_constraint intel_core2_pebs_event_constraints[] = {
619 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1),
620 INTEL_FLAGS_UEVENT_CONSTRAINT(0xfec1, 0x1),
621 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1),
622 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1fc7, 0x1),
623 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),
624
625 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
626 EVENT_CONSTRAINT_END
627};
628
629struct event_constraint intel_atom_pebs_event_constraints[] = {
630 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c0, 0x1),
631 INTEL_FLAGS_UEVENT_CONSTRAINT(0x00c5, 0x1),
632 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0x1),
633
634 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x01),
635
636 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
637 EVENT_CONSTRAINT_END
638};
639
640struct event_constraint intel_slm_pebs_event_constraints[] = {
641
642 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x1),
643
644 INTEL_ALL_EVENT_CONSTRAINT(0, 0x1),
645 EVENT_CONSTRAINT_END
646};
647
648struct event_constraint intel_nehalem_pebs_event_constraints[] = {
649 INTEL_PLD_CONSTRAINT(0x100b, 0xf),
650 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),
651 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf),
652 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),
653 INTEL_EVENT_CONSTRAINT(0xc2, 0xf),
654 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),
655 INTEL_FLAGS_UEVENT_CONSTRAINT(0x02c5, 0xf),
656 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),
657 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf),
658 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),
659 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),
660
661 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
662 EVENT_CONSTRAINT_END
663};
664
665struct event_constraint intel_westmere_pebs_event_constraints[] = {
666 INTEL_PLD_CONSTRAINT(0x100b, 0xf),
667 INTEL_FLAGS_EVENT_CONSTRAINT(0x0f, 0xf),
668 INTEL_FLAGS_UEVENT_CONSTRAINT(0x010c, 0xf),
669 INTEL_FLAGS_EVENT_CONSTRAINT(0xc0, 0xf),
670 INTEL_EVENT_CONSTRAINT(0xc2, 0xf),
671 INTEL_FLAGS_EVENT_CONSTRAINT(0xc4, 0xf),
672 INTEL_FLAGS_EVENT_CONSTRAINT(0xc5, 0xf),
673 INTEL_FLAGS_EVENT_CONSTRAINT(0xc7, 0xf),
674 INTEL_FLAGS_UEVENT_CONSTRAINT(0x20c8, 0xf),
675 INTEL_FLAGS_EVENT_CONSTRAINT(0xcb, 0xf),
676 INTEL_FLAGS_EVENT_CONSTRAINT(0xf7, 0xf),
677
678 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
679 EVENT_CONSTRAINT_END
680};
681
682struct event_constraint intel_snb_pebs_event_constraints[] = {
683 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2),
684 INTEL_PLD_CONSTRAINT(0x01cd, 0x8),
685 INTEL_PST_CONSTRAINT(0x02cd, 0x8),
686
687 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
688 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),
689 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),
690 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),
691 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),
692
693 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
694 EVENT_CONSTRAINT_END
695};
696
697struct event_constraint intel_ivb_pebs_event_constraints[] = {
698 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2),
699 INTEL_PLD_CONSTRAINT(0x01cd, 0x8),
700 INTEL_PST_CONSTRAINT(0x02cd, 0x8),
701
702 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
703
704 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
705 INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf),
706 INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf),
707 INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf),
708 INTEL_EXCLEVT_CONSTRAINT(0xd3, 0xf),
709
710 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
711 EVENT_CONSTRAINT_END
712};
713
714struct event_constraint intel_hsw_pebs_event_constraints[] = {
715 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2),
716 INTEL_PLD_CONSTRAINT(0x01cd, 0xf),
717
718 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
719
720 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
721 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf),
722 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x11d0, 0xf),
723 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x21d0, 0xf),
724 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x41d0, 0xf),
725 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XLD(0x81d0, 0xf),
726 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x12d0, 0xf),
727 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x42d0, 0xf),
728 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_XST(0x82d0, 0xf),
729 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd1, 0xf),
730 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd2, 0xf),
731 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_XLD(0xd3, 0xf),
732
733 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
734 EVENT_CONSTRAINT_END
735};
736
737struct event_constraint intel_bdw_pebs_event_constraints[] = {
738 INTEL_FLAGS_UEVENT_CONSTRAINT(0x01c0, 0x2),
739 INTEL_PLD_CONSTRAINT(0x01cd, 0xf),
740
741 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c2, 0xf),
742
743 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
744 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_NA(0x01c2, 0xf),
745 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf),
746 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf),
747 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf),
748 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf),
749 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf),
750 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf),
751 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf),
752 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),
753 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),
754 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),
755
756 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
757 EVENT_CONSTRAINT_END
758};
759
760
761struct event_constraint intel_skl_pebs_event_constraints[] = {
762 INTEL_FLAGS_UEVENT_CONSTRAINT(0x1c0, 0x2),
763
764 INTEL_FLAGS_EVENT_CONSTRAINT(0x108001c0, 0x2),
765
766 INTEL_FLAGS_EVENT_CONSTRAINT(0x108000c0, 0x0f),
767 INTEL_PLD_CONSTRAINT(0x1cd, 0xf),
768 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x11d0, 0xf),
769 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x12d0, 0xf),
770 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x21d0, 0xf),
771 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x22d0, 0xf),
772 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x41d0, 0xf),
773 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x42d0, 0xf),
774 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_LD(0x81d0, 0xf),
775 INTEL_FLAGS_UEVENT_CONSTRAINT_DATALA_ST(0x82d0, 0xf),
776 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd1, 0xf),
777 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd2, 0xf),
778 INTEL_FLAGS_EVENT_CONSTRAINT_DATALA_LD(0xd3, 0xf),
779
780 INTEL_ALL_EVENT_CONSTRAINT(0, 0xf),
781 EVENT_CONSTRAINT_END
782};
783
784struct event_constraint *intel_pebs_constraints(struct perf_event *event)
785{
786 struct event_constraint *c;
787
788 if (!event->attr.precise_ip)
789 return NULL;
790
791 if (x86_pmu.pebs_constraints) {
792 for_each_event_constraint(c, x86_pmu.pebs_constraints) {
793 if ((event->hw.config & c->cmask) == c->code) {
794 event->hw.flags |= c->flags;
795 return c;
796 }
797 }
798 }
799
800 return &emptyconstraint;
801}
802
803static inline bool pebs_is_enabled(struct cpu_hw_events *cpuc)
804{
805 return (cpuc->pebs_enabled & ((1ULL << MAX_PEBS_EVENTS) - 1));
806}
807
808void intel_pmu_pebs_enable(struct perf_event *event)
809{
810 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
811 struct hw_perf_event *hwc = &event->hw;
812 struct debug_store *ds = cpuc->ds;
813 bool first_pebs;
814 u64 threshold;
815
816 hwc->config &= ~ARCH_PERFMON_EVENTSEL_INT;
817
818 first_pebs = !pebs_is_enabled(cpuc);
819 cpuc->pebs_enabled |= 1ULL << hwc->idx;
820
821 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
822 cpuc->pebs_enabled |= 1ULL << (hwc->idx + 32);
823 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
824 cpuc->pebs_enabled |= 1ULL << 63;
825
826
827
828
829
830 if (hwc->flags & PERF_X86_EVENT_FREERUNNING) {
831 threshold = ds->pebs_absolute_maximum -
832 x86_pmu.max_pebs_events * x86_pmu.pebs_record_size;
833
834 if (first_pebs)
835 perf_sched_cb_inc(event->ctx->pmu);
836 } else {
837 threshold = ds->pebs_buffer_base + x86_pmu.pebs_record_size;
838
839
840
841
842
843 if (!first_pebs &&
844 (ds->pebs_interrupt_threshold > threshold))
845 perf_sched_cb_dec(event->ctx->pmu);
846 }
847
848
849 if (hwc->flags & PERF_X86_EVENT_AUTO_RELOAD) {
850 ds->pebs_event_reset[hwc->idx] =
851 (u64)(-hwc->sample_period) & x86_pmu.cntval_mask;
852 }
853
854 if (first_pebs || ds->pebs_interrupt_threshold > threshold)
855 ds->pebs_interrupt_threshold = threshold;
856}
857
858void intel_pmu_pebs_disable(struct perf_event *event)
859{
860 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
861 struct hw_perf_event *hwc = &event->hw;
862 struct debug_store *ds = cpuc->ds;
863 bool large_pebs = ds->pebs_interrupt_threshold >
864 ds->pebs_buffer_base + x86_pmu.pebs_record_size;
865
866 if (large_pebs)
867 intel_pmu_drain_pebs_buffer();
868
869 cpuc->pebs_enabled &= ~(1ULL << hwc->idx);
870
871 if (event->hw.flags & PERF_X86_EVENT_PEBS_LDLAT)
872 cpuc->pebs_enabled &= ~(1ULL << (hwc->idx + 32));
873 else if (event->hw.flags & PERF_X86_EVENT_PEBS_ST)
874 cpuc->pebs_enabled &= ~(1ULL << 63);
875
876 if (large_pebs && !pebs_is_enabled(cpuc))
877 perf_sched_cb_dec(event->ctx->pmu);
878
879 if (cpuc->enabled)
880 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
881
882 hwc->config |= ARCH_PERFMON_EVENTSEL_INT;
883}
884
885void intel_pmu_pebs_enable_all(void)
886{
887 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
888
889 if (cpuc->pebs_enabled)
890 wrmsrl(MSR_IA32_PEBS_ENABLE, cpuc->pebs_enabled);
891}
892
893void intel_pmu_pebs_disable_all(void)
894{
895 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
896
897 if (cpuc->pebs_enabled)
898 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
899}
900
901static int intel_pmu_pebs_fixup_ip(struct pt_regs *regs)
902{
903 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
904 unsigned long from = cpuc->lbr_entries[0].from;
905 unsigned long old_to, to = cpuc->lbr_entries[0].to;
906 unsigned long ip = regs->ip;
907 int is_64bit = 0;
908 void *kaddr;
909 int size;
910
911
912
913
914 if (!x86_pmu.intel_cap.pebs_trap)
915 return 1;
916
917
918
919
920 if (!cpuc->lbr_stack.nr || !from || !to)
921 return 0;
922
923
924
925
926 if (kernel_ip(ip) != kernel_ip(to))
927 return 0;
928
929
930
931
932
933 if ((ip - to) > PEBS_FIXUP_SIZE)
934 return 0;
935
936
937
938
939 if (ip == to) {
940 set_linear_ip(regs, from);
941 return 1;
942 }
943
944 size = ip - to;
945 if (!kernel_ip(ip)) {
946 int bytes;
947 u8 *buf = this_cpu_read(insn_buffer);
948
949
950 bytes = copy_from_user_nmi(buf, (void __user *)to, size);
951 if (bytes != 0)
952 return 0;
953
954 kaddr = buf;
955 } else {
956 kaddr = (void *)to;
957 }
958
959 do {
960 struct insn insn;
961
962 old_to = to;
963
964#ifdef CONFIG_X86_64
965 is_64bit = kernel_ip(to) || !test_thread_flag(TIF_IA32);
966#endif
967 insn_init(&insn, kaddr, size, is_64bit);
968 insn_get_length(&insn);
969
970
971
972
973
974
975 if (!insn.length)
976 break;
977
978 to += insn.length;
979 kaddr += insn.length;
980 size -= insn.length;
981 } while (to < ip);
982
983 if (to == ip) {
984 set_linear_ip(regs, old_to);
985 return 1;
986 }
987
988
989
990
991
992 return 0;
993}
994
995static inline u64 intel_hsw_weight(struct pebs_record_skl *pebs)
996{
997 if (pebs->tsx_tuning) {
998 union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };
999 return tsx.cycles_last_block;
1000 }
1001 return 0;
1002}
1003
1004static inline u64 intel_hsw_transaction(struct pebs_record_skl *pebs)
1005{
1006 u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;
1007
1008
1009 if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))
1010 txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;
1011 return txn;
1012}
1013
1014static void setup_pebs_sample_data(struct perf_event *event,
1015 struct pt_regs *iregs, void *__pebs,
1016 struct perf_sample_data *data,
1017 struct pt_regs *regs)
1018{
1019#define PERF_X86_EVENT_PEBS_HSW_PREC \
1020 (PERF_X86_EVENT_PEBS_ST_HSW | \
1021 PERF_X86_EVENT_PEBS_LD_HSW | \
1022 PERF_X86_EVENT_PEBS_NA_HSW)
1023
1024
1025
1026
1027 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1028 struct pebs_record_skl *pebs = __pebs;
1029 u64 sample_type;
1030 int fll, fst, dsrc;
1031 int fl = event->hw.flags;
1032
1033 if (pebs == NULL)
1034 return;
1035
1036 sample_type = event->attr.sample_type;
1037 dsrc = sample_type & PERF_SAMPLE_DATA_SRC;
1038
1039 fll = fl & PERF_X86_EVENT_PEBS_LDLAT;
1040 fst = fl & (PERF_X86_EVENT_PEBS_ST | PERF_X86_EVENT_PEBS_HSW_PREC);
1041
1042 perf_sample_data_init(data, 0, event->hw.last_period);
1043
1044 data->period = event->hw.last_period;
1045
1046
1047
1048
1049 if (fll && (sample_type & PERF_SAMPLE_WEIGHT))
1050 data->weight = pebs->lat;
1051
1052
1053
1054
1055 if (dsrc) {
1056 u64 val = PERF_MEM_NA;
1057 if (fll)
1058 val = load_latency_data(pebs->dse);
1059 else if (fst && (fl & PERF_X86_EVENT_PEBS_HSW_PREC))
1060 val = precise_datala_hsw(event, pebs->dse);
1061 else if (fst)
1062 val = precise_store_data(pebs->dse);
1063 data->data_src.val = val;
1064 }
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076 *regs = *iregs;
1077 regs->flags = pebs->flags;
1078 set_linear_ip(regs, pebs->ip);
1079 regs->bp = pebs->bp;
1080 regs->sp = pebs->sp;
1081
1082 if (sample_type & PERF_SAMPLE_REGS_INTR) {
1083 regs->ax = pebs->ax;
1084 regs->bx = pebs->bx;
1085 regs->cx = pebs->cx;
1086 regs->dx = pebs->dx;
1087 regs->si = pebs->si;
1088 regs->di = pebs->di;
1089 regs->bp = pebs->bp;
1090 regs->sp = pebs->sp;
1091
1092 regs->flags = pebs->flags;
1093#ifndef CONFIG_X86_32
1094 regs->r8 = pebs->r8;
1095 regs->r9 = pebs->r9;
1096 regs->r10 = pebs->r10;
1097 regs->r11 = pebs->r11;
1098 regs->r12 = pebs->r12;
1099 regs->r13 = pebs->r13;
1100 regs->r14 = pebs->r14;
1101 regs->r15 = pebs->r15;
1102#endif
1103 }
1104
1105 if (event->attr.precise_ip > 1 && x86_pmu.intel_cap.pebs_format >= 2) {
1106 regs->ip = pebs->real_ip;
1107 regs->flags |= PERF_EFLAGS_EXACT;
1108 } else if (event->attr.precise_ip > 1 && intel_pmu_pebs_fixup_ip(regs))
1109 regs->flags |= PERF_EFLAGS_EXACT;
1110 else
1111 regs->flags &= ~PERF_EFLAGS_EXACT;
1112
1113 if ((sample_type & PERF_SAMPLE_ADDR) &&
1114 x86_pmu.intel_cap.pebs_format >= 1)
1115 data->addr = pebs->dla;
1116
1117 if (x86_pmu.intel_cap.pebs_format >= 2) {
1118
1119 if ((sample_type & PERF_SAMPLE_WEIGHT) && !fll)
1120 data->weight = intel_hsw_weight(pebs);
1121
1122 if (sample_type & PERF_SAMPLE_TRANSACTION)
1123 data->txn = intel_hsw_transaction(pebs);
1124 }
1125
1126
1127
1128
1129
1130
1131
1132 if (x86_pmu.intel_cap.pebs_format >= 3 &&
1133 event->attr.use_clockid == 0)
1134 data->time = native_sched_clock_from_tsc(pebs->tsc);
1135
1136 if (has_branch_stack(event))
1137 data->br_stack = &cpuc->lbr_stack;
1138}
1139
1140static inline void *
1141get_next_pebs_record_by_bit(void *base, void *top, int bit)
1142{
1143 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1144 void *at;
1145 u64 pebs_status;
1146
1147
1148
1149
1150
1151 if (x86_pmu.intel_cap.pebs_format < 1)
1152 return base;
1153
1154 if (base == NULL)
1155 return NULL;
1156
1157 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1158 struct pebs_record_nhm *p = at;
1159
1160 if (test_bit(bit, (unsigned long *)&p->status)) {
1161
1162 if (x86_pmu.intel_cap.pebs_format >= 3)
1163 return at;
1164
1165 if (p->status == (1 << bit))
1166 return at;
1167
1168
1169 pebs_status = p->status & cpuc->pebs_enabled;
1170 pebs_status &= (1ULL << MAX_PEBS_EVENTS) - 1;
1171 if (pebs_status == (1 << bit))
1172 return at;
1173 }
1174 }
1175 return NULL;
1176}
1177
1178static void __intel_pmu_pebs_event(struct perf_event *event,
1179 struct pt_regs *iregs,
1180 void *base, void *top,
1181 int bit, int count)
1182{
1183 struct perf_sample_data data;
1184 struct pt_regs regs;
1185 void *at = get_next_pebs_record_by_bit(base, top, bit);
1186
1187 if (!intel_pmu_save_and_restart(event) &&
1188 !(event->hw.flags & PERF_X86_EVENT_AUTO_RELOAD))
1189 return;
1190
1191 while (count > 1) {
1192 setup_pebs_sample_data(event, iregs, at, &data, ®s);
1193 perf_event_output(event, &data, ®s);
1194 at += x86_pmu.pebs_record_size;
1195 at = get_next_pebs_record_by_bit(at, top, bit);
1196 count--;
1197 }
1198
1199 setup_pebs_sample_data(event, iregs, at, &data, ®s);
1200
1201
1202
1203
1204
1205 if (perf_event_overflow(event, &data, ®s)) {
1206 x86_pmu_stop(event, 0);
1207 return;
1208 }
1209
1210}
1211
1212static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
1213{
1214 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1215 struct debug_store *ds = cpuc->ds;
1216 struct perf_event *event = cpuc->events[0];
1217 struct pebs_record_core *at, *top;
1218 int n;
1219
1220 if (!x86_pmu.pebs_active)
1221 return;
1222
1223 at = (struct pebs_record_core *)(unsigned long)ds->pebs_buffer_base;
1224 top = (struct pebs_record_core *)(unsigned long)ds->pebs_index;
1225
1226
1227
1228
1229 ds->pebs_index = ds->pebs_buffer_base;
1230
1231 if (!test_bit(0, cpuc->active_mask))
1232 return;
1233
1234 WARN_ON_ONCE(!event);
1235
1236 if (!event->attr.precise_ip)
1237 return;
1238
1239 n = top - at;
1240 if (n <= 0)
1241 return;
1242
1243 __intel_pmu_pebs_event(event, iregs, at, top, 0, n);
1244}
1245
1246static void intel_pmu_drain_pebs_nhm(struct pt_regs *iregs)
1247{
1248 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1249 struct debug_store *ds = cpuc->ds;
1250 struct perf_event *event;
1251 void *base, *at, *top;
1252 short counts[MAX_PEBS_EVENTS] = {};
1253 short error[MAX_PEBS_EVENTS] = {};
1254 int bit, i;
1255
1256 if (!x86_pmu.pebs_active)
1257 return;
1258
1259 base = (struct pebs_record_nhm *)(unsigned long)ds->pebs_buffer_base;
1260 top = (struct pebs_record_nhm *)(unsigned long)ds->pebs_index;
1261
1262 ds->pebs_index = ds->pebs_buffer_base;
1263
1264 if (unlikely(base >= top))
1265 return;
1266
1267 for (at = base; at < top; at += x86_pmu.pebs_record_size) {
1268 struct pebs_record_nhm *p = at;
1269 u64 pebs_status;
1270
1271
1272 if (x86_pmu.intel_cap.pebs_format >= 3) {
1273 for_each_set_bit(bit, (unsigned long *)&p->status,
1274 MAX_PEBS_EVENTS)
1275 counts[bit]++;
1276
1277 continue;
1278 }
1279
1280 pebs_status = p->status & cpuc->pebs_enabled;
1281 pebs_status &= (1ULL << x86_pmu.max_pebs_events) - 1;
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291 if (!pebs_status && cpuc->pebs_enabled &&
1292 !(cpuc->pebs_enabled & (cpuc->pebs_enabled-1)))
1293 pebs_status = cpuc->pebs_enabled;
1294
1295 bit = find_first_bit((unsigned long *)&pebs_status,
1296 x86_pmu.max_pebs_events);
1297 if (bit >= x86_pmu.max_pebs_events)
1298 continue;
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315 if (p->status != (1ULL << bit)) {
1316 for_each_set_bit(i, (unsigned long *)&pebs_status,
1317 x86_pmu.max_pebs_events)
1318 error[i]++;
1319 continue;
1320 }
1321
1322 counts[bit]++;
1323 }
1324
1325 for (bit = 0; bit < x86_pmu.max_pebs_events; bit++) {
1326 if ((counts[bit] == 0) && (error[bit] == 0))
1327 continue;
1328
1329 event = cpuc->events[bit];
1330 WARN_ON_ONCE(!event);
1331 WARN_ON_ONCE(!event->attr.precise_ip);
1332
1333
1334 if (error[bit])
1335 perf_log_lost_samples(event, error[bit]);
1336
1337 if (counts[bit]) {
1338 __intel_pmu_pebs_event(event, iregs, base,
1339 top, bit, counts[bit]);
1340 }
1341 }
1342}
1343
1344
1345
1346
1347
1348void __init intel_ds_init(void)
1349{
1350
1351
1352
1353 if (!boot_cpu_has(X86_FEATURE_DTES64))
1354 return;
1355
1356 x86_pmu.bts = boot_cpu_has(X86_FEATURE_BTS);
1357 x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);
1358 x86_pmu.pebs_buffer_size = PEBS_BUFFER_SIZE;
1359 if (x86_pmu.pebs) {
1360 char pebs_type = x86_pmu.intel_cap.pebs_trap ? '+' : '-';
1361 int format = x86_pmu.intel_cap.pebs_format;
1362
1363 switch (format) {
1364 case 0:
1365 pr_cont("PEBS fmt0%c, ", pebs_type);
1366 x86_pmu.pebs_record_size = sizeof(struct pebs_record_core);
1367
1368
1369
1370
1371
1372
1373
1374 x86_pmu.pebs_buffer_size = PAGE_SIZE;
1375 x86_pmu.drain_pebs = intel_pmu_drain_pebs_core;
1376 break;
1377
1378 case 1:
1379 pr_cont("PEBS fmt1%c, ", pebs_type);
1380 x86_pmu.pebs_record_size = sizeof(struct pebs_record_nhm);
1381 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1382 break;
1383
1384 case 2:
1385 pr_cont("PEBS fmt2%c, ", pebs_type);
1386 x86_pmu.pebs_record_size = sizeof(struct pebs_record_hsw);
1387 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1388 break;
1389
1390 case 3:
1391 pr_cont("PEBS fmt3%c, ", pebs_type);
1392 x86_pmu.pebs_record_size =
1393 sizeof(struct pebs_record_skl);
1394 x86_pmu.drain_pebs = intel_pmu_drain_pebs_nhm;
1395 x86_pmu.free_running_flags |= PERF_SAMPLE_TIME;
1396 break;
1397
1398 default:
1399 pr_cont("no PEBS fmt%d%c, ", format, pebs_type);
1400 x86_pmu.pebs = 0;
1401 }
1402 }
1403}
1404
1405void perf_restore_debug_store(void)
1406{
1407 struct debug_store *ds = __this_cpu_read(cpu_hw_events.ds);
1408
1409 if (!x86_pmu.bts && !x86_pmu.pebs)
1410 return;
1411
1412 wrmsrl(MSR_IA32_DS_AREA, (unsigned long)ds);
1413}
1414