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21#include <linux/sched.h>
22#include <linux/pci.h>
23#include <linux/ioport.h>
24#include <linux/init.h>
25#include <linux/dmi.h>
26#include <linux/acpi.h>
27#include <linux/io.h>
28#include <linux/smp.h>
29
30#include <asm/segment.h>
31#include <asm/pci_x86.h>
32#include <asm/hw_irq.h>
33#include <asm/io_apic.h>
34#include <asm/intel-mid.h>
35
36#define PCIE_CAP_OFFSET 0x100
37
38
39#define PCI_DEVICE_ID_INTEL_MRFL_MMC 0x1190
40
41
42#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00
43#define PCI_FIXED_BAR_0_SIZE 0x04
44#define PCI_FIXED_BAR_1_SIZE 0x08
45#define PCI_FIXED_BAR_2_SIZE 0x0c
46#define PCI_FIXED_BAR_3_SIZE 0x10
47#define PCI_FIXED_BAR_4_SIZE 0x14
48#define PCI_FIXED_BAR_5_SIZE 0x1c
49
50static int pci_soc_mode;
51
52
53
54
55
56
57
58
59
60static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
61{
62 int pos;
63 u32 pcie_cap = 0, cap_data;
64
65 pos = PCIE_CAP_OFFSET;
66
67 if (!raw_pci_ext_ops)
68 return 0;
69
70 while (pos) {
71 if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
72 devfn, pos, 4, &pcie_cap))
73 return 0;
74
75 if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 ||
76 PCI_EXT_CAP_ID(pcie_cap) == 0xffff)
77 break;
78
79 if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
80 raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
81 devfn, pos + 4, 4, &cap_data);
82 if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR)
83 return pos;
84 }
85
86 pos = PCI_EXT_CAP_NEXT(pcie_cap);
87 }
88
89 return 0;
90}
91
92static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
93 int reg, int len, u32 val, int offset)
94{
95 u32 size;
96 unsigned int domain, busnum;
97 int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;
98
99 domain = pci_domain_nr(bus);
100 busnum = bus->number;
101
102 if (val == ~0 && len == 4) {
103 unsigned long decode;
104
105 raw_pci_ext_ops->read(domain, busnum, devfn,
106 offset + 8 + (bar * 4), 4, &size);
107
108
109 if (size) {
110 decode = size - 1;
111 decode |= decode >> 1;
112 decode |= decode >> 2;
113 decode |= decode >> 4;
114 decode |= decode >> 8;
115 decode |= decode >> 16;
116 decode++;
117 decode = ~(decode - 1);
118 } else {
119 decode = 0;
120 }
121
122
123
124
125
126
127
128 return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4,
129 decode);
130 }
131
132
133 return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val);
134}
135
136
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142
143
144
145
146static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
147{
148
149
150
151
152
153
154
155
156 if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
157 return false;
158 if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
159 || devfn == PCI_DEVFN(0, 0)
160 || devfn == PCI_DEVFN(3, 0)))
161 return true;
162 return false;
163}
164
165static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
166 int size, u32 *value)
167{
168 if (type1_access_ok(bus->number, devfn, where))
169 return pci_direct_conf1.read(pci_domain_nr(bus), bus->number,
170 devfn, where, size, value);
171 return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
172 devfn, where, size, value);
173}
174
175static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
176 int size, u32 value)
177{
178 int offset;
179
180
181
182
183
184 if (where == PCI_ROM_ADDRESS)
185 return 0;
186
187
188
189
190
191
192
193 offset = fixed_bar_cap(bus, devfn);
194 if (offset &&
195 (where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
196 return pci_device_update_fixed(bus, devfn, where, size, value,
197 offset);
198 }
199
200
201
202
203
204
205 if (type1_access_ok(bus->number, devfn, where))
206 return pci_direct_conf1.write(pci_domain_nr(bus), bus->number,
207 devfn, where, size, value);
208 return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn,
209 where, size, value);
210}
211
212static int intel_mid_pci_irq_enable(struct pci_dev *dev)
213{
214 struct irq_alloc_info info;
215 int polarity;
216 int ret;
217
218 if (dev->irq_managed && dev->irq > 0)
219 return 0;
220
221 switch (intel_mid_identify_cpu()) {
222 case INTEL_MID_CPU_CHIP_TANGIER:
223 polarity = IOAPIC_POL_HIGH;
224
225
226 if (dev->irq == 0) {
227
228
229
230
231
232
233 if (dev->device != PCI_DEVICE_ID_INTEL_MRFL_MMC)
234 return -EBUSY;
235 }
236 break;
237 default:
238 polarity = IOAPIC_POL_LOW;
239 break;
240 }
241
242 ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity);
243
244
245
246
247
248 ret = mp_map_gsi_to_irq(dev->irq, IOAPIC_MAP_ALLOC, &info);
249 if (ret < 0)
250 return ret;
251
252 dev->irq_managed = 1;
253
254 return 0;
255}
256
257static void intel_mid_pci_irq_disable(struct pci_dev *dev)
258{
259 if (!mp_should_keep_irq(&dev->dev) && dev->irq_managed &&
260 dev->irq > 0) {
261 mp_unmap_irq(dev->irq);
262 dev->irq_managed = 0;
263 }
264}
265
266static struct pci_ops intel_mid_pci_ops = {
267 .read = pci_read,
268 .write = pci_write,
269};
270
271
272
273
274
275
276
277int __init intel_mid_pci_init(void)
278{
279 pr_info("Intel MID platform detected, using MID PCI ops\n");
280 pci_mmcfg_late_init();
281 pcibios_enable_irq = intel_mid_pci_irq_enable;
282 pcibios_disable_irq = intel_mid_pci_irq_disable;
283 pci_root_ops = intel_mid_pci_ops;
284 pci_soc_mode = 1;
285
286 return 1;
287}
288
289
290
291
292
293static void pci_d3delay_fixup(struct pci_dev *dev)
294{
295
296
297
298
299 if (!pci_soc_mode)
300 return;
301
302
303
304
305 if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
306 return;
307 dev->d3_delay = 0;
308}
309DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
310
311static void mrst_power_off_unused_dev(struct pci_dev *dev)
312{
313 pci_set_power_state(dev, PCI_D3hot);
314}
315DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0801, mrst_power_off_unused_dev);
316DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0809, mrst_power_off_unused_dev);
317DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x080C, mrst_power_off_unused_dev);
318DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0815, mrst_power_off_unused_dev);
319
320
321
322
323static void pci_fixed_bar_fixup(struct pci_dev *dev)
324{
325 unsigned long offset;
326 u32 size;
327 int i;
328
329 if (!pci_soc_mode)
330 return;
331
332
333 if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
334 return;
335
336
337 offset = fixed_bar_cap(dev->bus, dev->devfn);
338 if (!offset || PCI_DEVFN(2, 0) == dev->devfn ||
339 PCI_DEVFN(2, 2) == dev->devfn)
340 return;
341
342 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
343 pci_read_config_dword(dev, offset + 8 + (i * 4), &size);
344 dev->resource[i].end = dev->resource[i].start + size - 1;
345 dev->resource[i].flags |= IORESOURCE_PCI_FIXED;
346 }
347}
348DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup);
349