LXR linux/drivers/clk/clk-xgene.c

   1/*
   2 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
   3 *
   4 * Copyright (c) 2013, Applied Micro Circuits Corporation
   5 * Author: Loc Ho <lho@apm.com>
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License as
   9 * published by the Free Software Foundation; either version 2 of
  10 * the License, or (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 * GNU General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU General Public License
  18 * along with this program; if not, write to the Free Software
  19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 * MA 02111-1307 USA
  21 *
  22 */
  23#include <linux/module.h>
  24#include <linux/spinlock.h>
  25#include <linux/io.h>
  26#include <linux/of.h>
  27#include <linux/clkdev.h>
  28#include <linux/clk-provider.h>
  29#include <linux/of_address.h>
  30
  31/* Register SCU_PCPPLL bit fields */
  32#define N_DIV_RD(src)                   ((src) & 0x000001ff)
  33#define SC_N_DIV_RD(src)                ((src) & 0x0000007f)
  34#define SC_OUTDIV2(src)                 (((src) & 0x00000100) >> 8)
  35
  36/* Register SCU_SOCPLL bit fields */
  37#define CLKR_RD(src)                    (((src) & 0x07000000)>>24)
  38#define CLKOD_RD(src)                   (((src) & 0x00300000)>>20)
  39#define REGSPEC_RESET_F1_MASK           0x00010000
  40#define CLKF_RD(src)                    (((src) & 0x000001ff))
  41
  42#define XGENE_CLK_DRIVER_VER            "0.1"
  43
  44static DEFINE_SPINLOCK(clk_lock);
  45
  46static inline u32 xgene_clk_read(void __iomem *csr)
  47{
  48        return readl_relaxed(csr);
  49}
  50
  51static inline void xgene_clk_write(u32 data, void __iomem *csr)
  52{
  53        writel_relaxed(data, csr);
  54}
  55
  56/* PLL Clock */
  57enum xgene_pll_type {
  58        PLL_TYPE_PCP = 0,
  59        PLL_TYPE_SOC = 1,
  60};
  61
  62struct xgene_clk_pll {
  63        struct clk_hw   hw;
  64        void __iomem    *reg;
  65        spinlock_t      *lock;
  66        u32             pll_offset;
  67        enum xgene_pll_type     type;
  68        int             version;
  69};
  70
  71#define to_xgene_clk_pll(_hw) container_of(_hw, struct xgene_clk_pll, hw)
  72
  73static int xgene_clk_pll_is_enabled(struct clk_hw *hw)
  74{
  75        struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);
  76        u32 data;
  77
  78        data = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
  79        pr_debug("%s pll %s\n", clk_hw_get_name(hw),
  80                data & REGSPEC_RESET_F1_MASK ? "disabled" : "enabled");
  81
  82        return data & REGSPEC_RESET_F1_MASK ? 0 : 1;
  83}
  84
  85static unsigned long xgene_clk_pll_recalc_rate(struct clk_hw *hw,
  86                                unsigned long parent_rate)
  87{
  88        struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw);
  89        unsigned long fref;
  90        unsigned long fvco;
  91        u32 pll;
  92        u32 nref;
  93        u32 nout;
  94        u32 nfb;
  95
  96        pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset);
  97
  98        if (pllclk->version <= 1) {
  99                if (pllclk->type == PLL_TYPE_PCP) {
 100                        /*
 101                        * PLL VCO = Reference clock * NF
 102                        * PCP PLL = PLL_VCO / 2
 103                        */
 104                        nout = 2;
 105                        fvco = parent_rate * (N_DIV_RD(pll) + 4);
 106                } else {
 107                        /*
 108                        * Fref = Reference Clock / NREF;
 109                        * Fvco = Fref * NFB;
 110                        * Fout = Fvco / NOUT;
 111                        */
 112                        nref = CLKR_RD(pll) + 1;
 113                        nout = CLKOD_RD(pll) + 1;
 114                        nfb = CLKF_RD(pll);
 115                        fref = parent_rate / nref;
 116                        fvco = fref * nfb;
 117                }
 118        } else {
 119                /*
 120                 * fvco = Reference clock * FBDIVC
 121                 * PLL freq = fvco / NOUT
 122                 */
 123                nout = SC_OUTDIV2(pll) ? 2 : 3;
 124                fvco = parent_rate * SC_N_DIV_RD(pll);
 125        }
 126        pr_debug("%s pll recalc rate %ld parent %ld version %d\n",
 127                 clk_hw_get_name(hw), fvco / nout, parent_rate,
 128                 pllclk->version);
 129
 130        return fvco / nout;
 131}
 132
 133static const struct clk_ops xgene_clk_pll_ops = {
 134        .is_enabled = xgene_clk_pll_is_enabled,
 135        .recalc_rate = xgene_clk_pll_recalc_rate,
 136};
 137
 138static struct clk *xgene_register_clk_pll(struct device *dev,
 139        const char *name, const char *parent_name,
 140        unsigned long flags, void __iomem *reg, u32 pll_offset,
 141        u32 type, spinlock_t *lock, int version)
 142{
 143        struct xgene_clk_pll *apmclk;
 144        struct clk *clk;
 145        struct clk_init_data init;
 146
 147        /* allocate the APM clock structure */
 148        apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
 149        if (!apmclk) {
 150                pr_err("%s: could not allocate APM clk\n", __func__);
 151                return ERR_PTR(-ENOMEM);
 152        }
 153
 154        init.name = name;
 155        init.ops = &xgene_clk_pll_ops;
 156        init.flags = flags;
 157        init.parent_names = parent_name ? &parent_name : NULL;
 158        init.num_parents = parent_name ? 1 : 0;
 159
 160        apmclk->version = version;
 161        apmclk->reg = reg;
 162        apmclk->lock = lock;
 163        apmclk->pll_offset = pll_offset;
 164        apmclk->type = type;
 165        apmclk->hw.init = &init;
 166
 167        /* Register the clock */
 168        clk = clk_register(dev, &apmclk->hw);
 169        if (IS_ERR(clk)) {
 170                pr_err("%s: could not register clk %s\n", __func__, name);
 171                kfree(apmclk);
 172                return NULL;
 173        }
 174        return clk;
 175}
 176
 177static int xgene_pllclk_version(struct device_node *np)
 178{
 179        if (of_device_is_compatible(np, "apm,xgene-socpll-clock"))
 180                return 1;
 181        if (of_device_is_compatible(np, "apm,xgene-pcppll-clock"))
 182                return 1;
 183        return 2;
 184}
 185
 186static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_type)
 187{
 188        const char *clk_name = np->full_name;
 189        struct clk *clk;
 190        void __iomem *reg;
 191        int version = xgene_pllclk_version(np);
 192
 193        reg = of_iomap(np, 0);
 194        if (reg == NULL) {
 195                pr_err("Unable to map CSR register for %s\n", np->full_name);
 196                return;
 197        }
 198        of_property_read_string(np, "clock-output-names", &clk_name);
 199        clk = xgene_register_clk_pll(NULL,
 200                        clk_name, of_clk_get_parent_name(np, 0),
 201                        CLK_IS_ROOT, reg, 0, pll_type, &clk_lock,
 202                        version);
 203        if (!IS_ERR(clk)) {
 204                of_clk_add_provider(np, of_clk_src_simple_get, clk);
 205                clk_register_clkdev(clk, clk_name, NULL);
 206                pr_debug("Add %s clock PLL\n", clk_name);
 207        }
 208}
 209
 210static void xgene_socpllclk_init(struct device_node *np)
 211{
 212        xgene_pllclk_init(np, PLL_TYPE_SOC);
 213}
 214
 215static void xgene_pcppllclk_init(struct device_node *np)
 216{
 217        xgene_pllclk_init(np, PLL_TYPE_PCP);
 218}
 219
 220/* IP Clock */
 221struct xgene_dev_parameters {
 222        void __iomem *csr_reg;          /* CSR for IP clock */
 223        u32 reg_clk_offset;             /* Offset to clock enable CSR */
 224        u32 reg_clk_mask;               /* Mask bit for clock enable */
 225        u32 reg_csr_offset;             /* Offset to CSR reset */
 226        u32 reg_csr_mask;               /* Mask bit for disable CSR reset */
 227        void __iomem *divider_reg;      /* CSR for divider */
 228        u32 reg_divider_offset;         /* Offset to divider register */
 229        u32 reg_divider_shift;          /* Bit shift to divider field */
 230        u32 reg_divider_width;          /* Width of the bit to divider field */
 231};
 232
 233struct xgene_clk {
 234        struct clk_hw   hw;
 235        spinlock_t      *lock;
 236        struct xgene_dev_parameters     param;
 237};
 238
 239#define to_xgene_clk(_hw) container_of(_hw, struct xgene_clk, hw)
 240
 241static int xgene_clk_enable(struct clk_hw *hw)
 242{
 243        struct xgene_clk *pclk = to_xgene_clk(hw);
 244        unsigned long flags = 0;
 245        u32 data;
 246        phys_addr_t reg;
 247
 248        if (pclk->lock)
 249                spin_lock_irqsave(pclk->lock, flags);
 250
 251        if (pclk->param.csr_reg != NULL) {
 252                pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
 253                reg = __pa(pclk->param.csr_reg);
 254                /* First enable the clock */
 255                data = xgene_clk_read(pclk->param.csr_reg +
 256                                        pclk->param.reg_clk_offset);
 257                data |= pclk->param.reg_clk_mask;
 258                xgene_clk_write(data, pclk->param.csr_reg +
 259                                        pclk->param.reg_clk_offset);
 260                pr_debug("%s clock PADDR base %pa clk offset 0x%08X mask 0x%08X value 0x%08X\n",
 261                        clk_hw_get_name(hw), &reg,
 262                        pclk->param.reg_clk_offset, pclk->param.reg_clk_mask,
 263                        data);
 264
 265                /* Second enable the CSR */
 266                data = xgene_clk_read(pclk->param.csr_reg +
 267                                        pclk->param.reg_csr_offset);
 268                data &= ~pclk->param.reg_csr_mask;
 269                xgene_clk_write(data, pclk->param.csr_reg +
 270                                        pclk->param.reg_csr_offset);
 271                pr_debug("%s CSR RESET PADDR base %pa csr offset 0x%08X mask 0x%08X value 0x%08X\n",
 272                        clk_hw_get_name(hw), &reg,
 273                        pclk->param.reg_csr_offset, pclk->param.reg_csr_mask,
 274                        data);
 275        }
 276
 277        if (pclk->lock)
 278                spin_unlock_irqrestore(pclk->lock, flags);
 279
 280        return 0;
 281}
 282
 283static void xgene_clk_disable(struct clk_hw *hw)
 284{
 285        struct xgene_clk *pclk = to_xgene_clk(hw);
 286        unsigned long flags = 0;
 287        u32 data;
 288
 289        if (pclk->lock)
 290                spin_lock_irqsave(pclk->lock, flags);
 291
 292        if (pclk->param.csr_reg != NULL) {
 293                pr_debug("%s clock disabled\n", clk_hw_get_name(hw));
 294                /* First put the CSR in reset */
 295                data = xgene_clk_read(pclk->param.csr_reg +
 296                                        pclk->param.reg_csr_offset);
 297                data |= pclk->param.reg_csr_mask;
 298                xgene_clk_write(data, pclk->param.csr_reg +
 299                                        pclk->param.reg_csr_offset);
 300
 301                /* Second disable the clock */
 302                data = xgene_clk_read(pclk->param.csr_reg +
 303                                        pclk->param.reg_clk_offset);
 304                data &= ~pclk->param.reg_clk_mask;
 305                xgene_clk_write(data, pclk->param.csr_reg +
 306                                        pclk->param.reg_clk_offset);
 307        }
 308
 309        if (pclk->lock)
 310                spin_unlock_irqrestore(pclk->lock, flags);
 311}
 312
 313static int xgene_clk_is_enabled(struct clk_hw *hw)
 314{
 315        struct xgene_clk *pclk = to_xgene_clk(hw);
 316        u32 data = 0;
 317
 318        if (pclk->param.csr_reg != NULL) {
 319                pr_debug("%s clock checking\n", clk_hw_get_name(hw));
 320                data = xgene_clk_read(pclk->param.csr_reg +
 321                                        pclk->param.reg_clk_offset);
 322                pr_debug("%s clock is %s\n", clk_hw_get_name(hw),
 323                        data & pclk->param.reg_clk_mask ? "enabled" :
 324                                                        "disabled");
 325        }
 326
 327        if (pclk->param.csr_reg == NULL)
 328                return 1;
 329        return data & pclk->param.reg_clk_mask ? 1 : 0;
 330}
 331
 332static unsigned long xgene_clk_recalc_rate(struct clk_hw *hw,
 333                                unsigned long parent_rate)
 334{
 335        struct xgene_clk *pclk = to_xgene_clk(hw);
 336        u32 data;
 337
 338        if (pclk->param.divider_reg) {
 339                data = xgene_clk_read(pclk->param.divider_reg +
 340                                        pclk->param.reg_divider_offset);
 341                data >>= pclk->param.reg_divider_shift;
 342                data &= (1 << pclk->param.reg_divider_width) - 1;
 343
 344                pr_debug("%s clock recalc rate %ld parent %ld\n",
 345                        clk_hw_get_name(hw),
 346                        parent_rate / data, parent_rate);
 347
 348                return parent_rate / data;
 349        } else {
 350                pr_debug("%s clock recalc rate %ld parent %ld\n",
 351                        clk_hw_get_name(hw), parent_rate, parent_rate);
 352                return parent_rate;
 353        }
 354}
 355
 356static int xgene_clk_set_rate(struct clk_hw *hw, unsigned long rate,
 357                                unsigned long parent_rate)
 358{
 359        struct xgene_clk *pclk = to_xgene_clk(hw);
 360        unsigned long flags = 0;
 361        u32 data;
 362        u32 divider;
 363        u32 divider_save;
 364
 365        if (pclk->lock)
 366                spin_lock_irqsave(pclk->lock, flags);
 367
 368        if (pclk->param.divider_reg) {
 369                /* Let's compute the divider */
 370                if (rate > parent_rate)
 371                        rate = parent_rate;
 372                divider_save = divider = parent_rate / rate; /* Rounded down */
 373                divider &= (1 << pclk->param.reg_divider_width) - 1;
 374                divider <<= pclk->param.reg_divider_shift;
 375
 376                /* Set new divider */
 377                data = xgene_clk_read(pclk->param.divider_reg +
 378                                pclk->param.reg_divider_offset);
 379                data &= ~(((1 << pclk->param.reg_divider_width) - 1)
 380                                << pclk->param.reg_divider_shift);
 381                data |= divider;
 382                xgene_clk_write(data, pclk->param.divider_reg +
 383                                        pclk->param.reg_divider_offset);
 384                pr_debug("%s clock set rate %ld\n", clk_hw_get_name(hw),
 385                        parent_rate / divider_save);
 386        } else {
 387                divider_save = 1;
 388        }
 389
 390        if (pclk->lock)
 391                spin_unlock_irqrestore(pclk->lock, flags);
 392
 393        return parent_rate / divider_save;
 394}
 395
 396static long xgene_clk_round_rate(struct clk_hw *hw, unsigned long rate,
 397                                unsigned long *prate)
 398{
 399        struct xgene_clk *pclk = to_xgene_clk(hw);
 400        unsigned long parent_rate = *prate;
 401        u32 divider;
 402
 403        if (pclk->param.divider_reg) {
 404                /* Let's compute the divider */
 405                if (rate > parent_rate)
 406                        rate = parent_rate;
 407                divider = parent_rate / rate;   /* Rounded down */
 408        } else {
 409                divider = 1;
 410        }
 411
 412        return parent_rate / divider;
 413}
 414
 415static const struct clk_ops xgene_clk_ops = {
 416        .enable = xgene_clk_enable,
 417        .disable = xgene_clk_disable,
 418        .is_enabled = xgene_clk_is_enabled,
 419        .recalc_rate = xgene_clk_recalc_rate,
 420        .set_rate = xgene_clk_set_rate,
 421        .round_rate = xgene_clk_round_rate,
 422};
 423
 424static struct clk *xgene_register_clk(struct device *dev,
 425                const char *name, const char *parent_name,
 426                struct xgene_dev_parameters *parameters, spinlock_t *lock)
 427{
 428        struct xgene_clk *apmclk;
 429        struct clk *clk;
 430        struct clk_init_data init;
 431        int rc;
 432
 433        /* allocate the APM clock structure */
 434        apmclk = kzalloc(sizeof(*apmclk), GFP_KERNEL);
 435        if (!apmclk) {
 436                pr_err("%s: could not allocate APM clk\n", __func__);
 437                return ERR_PTR(-ENOMEM);
 438        }
 439
 440        init.name = name;
 441        init.ops = &xgene_clk_ops;
 442        init.flags = 0;
 443        init.parent_names = parent_name ? &parent_name : NULL;
 444        init.num_parents = parent_name ? 1 : 0;
 445
 446        apmclk->lock = lock;
 447        apmclk->hw.init = &init;
 448        apmclk->param = *parameters;
 449
 450        /* Register the clock */
 451        clk = clk_register(dev, &apmclk->hw);
 452        if (IS_ERR(clk)) {
 453                pr_err("%s: could not register clk %s\n", __func__, name);
 454                kfree(apmclk);
 455                return clk;
 456        }
 457
 458        /* Register the clock for lookup */
 459        rc = clk_register_clkdev(clk, name, NULL);
 460        if (rc != 0) {
 461                pr_err("%s: could not register lookup clk %s\n",
 462                        __func__, name);
 463        }
 464        return clk;
 465}
 466
 467static void __init xgene_devclk_init(struct device_node *np)
 468{
 469        const char *clk_name = np->full_name;
 470        struct clk *clk;
 471        struct resource res;
 472        int rc;
 473        struct xgene_dev_parameters parameters;
 474        int i;
 475
 476        /* Check if the entry is disabled */
 477        if (!of_device_is_available(np))
 478                return;
 479
 480        /* Parse the DTS register for resource */
 481        parameters.csr_reg = NULL;
 482        parameters.divider_reg = NULL;
 483        for (i = 0; i < 2; i++) {
 484                void __iomem *map_res;
 485                rc = of_address_to_resource(np, i, &res);
 486                if (rc != 0) {
 487                        if (i == 0) {
 488                                pr_err("no DTS register for %s\n",
 489                                        np->full_name);
 490                                return;
 491                        }
 492                        break;
 493                }
 494                map_res = of_iomap(np, i);
 495                if (map_res == NULL) {
 496                        pr_err("Unable to map resource %d for %s\n",
 497                                i, np->full_name);
 498                        goto err;
 499                }
 500                if (strcmp(res.name, "div-reg") == 0)
 501                        parameters.divider_reg = map_res;
 502                else /* if (strcmp(res->name, "csr-reg") == 0) */
 503                        parameters.csr_reg = map_res;
 504        }
 505        if (of_property_read_u32(np, "csr-offset", &parameters.reg_csr_offset))
 506                parameters.reg_csr_offset = 0;
 507        if (of_property_read_u32(np, "csr-mask", &parameters.reg_csr_mask))
 508                parameters.reg_csr_mask = 0xF;
 509        if (of_property_read_u32(np, "enable-offset",
 510                                &parameters.reg_clk_offset))
 511                parameters.reg_clk_offset = 0x8;
 512        if (of_property_read_u32(np, "enable-mask", &parameters.reg_clk_mask))
 513                parameters.reg_clk_mask = 0xF;
 514        if (of_property_read_u32(np, "divider-offset",
 515                                &parameters.reg_divider_offset))
 516                parameters.reg_divider_offset = 0;
 517        if (of_property_read_u32(np, "divider-width",
 518                                &parameters.reg_divider_width))
 519                parameters.reg_divider_width = 0;
 520        if (of_property_read_u32(np, "divider-shift",
 521                                &parameters.reg_divider_shift))
 522                parameters.reg_divider_shift = 0;
 523        of_property_read_string(np, "clock-output-names", &clk_name);
 524
 525        clk = xgene_register_clk(NULL, clk_name,
 526                of_clk_get_parent_name(np, 0), &parameters, &clk_lock);
 527        if (IS_ERR(clk))
 528                goto err;
 529        pr_debug("Add %s clock\n", clk_name);
 530        rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
 531        if (rc != 0)
 532                pr_err("%s: could register provider clk %s\n", __func__,
 533                        np->full_name);
 534
 535        return;
 536
 537err:
 538        if (parameters.csr_reg)
 539                iounmap(parameters.csr_reg);
 540        if (parameters.divider_reg)
 541                iounmap(parameters.divider_reg);
 542}
 543
 544CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init);
 545CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init);
 546CLK_OF_DECLARE(xgene_socpll_v2_clock, "apm,xgene-socpll-v2-clock",
 547               xgene_socpllclk_init);
 548CLK_OF_DECLARE(xgene_pcppll_v2_clock, "apm,xgene-pcppll-v2-clock",
 549               xgene_pcppllclk_init);
 550CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init);
 551