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17#include <linux/io.h>
18#include <linux/delay.h>
19#include <linux/clk-provider.h>
20#include <linux/clkdev.h>
21#include <linux/of.h>
22#include <linux/of_address.h>
23#include <linux/clk/tegra.h>
24
25#include <soc/tegra/pmc.h>
26
27#include <dt-bindings/clock/tegra30-car.h>
28
29#include "clk.h"
30#include "clk-id.h"
31
32#define OSC_CTRL 0x50
33#define OSC_CTRL_OSC_FREQ_MASK (0xF<<28)
34#define OSC_CTRL_OSC_FREQ_13MHZ (0X0<<28)
35#define OSC_CTRL_OSC_FREQ_19_2MHZ (0X4<<28)
36#define OSC_CTRL_OSC_FREQ_12MHZ (0X8<<28)
37#define OSC_CTRL_OSC_FREQ_26MHZ (0XC<<28)
38#define OSC_CTRL_OSC_FREQ_16_8MHZ (0X1<<28)
39#define OSC_CTRL_OSC_FREQ_38_4MHZ (0X5<<28)
40#define OSC_CTRL_OSC_FREQ_48MHZ (0X9<<28)
41#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
42
43#define OSC_CTRL_PLL_REF_DIV_MASK (3<<26)
44#define OSC_CTRL_PLL_REF_DIV_1 (0<<26)
45#define OSC_CTRL_PLL_REF_DIV_2 (1<<26)
46#define OSC_CTRL_PLL_REF_DIV_4 (2<<26)
47
48#define OSC_FREQ_DET 0x58
49#define OSC_FREQ_DET_TRIG BIT(31)
50
51#define OSC_FREQ_DET_STATUS 0x5c
52#define OSC_FREQ_DET_BUSY BIT(31)
53#define OSC_FREQ_DET_CNT_MASK 0xffff
54
55#define CCLKG_BURST_POLICY 0x368
56#define SUPER_CCLKG_DIVIDER 0x36c
57#define CCLKLP_BURST_POLICY 0x370
58#define SUPER_CCLKLP_DIVIDER 0x374
59#define SCLK_BURST_POLICY 0x028
60#define SUPER_SCLK_DIVIDER 0x02c
61
62#define SYSTEM_CLK_RATE 0x030
63
64#define TEGRA30_CLK_PERIPH_BANKS 5
65
66#define PLLC_BASE 0x80
67#define PLLC_MISC 0x8c
68#define PLLM_BASE 0x90
69#define PLLM_MISC 0x9c
70#define PLLP_BASE 0xa0
71#define PLLP_MISC 0xac
72#define PLLX_BASE 0xe0
73#define PLLX_MISC 0xe4
74#define PLLD_BASE 0xd0
75#define PLLD_MISC 0xdc
76#define PLLD2_BASE 0x4b8
77#define PLLD2_MISC 0x4bc
78#define PLLE_BASE 0xe8
79#define PLLE_MISC 0xec
80#define PLLA_BASE 0xb0
81#define PLLA_MISC 0xbc
82#define PLLU_BASE 0xc0
83#define PLLU_MISC 0xcc
84
85#define PLL_MISC_LOCK_ENABLE 18
86#define PLLDU_MISC_LOCK_ENABLE 22
87#define PLLE_MISC_LOCK_ENABLE 9
88
89#define PLL_BASE_LOCK BIT(27)
90#define PLLE_MISC_LOCK BIT(11)
91
92#define PLLE_AUX 0x48c
93#define PLLC_OUT 0x84
94#define PLLM_OUT 0x94
95#define PLLP_OUTA 0xa4
96#define PLLP_OUTB 0xa8
97#define PLLA_OUT 0xb4
98
99#define AUDIO_SYNC_CLK_I2S0 0x4a0
100#define AUDIO_SYNC_CLK_I2S1 0x4a4
101#define AUDIO_SYNC_CLK_I2S2 0x4a8
102#define AUDIO_SYNC_CLK_I2S3 0x4ac
103#define AUDIO_SYNC_CLK_I2S4 0x4b0
104#define AUDIO_SYNC_CLK_SPDIF 0x4b4
105
106#define CLK_SOURCE_SPDIF_OUT 0x108
107#define CLK_SOURCE_PWM 0x110
108#define CLK_SOURCE_D_AUDIO 0x3d0
109#define CLK_SOURCE_DAM0 0x3d8
110#define CLK_SOURCE_DAM1 0x3dc
111#define CLK_SOURCE_DAM2 0x3e0
112#define CLK_SOURCE_3D2 0x3b0
113#define CLK_SOURCE_2D 0x15c
114#define CLK_SOURCE_HDMI 0x18c
115#define CLK_SOURCE_DSIB 0xd0
116#define CLK_SOURCE_SE 0x42c
117#define CLK_SOURCE_EMC 0x19c
118
119#define AUDIO_SYNC_DOUBLER 0x49c
120
121#define UTMIP_PLL_CFG2 0x488
122#define UTMIP_PLL_CFG2_STABLE_COUNT(x) (((x) & 0xffff) << 6)
123#define UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(x) (((x) & 0x3f) << 18)
124#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN BIT(0)
125#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN BIT(2)
126#define UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN BIT(4)
127
128#define UTMIP_PLL_CFG1 0x484
129#define UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(x) (((x) & 0x1f) << 6)
130#define UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(x) (((x) & 0xfff) << 0)
131#define UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN BIT(14)
132#define UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN BIT(12)
133#define UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN BIT(16)
134
135
136#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
137#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
138#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
139#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
140#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
141
142#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
143#define CPU_RESET(cpu) (0x1111ul << (cpu))
144
145#define CLK_RESET_CCLK_BURST 0x20
146#define CLK_RESET_CCLK_DIVIDER 0x24
147#define CLK_RESET_PLLX_BASE 0xe0
148#define CLK_RESET_PLLX_MISC 0xe4
149
150#define CLK_RESET_SOURCE_CSITE 0x1d4
151
152#define CLK_RESET_CCLK_BURST_POLICY_SHIFT 28
153#define CLK_RESET_CCLK_RUN_POLICY_SHIFT 4
154#define CLK_RESET_CCLK_IDLE_POLICY_SHIFT 0
155#define CLK_RESET_CCLK_IDLE_POLICY 1
156#define CLK_RESET_CCLK_RUN_POLICY 2
157#define CLK_RESET_CCLK_BURST_POLICY_PLLX 8
158
159
160#define PMC_PLLM_WB0_OVERRIDE 0x1dc
161
162#ifdef CONFIG_PM_SLEEP
163static struct cpu_clk_suspend_context {
164 u32 pllx_misc;
165 u32 pllx_base;
166
167 u32 cpu_burst;
168 u32 clk_csite_src;
169 u32 cclk_divider;
170} tegra30_cpu_clk_sctx;
171#endif
172
173static void __iomem *clk_base;
174static void __iomem *pmc_base;
175static unsigned long input_freq;
176
177static DEFINE_SPINLOCK(cml_lock);
178static DEFINE_SPINLOCK(pll_d_lock);
179static DEFINE_SPINLOCK(emc_lock);
180
181#define TEGRA_INIT_DATA_MUX(_name, _parents, _offset, \
182 _clk_num, _gate_flags, _clk_id) \
183 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
184 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
185 _clk_num, _gate_flags, _clk_id)
186
187#define TEGRA_INIT_DATA_MUX8(_name, _parents, _offset, \
188 _clk_num, _gate_flags, _clk_id) \
189 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
190 29, 3, 0, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, \
191 _clk_num, _gate_flags, _clk_id)
192
193#define TEGRA_INIT_DATA_INT(_name, _parents, _offset, \
194 _clk_num, _gate_flags, _clk_id) \
195 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
196 30, 2, 0, 0, 8, 1, TEGRA_DIVIDER_INT | \
197 TEGRA_DIVIDER_ROUND_UP, _clk_num, \
198 _gate_flags, _clk_id)
199
200#define TEGRA_INIT_DATA_NODIV(_name, _parents, _offset, \
201 _mux_shift, _mux_width, _clk_num, \
202 _gate_flags, _clk_id) \
203 TEGRA_INIT_DATA(_name, NULL, NULL, _parents, _offset, \
204 _mux_shift, _mux_width, 0, 0, 0, 0, 0,\
205 _clk_num, _gate_flags, \
206 _clk_id)
207
208static struct clk **clks;
209
210
211
212
213struct utmi_clk_param {
214
215 u32 osc_frequency;
216
217 u8 enable_delay_count;
218
219 u8 stable_count;
220
221 u8 active_delay_count;
222
223 u8 xtal_freq_count;
224};
225
226static const struct utmi_clk_param utmi_parameters[] = {
227 {
228 .osc_frequency = 13000000, .enable_delay_count = 0x02,
229 .stable_count = 0x33, .active_delay_count = 0x05,
230 .xtal_freq_count = 0x7f
231 }, {
232 .osc_frequency = 19200000, .enable_delay_count = 0x03,
233 .stable_count = 0x4b, .active_delay_count = 0x06,
234 .xtal_freq_count = 0xbb
235 }, {
236 .osc_frequency = 12000000, .enable_delay_count = 0x02,
237 .stable_count = 0x2f, .active_delay_count = 0x04,
238 .xtal_freq_count = 0x76
239 }, {
240 .osc_frequency = 26000000, .enable_delay_count = 0x04,
241 .stable_count = 0x66, .active_delay_count = 0x09,
242 .xtal_freq_count = 0xfe
243 }, {
244 .osc_frequency = 16800000, .enable_delay_count = 0x03,
245 .stable_count = 0x41, .active_delay_count = 0x0a,
246 .xtal_freq_count = 0xa4
247 },
248};
249
250static struct tegra_clk_pll_freq_table pll_c_freq_table[] = {
251 { 12000000, 1040000000, 520, 6, 1, 8 },
252 { 13000000, 1040000000, 480, 6, 1, 8 },
253 { 16800000, 1040000000, 495, 8, 1, 8 },
254 { 19200000, 1040000000, 325, 6, 1, 6 },
255 { 26000000, 1040000000, 520, 13, 1, 8 },
256 { 12000000, 832000000, 416, 6, 1, 8 },
257 { 13000000, 832000000, 832, 13, 1, 8 },
258 { 16800000, 832000000, 396, 8, 1, 8 },
259 { 19200000, 832000000, 260, 6, 1, 8 },
260 { 26000000, 832000000, 416, 13, 1, 8 },
261 { 12000000, 624000000, 624, 12, 1, 8 },
262 { 13000000, 624000000, 624, 13, 1, 8 },
263 { 16800000, 600000000, 520, 14, 1, 8 },
264 { 19200000, 624000000, 520, 16, 1, 8 },
265 { 26000000, 624000000, 624, 26, 1, 8 },
266 { 12000000, 600000000, 600, 12, 1, 8 },
267 { 13000000, 600000000, 600, 13, 1, 8 },
268 { 16800000, 600000000, 500, 14, 1, 8 },
269 { 19200000, 600000000, 375, 12, 1, 6 },
270 { 26000000, 600000000, 600, 26, 1, 8 },
271 { 12000000, 520000000, 520, 12, 1, 8 },
272 { 13000000, 520000000, 520, 13, 1, 8 },
273 { 16800000, 520000000, 495, 16, 1, 8 },
274 { 19200000, 520000000, 325, 12, 1, 6 },
275 { 26000000, 520000000, 520, 26, 1, 8 },
276 { 12000000, 416000000, 416, 12, 1, 8 },
277 { 13000000, 416000000, 416, 13, 1, 8 },
278 { 16800000, 416000000, 396, 16, 1, 8 },
279 { 19200000, 416000000, 260, 12, 1, 6 },
280 { 26000000, 416000000, 416, 26, 1, 8 },
281 { 0, 0, 0, 0, 0, 0 },
282};
283
284static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
285 { 12000000, 666000000, 666, 12, 1, 8 },
286 { 13000000, 666000000, 666, 13, 1, 8 },
287 { 16800000, 666000000, 555, 14, 1, 8 },
288 { 19200000, 666000000, 555, 16, 1, 8 },
289 { 26000000, 666000000, 666, 26, 1, 8 },
290 { 12000000, 600000000, 600, 12, 1, 8 },
291 { 13000000, 600000000, 600, 13, 1, 8 },
292 { 16800000, 600000000, 500, 14, 1, 8 },
293 { 19200000, 600000000, 375, 12, 1, 6 },
294 { 26000000, 600000000, 600, 26, 1, 8 },
295 { 0, 0, 0, 0, 0, 0 },
296};
297
298static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
299 { 12000000, 216000000, 432, 12, 2, 8 },
300 { 13000000, 216000000, 432, 13, 2, 8 },
301 { 16800000, 216000000, 360, 14, 2, 8 },
302 { 19200000, 216000000, 360, 16, 2, 8 },
303 { 26000000, 216000000, 432, 26, 2, 8 },
304 { 0, 0, 0, 0, 0, 0 },
305};
306
307static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
308 { 9600000, 564480000, 294, 5, 1, 4 },
309 { 9600000, 552960000, 288, 5, 1, 4 },
310 { 9600000, 24000000, 5, 2, 1, 1 },
311 { 28800000, 56448000, 49, 25, 1, 1 },
312 { 28800000, 73728000, 64, 25, 1, 1 },
313 { 28800000, 24000000, 5, 6, 1, 1 },
314 { 0, 0, 0, 0, 0, 0 },
315};
316
317static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
318 { 12000000, 216000000, 216, 12, 1, 4 },
319 { 13000000, 216000000, 216, 13, 1, 4 },
320 { 16800000, 216000000, 180, 14, 1, 4 },
321 { 19200000, 216000000, 180, 16, 1, 4 },
322 { 26000000, 216000000, 216, 26, 1, 4 },
323 { 12000000, 594000000, 594, 12, 1, 8 },
324 { 13000000, 594000000, 594, 13, 1, 8 },
325 { 16800000, 594000000, 495, 14, 1, 8 },
326 { 19200000, 594000000, 495, 16, 1, 8 },
327 { 26000000, 594000000, 594, 26, 1, 8 },
328 { 12000000, 1000000000, 1000, 12, 1, 12 },
329 { 13000000, 1000000000, 1000, 13, 1, 12 },
330 { 19200000, 1000000000, 625, 12, 1, 8 },
331 { 26000000, 1000000000, 1000, 26, 1, 12 },
332 { 0, 0, 0, 0, 0, 0 },
333};
334
335static const struct pdiv_map pllu_p[] = {
336 { .pdiv = 1, .hw_val = 1 },
337 { .pdiv = 2, .hw_val = 0 },
338 { .pdiv = 0, .hw_val = 0 },
339};
340
341static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
342 { 12000000, 480000000, 960, 12, 1, 12 },
343 { 13000000, 480000000, 960, 13, 1, 12 },
344 { 16800000, 480000000, 400, 7, 1, 5 },
345 { 19200000, 480000000, 200, 4, 1, 3 },
346 { 26000000, 480000000, 960, 26, 1, 12 },
347 { 0, 0, 0, 0, 0, 0 },
348};
349
350static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
351
352 { 12000000, 1700000000, 850, 6, 1, 8 },
353 { 13000000, 1700000000, 915, 7, 1, 8 },
354 { 16800000, 1700000000, 708, 7, 1, 8 },
355 { 19200000, 1700000000, 885, 10, 1, 8 },
356 { 26000000, 1700000000, 850, 13, 1, 8 },
357
358 { 12000000, 1600000000, 800, 6, 1, 8 },
359 { 13000000, 1600000000, 738, 6, 1, 8 },
360 { 16800000, 1600000000, 857, 9, 1, 8 },
361 { 19200000, 1600000000, 500, 6, 1, 8 },
362 { 26000000, 1600000000, 800, 13, 1, 8 },
363
364 { 12000000, 1500000000, 750, 6, 1, 8 },
365 { 13000000, 1500000000, 923, 8, 1, 8 },
366 { 16800000, 1500000000, 625, 7, 1, 8 },
367 { 19200000, 1500000000, 625, 8, 1, 8 },
368 { 26000000, 1500000000, 750, 13, 1, 8 },
369
370 { 12000000, 1400000000, 700, 6, 1, 8 },
371 { 13000000, 1400000000, 969, 9, 1, 8 },
372 { 16800000, 1400000000, 1000, 12, 1, 8 },
373 { 19200000, 1400000000, 875, 12, 1, 8 },
374 { 26000000, 1400000000, 700, 13, 1, 8 },
375
376 { 12000000, 1300000000, 975, 9, 1, 8 },
377 { 13000000, 1300000000, 1000, 10, 1, 8 },
378 { 16800000, 1300000000, 928, 12, 1, 8 },
379 { 19200000, 1300000000, 812, 12, 1, 8 },
380 { 26000000, 1300000000, 650, 13, 1, 8 },
381
382 { 12000000, 1200000000, 1000, 10, 1, 8 },
383 { 13000000, 1200000000, 923, 10, 1, 8 },
384 { 16800000, 1200000000, 1000, 14, 1, 8 },
385 { 19200000, 1200000000, 1000, 16, 1, 8 },
386 { 26000000, 1200000000, 600, 13, 1, 8 },
387
388 { 12000000, 1100000000, 825, 9, 1, 8 },
389 { 13000000, 1100000000, 846, 10, 1, 8 },
390 { 16800000, 1100000000, 982, 15, 1, 8 },
391 { 19200000, 1100000000, 859, 15, 1, 8 },
392 { 26000000, 1100000000, 550, 13, 1, 8 },
393
394 { 12000000, 1000000000, 1000, 12, 1, 8 },
395 { 13000000, 1000000000, 1000, 13, 1, 8 },
396 { 16800000, 1000000000, 833, 14, 1, 8 },
397 { 19200000, 1000000000, 625, 12, 1, 8 },
398 { 26000000, 1000000000, 1000, 26, 1, 8 },
399 { 0, 0, 0, 0, 0, 0 },
400};
401
402static const struct pdiv_map plle_p[] = {
403 { .pdiv = 18, .hw_val = 18 },
404 { .pdiv = 24, .hw_val = 24 },
405 { .pdiv = 0, .hw_val = 0 },
406};
407
408static struct tegra_clk_pll_freq_table pll_e_freq_table[] = {
409
410 { 12000000, 100000000, 150, 1, 18, 11 },
411 { 216000000, 100000000, 200, 18, 24, 13 },
412 { 0, 0, 0, 0, 0, 0 },
413};
414
415
416static struct tegra_clk_pll_params pll_c_params = {
417 .input_min = 2000000,
418 .input_max = 31000000,
419 .cf_min = 1000000,
420 .cf_max = 6000000,
421 .vco_min = 20000000,
422 .vco_max = 1400000000,
423 .base_reg = PLLC_BASE,
424 .misc_reg = PLLC_MISC,
425 .lock_mask = PLL_BASE_LOCK,
426 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
427 .lock_delay = 300,
428 .freq_table = pll_c_freq_table,
429 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
430 TEGRA_PLL_HAS_LOCK_ENABLE,
431};
432
433static struct div_nmp pllm_nmp = {
434 .divn_shift = 8,
435 .divn_width = 10,
436 .override_divn_shift = 5,
437 .divm_shift = 0,
438 .divm_width = 5,
439 .override_divm_shift = 0,
440 .divp_shift = 20,
441 .divp_width = 3,
442 .override_divp_shift = 15,
443};
444
445static struct tegra_clk_pll_params pll_m_params = {
446 .input_min = 2000000,
447 .input_max = 31000000,
448 .cf_min = 1000000,
449 .cf_max = 6000000,
450 .vco_min = 20000000,
451 .vco_max = 1200000000,
452 .base_reg = PLLM_BASE,
453 .misc_reg = PLLM_MISC,
454 .lock_mask = PLL_BASE_LOCK,
455 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
456 .lock_delay = 300,
457 .div_nmp = &pllm_nmp,
458 .pmc_divnm_reg = PMC_PLLM_WB0_OVERRIDE,
459 .pmc_divp_reg = PMC_PLLM_WB0_OVERRIDE,
460 .freq_table = pll_m_freq_table,
461 .flags = TEGRA_PLLM | TEGRA_PLL_HAS_CPCON |
462 TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK |
463 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_FIXED,
464};
465
466static struct tegra_clk_pll_params pll_p_params = {
467 .input_min = 2000000,
468 .input_max = 31000000,
469 .cf_min = 1000000,
470 .cf_max = 6000000,
471 .vco_min = 20000000,
472 .vco_max = 1400000000,
473 .base_reg = PLLP_BASE,
474 .misc_reg = PLLP_MISC,
475 .lock_mask = PLL_BASE_LOCK,
476 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
477 .lock_delay = 300,
478 .freq_table = pll_p_freq_table,
479 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
480 TEGRA_PLL_HAS_LOCK_ENABLE,
481 .fixed_rate = 408000000,
482};
483
484static struct tegra_clk_pll_params pll_a_params = {
485 .input_min = 2000000,
486 .input_max = 31000000,
487 .cf_min = 1000000,
488 .cf_max = 6000000,
489 .vco_min = 20000000,
490 .vco_max = 1400000000,
491 .base_reg = PLLA_BASE,
492 .misc_reg = PLLA_MISC,
493 .lock_mask = PLL_BASE_LOCK,
494 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
495 .lock_delay = 300,
496 .freq_table = pll_a_freq_table,
497 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_USE_LOCK |
498 TEGRA_PLL_HAS_LOCK_ENABLE,
499};
500
501static struct tegra_clk_pll_params pll_d_params = {
502 .input_min = 2000000,
503 .input_max = 40000000,
504 .cf_min = 1000000,
505 .cf_max = 6000000,
506 .vco_min = 40000000,
507 .vco_max = 1000000000,
508 .base_reg = PLLD_BASE,
509 .misc_reg = PLLD_MISC,
510 .lock_mask = PLL_BASE_LOCK,
511 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
512 .lock_delay = 1000,
513 .freq_table = pll_d_freq_table,
514 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
515 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
516};
517
518static struct tegra_clk_pll_params pll_d2_params = {
519 .input_min = 2000000,
520 .input_max = 40000000,
521 .cf_min = 1000000,
522 .cf_max = 6000000,
523 .vco_min = 40000000,
524 .vco_max = 1000000000,
525 .base_reg = PLLD2_BASE,
526 .misc_reg = PLLD2_MISC,
527 .lock_mask = PLL_BASE_LOCK,
528 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
529 .lock_delay = 1000,
530 .freq_table = pll_d_freq_table,
531 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
532 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
533};
534
535static struct tegra_clk_pll_params pll_u_params = {
536 .input_min = 2000000,
537 .input_max = 40000000,
538 .cf_min = 1000000,
539 .cf_max = 6000000,
540 .vco_min = 48000000,
541 .vco_max = 960000000,
542 .base_reg = PLLU_BASE,
543 .misc_reg = PLLU_MISC,
544 .lock_mask = PLL_BASE_LOCK,
545 .lock_enable_bit_idx = PLLDU_MISC_LOCK_ENABLE,
546 .lock_delay = 1000,
547 .pdiv_tohw = pllu_p,
548 .freq_table = pll_u_freq_table,
549 .flags = TEGRA_PLLU | TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_LFCON |
550 TEGRA_PLL_HAS_LOCK_ENABLE,
551};
552
553static struct tegra_clk_pll_params pll_x_params = {
554 .input_min = 2000000,
555 .input_max = 31000000,
556 .cf_min = 1000000,
557 .cf_max = 6000000,
558 .vco_min = 20000000,
559 .vco_max = 1700000000,
560 .base_reg = PLLX_BASE,
561 .misc_reg = PLLX_MISC,
562 .lock_mask = PLL_BASE_LOCK,
563 .lock_enable_bit_idx = PLL_MISC_LOCK_ENABLE,
564 .lock_delay = 300,
565 .freq_table = pll_x_freq_table,
566 .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON |
567 TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE,
568};
569
570static struct tegra_clk_pll_params pll_e_params = {
571 .input_min = 12000000,
572 .input_max = 216000000,
573 .cf_min = 12000000,
574 .cf_max = 12000000,
575 .vco_min = 1200000000,
576 .vco_max = 2400000000U,
577 .base_reg = PLLE_BASE,
578 .misc_reg = PLLE_MISC,
579 .lock_mask = PLLE_MISC_LOCK,
580 .lock_enable_bit_idx = PLLE_MISC_LOCK_ENABLE,
581 .lock_delay = 300,
582 .pdiv_tohw = plle_p,
583 .freq_table = pll_e_freq_table,
584 .flags = TEGRA_PLLE_CONFIGURE | TEGRA_PLL_FIXED |
585 TEGRA_PLL_HAS_LOCK_ENABLE | TEGRA_PLL_LOCK_MISC,
586 .fixed_rate = 100000000,
587};
588
589static unsigned long tegra30_input_freq[] = {
590 [ 0] = 13000000,
591 [ 1] = 16800000,
592 [ 4] = 19200000,
593 [ 5] = 38400000,
594 [ 8] = 12000000,
595 [ 9] = 48000000,
596 [12] = 26000000,
597};
598
599static struct tegra_devclk devclks[] __initdata = {
600 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
601 { .con_id = "pll_c_out1", .dt_id = TEGRA30_CLK_PLL_C_OUT1 },
602 { .con_id = "pll_p", .dt_id = TEGRA30_CLK_PLL_P },
603 { .con_id = "pll_p_out1", .dt_id = TEGRA30_CLK_PLL_P_OUT1 },
604 { .con_id = "pll_p_out2", .dt_id = TEGRA30_CLK_PLL_P_OUT2 },
605 { .con_id = "pll_p_out3", .dt_id = TEGRA30_CLK_PLL_P_OUT3 },
606 { .con_id = "pll_p_out4", .dt_id = TEGRA30_CLK_PLL_P_OUT4 },
607 { .con_id = "pll_m", .dt_id = TEGRA30_CLK_PLL_M },
608 { .con_id = "pll_m_out1", .dt_id = TEGRA30_CLK_PLL_M_OUT1 },
609 { .con_id = "pll_x", .dt_id = TEGRA30_CLK_PLL_X },
610 { .con_id = "pll_x_out0", .dt_id = TEGRA30_CLK_PLL_X_OUT0 },
611 { .con_id = "pll_u", .dt_id = TEGRA30_CLK_PLL_U },
612 { .con_id = "pll_d", .dt_id = TEGRA30_CLK_PLL_D },
613 { .con_id = "pll_d_out0", .dt_id = TEGRA30_CLK_PLL_D_OUT0 },
614 { .con_id = "pll_d2", .dt_id = TEGRA30_CLK_PLL_D2 },
615 { .con_id = "pll_d2_out0", .dt_id = TEGRA30_CLK_PLL_D2_OUT0 },
616 { .con_id = "pll_a", .dt_id = TEGRA30_CLK_PLL_A },
617 { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },
618 { .con_id = "pll_e", .dt_id = TEGRA30_CLK_PLL_E },
619 { .con_id = "spdif_in_sync", .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC },
620 { .con_id = "i2s0_sync", .dt_id = TEGRA30_CLK_I2S0_SYNC },
621 { .con_id = "i2s1_sync", .dt_id = TEGRA30_CLK_I2S1_SYNC },
622 { .con_id = "i2s2_sync", .dt_id = TEGRA30_CLK_I2S2_SYNC },
623 { .con_id = "i2s3_sync", .dt_id = TEGRA30_CLK_I2S3_SYNC },
624 { .con_id = "i2s4_sync", .dt_id = TEGRA30_CLK_I2S4_SYNC },
625 { .con_id = "vimclk_sync", .dt_id = TEGRA30_CLK_VIMCLK_SYNC },
626 { .con_id = "audio0", .dt_id = TEGRA30_CLK_AUDIO0 },
627 { .con_id = "audio1", .dt_id = TEGRA30_CLK_AUDIO1 },
628 { .con_id = "audio2", .dt_id = TEGRA30_CLK_AUDIO2 },
629 { .con_id = "audio3", .dt_id = TEGRA30_CLK_AUDIO3 },
630 { .con_id = "audio4", .dt_id = TEGRA30_CLK_AUDIO4 },
631 { .con_id = "spdif", .dt_id = TEGRA30_CLK_SPDIF },
632 { .con_id = "audio0_2x", .dt_id = TEGRA30_CLK_AUDIO0_2X },
633 { .con_id = "audio1_2x", .dt_id = TEGRA30_CLK_AUDIO1_2X },
634 { .con_id = "audio2_2x", .dt_id = TEGRA30_CLK_AUDIO2_2X },
635 { .con_id = "audio3_2x", .dt_id = TEGRA30_CLK_AUDIO3_2X },
636 { .con_id = "audio4_2x", .dt_id = TEGRA30_CLK_AUDIO4_2X },
637 { .con_id = "spdif_2x", .dt_id = TEGRA30_CLK_SPDIF_2X },
638 { .con_id = "extern1", .dev_id = "clk_out_1", .dt_id = TEGRA30_CLK_EXTERN1 },
639 { .con_id = "extern2", .dev_id = "clk_out_2", .dt_id = TEGRA30_CLK_EXTERN2 },
640 { .con_id = "extern3", .dev_id = "clk_out_3", .dt_id = TEGRA30_CLK_EXTERN3 },
641 { .con_id = "blink", .dt_id = TEGRA30_CLK_BLINK },
642 { .con_id = "cclk_g", .dt_id = TEGRA30_CLK_CCLK_G },
643 { .con_id = "cclk_lp", .dt_id = TEGRA30_CLK_CCLK_LP },
644 { .con_id = "sclk", .dt_id = TEGRA30_CLK_SCLK },
645 { .con_id = "hclk", .dt_id = TEGRA30_CLK_HCLK },
646 { .con_id = "pclk", .dt_id = TEGRA30_CLK_PCLK },
647 { .con_id = "twd", .dt_id = TEGRA30_CLK_TWD },
648 { .con_id = "emc", .dt_id = TEGRA30_CLK_EMC },
649 { .con_id = "clk_32k", .dt_id = TEGRA30_CLK_CLK_32K },
650 { .con_id = "clk_m_div2", .dt_id = TEGRA30_CLK_CLK_M_DIV2 },
651 { .con_id = "clk_m_div4", .dt_id = TEGRA30_CLK_CLK_M_DIV4 },
652 { .con_id = "cml0", .dt_id = TEGRA30_CLK_CML0 },
653 { .con_id = "cml1", .dt_id = TEGRA30_CLK_CML1 },
654 { .con_id = "clk_m", .dt_id = TEGRA30_CLK_CLK_M },
655 { .con_id = "pll_ref", .dt_id = TEGRA30_CLK_PLL_REF },
656 { .con_id = "csus", .dev_id = "tengra_camera", .dt_id = TEGRA30_CLK_CSUS },
657 { .con_id = "vcp", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_VCP },
658 { .con_id = "bsea", .dev_id = "tegra-avp", .dt_id = TEGRA30_CLK_BSEA },
659 { .con_id = "bsev", .dev_id = "tegra-aes", .dt_id = TEGRA30_CLK_BSEV },
660 { .con_id = "dsia", .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DSIA },
661 { .con_id = "csi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_CSI },
662 { .con_id = "isp", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_ISP },
663 { .con_id = "pcie", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_PCIE },
664 { .con_id = "afi", .dev_id = "tegra-pcie", .dt_id = TEGRA30_CLK_AFI },
665 { .con_id = "fuse", .dt_id = TEGRA30_CLK_FUSE },
666 { .con_id = "fuse_burn", .dev_id = "fuse-tegra", .dt_id = TEGRA30_CLK_FUSE_BURN },
667 { .con_id = "apbif", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_APBIF },
668 { .con_id = "hda2hdmi", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2HDMI },
669 { .dev_id = "tegra-apbdma", .dt_id = TEGRA30_CLK_APBDMA },
670 { .dev_id = "rtc-tegra", .dt_id = TEGRA30_CLK_RTC },
671 { .dev_id = "timer", .dt_id = TEGRA30_CLK_TIMER },
672 { .dev_id = "tegra-kbc", .dt_id = TEGRA30_CLK_KBC },
673 { .dev_id = "fsl-tegra-udc", .dt_id = TEGRA30_CLK_USBD },
674 { .dev_id = "tegra-ehci.1", .dt_id = TEGRA30_CLK_USB2 },
675 { .dev_id = "tegra-ehci.2", .dt_id = TEGRA30_CLK_USB2 },
676 { .dev_id = "kfuse-tegra", .dt_id = TEGRA30_CLK_KFUSE },
677 { .dev_id = "tegra_sata_cold", .dt_id = TEGRA30_CLK_SATA_COLD },
678 { .dev_id = "dtv", .dt_id = TEGRA30_CLK_DTV },
679 { .dev_id = "tegra30-i2s.0", .dt_id = TEGRA30_CLK_I2S0 },
680 { .dev_id = "tegra30-i2s.1", .dt_id = TEGRA30_CLK_I2S1 },
681 { .dev_id = "tegra30-i2s.2", .dt_id = TEGRA30_CLK_I2S2 },
682 { .dev_id = "tegra30-i2s.3", .dt_id = TEGRA30_CLK_I2S3 },
683 { .dev_id = "tegra30-i2s.4", .dt_id = TEGRA30_CLK_I2S4 },
684 { .con_id = "spdif_out", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_OUT },
685 { .con_id = "spdif_in", .dev_id = "tegra30-spdif", .dt_id = TEGRA30_CLK_SPDIF_IN },
686 { .con_id = "d_audio", .dev_id = "tegra30-ahub", .dt_id = TEGRA30_CLK_D_AUDIO },
687 { .dev_id = "tegra30-dam.0", .dt_id = TEGRA30_CLK_DAM0 },
688 { .dev_id = "tegra30-dam.1", .dt_id = TEGRA30_CLK_DAM1 },
689 { .dev_id = "tegra30-dam.2", .dt_id = TEGRA30_CLK_DAM2 },
690 { .con_id = "hda", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA },
691 { .con_id = "hda2codec_2x", .dev_id = "tegra30-hda", .dt_id = TEGRA30_CLK_HDA2CODEC_2X },
692 { .dev_id = "spi_tegra.0", .dt_id = TEGRA30_CLK_SBC1 },
693 { .dev_id = "spi_tegra.1", .dt_id = TEGRA30_CLK_SBC2 },
694 { .dev_id = "spi_tegra.2", .dt_id = TEGRA30_CLK_SBC3 },
695 { .dev_id = "spi_tegra.3", .dt_id = TEGRA30_CLK_SBC4 },
696 { .dev_id = "spi_tegra.4", .dt_id = TEGRA30_CLK_SBC5 },
697 { .dev_id = "spi_tegra.5", .dt_id = TEGRA30_CLK_SBC6 },
698 { .dev_id = "tegra_sata_oob", .dt_id = TEGRA30_CLK_SATA_OOB },
699 { .dev_id = "tegra_sata", .dt_id = TEGRA30_CLK_SATA },
700 { .dev_id = "tegra_nand", .dt_id = TEGRA30_CLK_NDFLASH },
701 { .dev_id = "tegra_nand_speed", .dt_id = TEGRA30_CLK_NDSPEED },
702 { .dev_id = "vfir", .dt_id = TEGRA30_CLK_VFIR },
703 { .dev_id = "csite", .dt_id = TEGRA30_CLK_CSITE },
704 { .dev_id = "la", .dt_id = TEGRA30_CLK_LA },
705 { .dev_id = "tegra_w1", .dt_id = TEGRA30_CLK_OWR },
706 { .dev_id = "mipi", .dt_id = TEGRA30_CLK_MIPI },
707 { .dev_id = "tegra-tsensor", .dt_id = TEGRA30_CLK_TSENSOR },
708 { .dev_id = "i2cslow", .dt_id = TEGRA30_CLK_I2CSLOW },
709 { .dev_id = "vde", .dt_id = TEGRA30_CLK_VDE },
710 { .con_id = "vi", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI },
711 { .dev_id = "epp", .dt_id = TEGRA30_CLK_EPP },
712 { .dev_id = "mpe", .dt_id = TEGRA30_CLK_MPE },
713 { .dev_id = "host1x", .dt_id = TEGRA30_CLK_HOST1X },
714 { .dev_id = "3d", .dt_id = TEGRA30_CLK_GR3D },
715 { .dev_id = "3d2", .dt_id = TEGRA30_CLK_GR3D2 },
716 { .dev_id = "2d", .dt_id = TEGRA30_CLK_GR2D },
717 { .dev_id = "se", .dt_id = TEGRA30_CLK_SE },
718 { .dev_id = "mselect", .dt_id = TEGRA30_CLK_MSELECT },
719 { .dev_id = "tegra-nor", .dt_id = TEGRA30_CLK_NOR },
720 { .dev_id = "sdhci-tegra.0", .dt_id = TEGRA30_CLK_SDMMC1 },
721 { .dev_id = "sdhci-tegra.1", .dt_id = TEGRA30_CLK_SDMMC2 },
722 { .dev_id = "sdhci-tegra.2", .dt_id = TEGRA30_CLK_SDMMC3 },
723 { .dev_id = "sdhci-tegra.3", .dt_id = TEGRA30_CLK_SDMMC4 },
724 { .dev_id = "cve", .dt_id = TEGRA30_CLK_CVE },
725 { .dev_id = "tvo", .dt_id = TEGRA30_CLK_TVO },
726 { .dev_id = "tvdac", .dt_id = TEGRA30_CLK_TVDAC },
727 { .dev_id = "actmon", .dt_id = TEGRA30_CLK_ACTMON },
728 { .con_id = "vi_sensor", .dev_id = "tegra_camera", .dt_id = TEGRA30_CLK_VI_SENSOR },
729 { .con_id = "div-clk", .dev_id = "tegra-i2c.0", .dt_id = TEGRA30_CLK_I2C1 },
730 { .con_id = "div-clk", .dev_id = "tegra-i2c.1", .dt_id = TEGRA30_CLK_I2C2 },
731 { .con_id = "div-clk", .dev_id = "tegra-i2c.2", .dt_id = TEGRA30_CLK_I2C3 },
732 { .con_id = "div-clk", .dev_id = "tegra-i2c.3", .dt_id = TEGRA30_CLK_I2C4 },
733 { .con_id = "div-clk", .dev_id = "tegra-i2c.4", .dt_id = TEGRA30_CLK_I2C5 },
734 { .dev_id = "tegra_uart.0", .dt_id = TEGRA30_CLK_UARTA },
735 { .dev_id = "tegra_uart.1", .dt_id = TEGRA30_CLK_UARTB },
736 { .dev_id = "tegra_uart.2", .dt_id = TEGRA30_CLK_UARTC },
737 { .dev_id = "tegra_uart.3", .dt_id = TEGRA30_CLK_UARTD },
738 { .dev_id = "tegra_uart.4", .dt_id = TEGRA30_CLK_UARTE },
739 { .dev_id = "hdmi", .dt_id = TEGRA30_CLK_HDMI },
740 { .dev_id = "extern1", .dt_id = TEGRA30_CLK_EXTERN1 },
741 { .dev_id = "extern2", .dt_id = TEGRA30_CLK_EXTERN2 },
742 { .dev_id = "extern3", .dt_id = TEGRA30_CLK_EXTERN3 },
743 { .dev_id = "pwm", .dt_id = TEGRA30_CLK_PWM },
744 { .dev_id = "tegradc.0", .dt_id = TEGRA30_CLK_DISP1 },
745 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DISP2 },
746 { .dev_id = "tegradc.1", .dt_id = TEGRA30_CLK_DSIB },
747};
748
749static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = {
750 [tegra_clk_clk_32k] = { .dt_id = TEGRA30_CLK_CLK_32K, .present = true },
751 [tegra_clk_clk_m] = { .dt_id = TEGRA30_CLK_CLK_M, .present = true },
752 [tegra_clk_clk_m_div2] = { .dt_id = TEGRA30_CLK_CLK_M_DIV2, .present = true },
753 [tegra_clk_clk_m_div4] = { .dt_id = TEGRA30_CLK_CLK_M_DIV4, .present = true },
754 [tegra_clk_pll_ref] = { .dt_id = TEGRA30_CLK_PLL_REF, .present = true },
755 [tegra_clk_spdif_in_sync] = { .dt_id = TEGRA30_CLK_SPDIF_IN_SYNC, .present = true },
756 [tegra_clk_i2s0_sync] = { .dt_id = TEGRA30_CLK_I2S0_SYNC, .present = true },
757 [tegra_clk_i2s1_sync] = { .dt_id = TEGRA30_CLK_I2S1_SYNC, .present = true },
758 [tegra_clk_i2s2_sync] = { .dt_id = TEGRA30_CLK_I2S2_SYNC, .present = true },
759 [tegra_clk_i2s3_sync] = { .dt_id = TEGRA30_CLK_I2S3_SYNC, .present = true },
760 [tegra_clk_i2s4_sync] = { .dt_id = TEGRA30_CLK_I2S4_SYNC, .present = true },
761 [tegra_clk_vimclk_sync] = { .dt_id = TEGRA30_CLK_VIMCLK_SYNC, .present = true },
762 [tegra_clk_audio0] = { .dt_id = TEGRA30_CLK_AUDIO0, .present = true },
763 [tegra_clk_audio1] = { .dt_id = TEGRA30_CLK_AUDIO1, .present = true },
764 [tegra_clk_audio2] = { .dt_id = TEGRA30_CLK_AUDIO2, .present = true },
765 [tegra_clk_audio3] = { .dt_id = TEGRA30_CLK_AUDIO3, .present = true },
766 [tegra_clk_audio4] = { .dt_id = TEGRA30_CLK_AUDIO4, .present = true },
767 [tegra_clk_spdif] = { .dt_id = TEGRA30_CLK_SPDIF, .present = true },
768 [tegra_clk_audio0_mux] = { .dt_id = TEGRA30_CLK_AUDIO0_MUX, .present = true },
769 [tegra_clk_audio1_mux] = { .dt_id = TEGRA30_CLK_AUDIO1_MUX, .present = true },
770 [tegra_clk_audio2_mux] = { .dt_id = TEGRA30_CLK_AUDIO2_MUX, .present = true },
771 [tegra_clk_audio3_mux] = { .dt_id = TEGRA30_CLK_AUDIO3_MUX, .present = true },
772 [tegra_clk_audio4_mux] = { .dt_id = TEGRA30_CLK_AUDIO4_MUX, .present = true },
773 [tegra_clk_spdif_mux] = { .dt_id = TEGRA30_CLK_SPDIF_MUX, .present = true },
774 [tegra_clk_audio0_2x] = { .dt_id = TEGRA30_CLK_AUDIO0_2X, .present = true },
775 [tegra_clk_audio1_2x] = { .dt_id = TEGRA30_CLK_AUDIO1_2X, .present = true },
776 [tegra_clk_audio2_2x] = { .dt_id = TEGRA30_CLK_AUDIO2_2X, .present = true },
777 [tegra_clk_audio3_2x] = { .dt_id = TEGRA30_CLK_AUDIO3_2X, .present = true },
778 [tegra_clk_audio4_2x] = { .dt_id = TEGRA30_CLK_AUDIO4_2X, .present = true },
779 [tegra_clk_spdif_2x] = { .dt_id = TEGRA30_CLK_SPDIF_2X, .present = true },
780 [tegra_clk_clk_out_1] = { .dt_id = TEGRA30_CLK_CLK_OUT_1, .present = true },
781 [tegra_clk_clk_out_2] = { .dt_id = TEGRA30_CLK_CLK_OUT_2, .present = true },
782 [tegra_clk_clk_out_3] = { .dt_id = TEGRA30_CLK_CLK_OUT_3, .present = true },
783 [tegra_clk_blink] = { .dt_id = TEGRA30_CLK_BLINK, .present = true },
784 [tegra_clk_clk_out_1_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_1_MUX, .present = true },
785 [tegra_clk_clk_out_2_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_2_MUX, .present = true },
786 [tegra_clk_clk_out_3_mux] = { .dt_id = TEGRA30_CLK_CLK_OUT_3_MUX, .present = true },
787 [tegra_clk_hclk] = { .dt_id = TEGRA30_CLK_HCLK, .present = true },
788 [tegra_clk_pclk] = { .dt_id = TEGRA30_CLK_PCLK, .present = true },
789 [tegra_clk_i2s0] = { .dt_id = TEGRA30_CLK_I2S0, .present = true },
790 [tegra_clk_i2s1] = { .dt_id = TEGRA30_CLK_I2S1, .present = true },
791 [tegra_clk_i2s2] = { .dt_id = TEGRA30_CLK_I2S2, .present = true },
792 [tegra_clk_i2s3] = { .dt_id = TEGRA30_CLK_I2S3, .present = true },
793 [tegra_clk_i2s4] = { .dt_id = TEGRA30_CLK_I2S4, .present = true },
794 [tegra_clk_spdif_in] = { .dt_id = TEGRA30_CLK_SPDIF_IN, .present = true },
795 [tegra_clk_hda] = { .dt_id = TEGRA30_CLK_HDA, .present = true },
796 [tegra_clk_hda2codec_2x] = { .dt_id = TEGRA30_CLK_HDA2CODEC_2X, .present = true },
797 [tegra_clk_sbc1] = { .dt_id = TEGRA30_CLK_SBC1, .present = true },
798 [tegra_clk_sbc2] = { .dt_id = TEGRA30_CLK_SBC2, .present = true },
799 [tegra_clk_sbc3] = { .dt_id = TEGRA30_CLK_SBC3, .present = true },
800 [tegra_clk_sbc4] = { .dt_id = TEGRA30_CLK_SBC4, .present = true },
801 [tegra_clk_sbc5] = { .dt_id = TEGRA30_CLK_SBC5, .present = true },
802 [tegra_clk_sbc6] = { .dt_id = TEGRA30_CLK_SBC6, .present = true },
803 [tegra_clk_ndflash] = { .dt_id = TEGRA30_CLK_NDFLASH, .present = true },
804 [tegra_clk_ndspeed] = { .dt_id = TEGRA30_CLK_NDSPEED, .present = true },
805 [tegra_clk_vfir] = { .dt_id = TEGRA30_CLK_VFIR, .present = true },
806 [tegra_clk_la] = { .dt_id = TEGRA30_CLK_LA, .present = true },
807 [tegra_clk_csite] = { .dt_id = TEGRA30_CLK_CSITE, .present = true },
808 [tegra_clk_owr] = { .dt_id = TEGRA30_CLK_OWR, .present = true },
809 [tegra_clk_mipi] = { .dt_id = TEGRA30_CLK_MIPI, .present = true },
810 [tegra_clk_tsensor] = { .dt_id = TEGRA30_CLK_TSENSOR, .present = true },
811 [tegra_clk_i2cslow] = { .dt_id = TEGRA30_CLK_I2CSLOW, .present = true },
812 [tegra_clk_vde] = { .dt_id = TEGRA30_CLK_VDE, .present = true },
813 [tegra_clk_vi] = { .dt_id = TEGRA30_CLK_VI, .present = true },
814 [tegra_clk_epp] = { .dt_id = TEGRA30_CLK_EPP, .present = true },
815 [tegra_clk_mpe] = { .dt_id = TEGRA30_CLK_MPE, .present = true },
816 [tegra_clk_host1x] = { .dt_id = TEGRA30_CLK_HOST1X, .present = true },
817 [tegra_clk_gr2d] = { .dt_id = TEGRA30_CLK_GR2D, .present = true },
818 [tegra_clk_gr3d] = { .dt_id = TEGRA30_CLK_GR3D, .present = true },
819 [tegra_clk_mselect] = { .dt_id = TEGRA30_CLK_MSELECT, .present = true },
820 [tegra_clk_nor] = { .dt_id = TEGRA30_CLK_NOR, .present = true },
821 [tegra_clk_sdmmc1] = { .dt_id = TEGRA30_CLK_SDMMC1, .present = true },
822 [tegra_clk_sdmmc2] = { .dt_id = TEGRA30_CLK_SDMMC2, .present = true },
823 [tegra_clk_sdmmc3] = { .dt_id = TEGRA30_CLK_SDMMC3, .present = true },
824 [tegra_clk_sdmmc4] = { .dt_id = TEGRA30_CLK_SDMMC4, .present = true },
825 [tegra_clk_cve] = { .dt_id = TEGRA30_CLK_CVE, .present = true },
826 [tegra_clk_tvo] = { .dt_id = TEGRA30_CLK_TVO, .present = true },
827 [tegra_clk_tvdac] = { .dt_id = TEGRA30_CLK_TVDAC, .present = true },
828 [tegra_clk_actmon] = { .dt_id = TEGRA30_CLK_ACTMON, .present = true },
829 [tegra_clk_vi_sensor] = { .dt_id = TEGRA30_CLK_VI_SENSOR, .present = true },
830 [tegra_clk_i2c1] = { .dt_id = TEGRA30_CLK_I2C1, .present = true },
831 [tegra_clk_i2c2] = { .dt_id = TEGRA30_CLK_I2C2, .present = true },
832 [tegra_clk_i2c3] = { .dt_id = TEGRA30_CLK_I2C3, .present = true },
833 [tegra_clk_i2c4] = { .dt_id = TEGRA30_CLK_I2C4, .present = true },
834 [tegra_clk_i2c5] = { .dt_id = TEGRA30_CLK_I2C5, .present = true },
835 [tegra_clk_uarta] = { .dt_id = TEGRA30_CLK_UARTA, .present = true },
836 [tegra_clk_uartb] = { .dt_id = TEGRA30_CLK_UARTB, .present = true },
837 [tegra_clk_uartc] = { .dt_id = TEGRA30_CLK_UARTC, .present = true },
838 [tegra_clk_uartd] = { .dt_id = TEGRA30_CLK_UARTD, .present = true },
839 [tegra_clk_uarte] = { .dt_id = TEGRA30_CLK_UARTE, .present = true },
840 [tegra_clk_extern1] = { .dt_id = TEGRA30_CLK_EXTERN1, .present = true },
841 [tegra_clk_extern2] = { .dt_id = TEGRA30_CLK_EXTERN2, .present = true },
842 [tegra_clk_extern3] = { .dt_id = TEGRA30_CLK_EXTERN3, .present = true },
843 [tegra_clk_disp1] = { .dt_id = TEGRA30_CLK_DISP1, .present = true },
844 [tegra_clk_disp2] = { .dt_id = TEGRA30_CLK_DISP2, .present = true },
845 [tegra_clk_apbdma] = { .dt_id = TEGRA30_CLK_APBDMA, .present = true },
846 [tegra_clk_rtc] = { .dt_id = TEGRA30_CLK_RTC, .present = true },
847 [tegra_clk_timer] = { .dt_id = TEGRA30_CLK_TIMER, .present = true },
848 [tegra_clk_kbc] = { .dt_id = TEGRA30_CLK_KBC, .present = true },
849 [tegra_clk_csus] = { .dt_id = TEGRA30_CLK_CSUS, .present = true },
850 [tegra_clk_vcp] = { .dt_id = TEGRA30_CLK_VCP, .present = true },
851 [tegra_clk_bsea] = { .dt_id = TEGRA30_CLK_BSEA, .present = true },
852 [tegra_clk_bsev] = { .dt_id = TEGRA30_CLK_BSEV, .present = true },
853 [tegra_clk_usbd] = { .dt_id = TEGRA30_CLK_USBD, .present = true },
854 [tegra_clk_usb2] = { .dt_id = TEGRA30_CLK_USB2, .present = true },
855 [tegra_clk_usb3] = { .dt_id = TEGRA30_CLK_USB3, .present = true },
856 [tegra_clk_csi] = { .dt_id = TEGRA30_CLK_CSI, .present = true },
857 [tegra_clk_isp] = { .dt_id = TEGRA30_CLK_ISP, .present = true },
858 [tegra_clk_kfuse] = { .dt_id = TEGRA30_CLK_KFUSE, .present = true },
859 [tegra_clk_fuse] = { .dt_id = TEGRA30_CLK_FUSE, .present = true },
860 [tegra_clk_fuse_burn] = { .dt_id = TEGRA30_CLK_FUSE_BURN, .present = true },
861 [tegra_clk_apbif] = { .dt_id = TEGRA30_CLK_APBIF, .present = true },
862 [tegra_clk_hda2hdmi] = { .dt_id = TEGRA30_CLK_HDA2HDMI, .present = true },
863 [tegra_clk_sata_cold] = { .dt_id = TEGRA30_CLK_SATA_COLD, .present = true },
864 [tegra_clk_sata_oob] = { .dt_id = TEGRA30_CLK_SATA_OOB, .present = true },
865 [tegra_clk_sata] = { .dt_id = TEGRA30_CLK_SATA, .present = true },
866 [tegra_clk_dtv] = { .dt_id = TEGRA30_CLK_DTV, .present = true },
867 [tegra_clk_pll_p] = { .dt_id = TEGRA30_CLK_PLL_P, .present = true },
868 [tegra_clk_pll_p_out1] = { .dt_id = TEGRA30_CLK_PLL_P_OUT1, .present = true },
869 [tegra_clk_pll_p_out2] = { .dt_id = TEGRA30_CLK_PLL_P_OUT2, .present = true },
870 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA30_CLK_PLL_P_OUT3, .present = true },
871 [tegra_clk_pll_p_out4] = { .dt_id = TEGRA30_CLK_PLL_P_OUT4, .present = true },
872 [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true },
873 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
874};
875
876static void tegra30_utmi_param_configure(void)
877{
878 unsigned int i;
879 u32 reg;
880
881 for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
882 if (input_freq == utmi_parameters[i].osc_frequency)
883 break;
884 }
885
886 if (i >= ARRAY_SIZE(utmi_parameters)) {
887 pr_err("%s: Unexpected input rate %lu\n", __func__, input_freq);
888 return;
889 }
890
891 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG2);
892
893
894 reg &= ~UTMIP_PLL_CFG2_STABLE_COUNT(~0);
895 reg |= UTMIP_PLL_CFG2_STABLE_COUNT(
896 utmi_parameters[i].stable_count);
897
898 reg &= ~UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(~0);
899
900 reg |= UTMIP_PLL_CFG2_ACTIVE_DLY_COUNT(
901 utmi_parameters[i].active_delay_count);
902
903
904 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_A_POWERDOWN;
905 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_B_POWERDOWN;
906 reg &= ~UTMIP_PLL_CFG2_FORCE_PD_SAMP_C_POWERDOWN;
907
908 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2);
909
910
911 reg = readl_relaxed(clk_base + UTMIP_PLL_CFG1);
912 reg &= ~UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(~0);
913
914 reg |= UTMIP_PLL_CFG1_ENABLE_DLY_COUNT(
915 utmi_parameters[i].enable_delay_count);
916
917 reg &= ~UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(~0);
918 reg |= UTMIP_PLL_CFG1_XTAL_FREQ_COUNT(
919 utmi_parameters[i].xtal_freq_count);
920
921
922 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ENABLE_POWERDOWN;
923 reg &= ~UTMIP_PLL_CFG1_FORCE_PLL_ACTIVE_POWERDOWN;
924 reg &= ~UTMIP_PLL_CFG1_FORCE_PLLU_POWERDOWN;
925
926 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1);
927}
928
929static const char *pll_e_parents[] = { "pll_ref", "pll_p" };
930
931static void __init tegra30_pll_init(void)
932{
933 struct clk *clk;
934
935
936 clk = tegra_clk_register_pll("pll_c", "pll_ref", clk_base, pmc_base, 0,
937 &pll_c_params, NULL);
938 clks[TEGRA30_CLK_PLL_C] = clk;
939
940
941 clk = tegra_clk_register_divider("pll_c_out1_div", "pll_c",
942 clk_base + PLLC_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
943 8, 8, 1, NULL);
944 clk = tegra_clk_register_pll_out("pll_c_out1", "pll_c_out1_div",
945 clk_base + PLLC_OUT, 1, 0, CLK_SET_RATE_PARENT,
946 0, NULL);
947 clks[TEGRA30_CLK_PLL_C_OUT1] = clk;
948
949
950 clk = tegra_clk_register_pll("pll_m", "pll_ref", clk_base, pmc_base,
951 CLK_IGNORE_UNUSED | CLK_SET_RATE_GATE,
952 &pll_m_params, NULL);
953 clks[TEGRA30_CLK_PLL_M] = clk;
954
955
956 clk = tegra_clk_register_divider("pll_m_out1_div", "pll_m",
957 clk_base + PLLM_OUT, 0, TEGRA_DIVIDER_ROUND_UP,
958 8, 8, 1, NULL);
959 clk = tegra_clk_register_pll_out("pll_m_out1", "pll_m_out1_div",
960 clk_base + PLLM_OUT, 1, 0, CLK_IGNORE_UNUSED |
961 CLK_SET_RATE_PARENT, 0, NULL);
962 clks[TEGRA30_CLK_PLL_M_OUT1] = clk;
963
964
965 clk = tegra_clk_register_pll("pll_x", "pll_ref", clk_base, pmc_base, 0,
966 &pll_x_params, NULL);
967 clks[TEGRA30_CLK_PLL_X] = clk;
968
969
970 clk = clk_register_fixed_factor(NULL, "pll_x_out0", "pll_x",
971 CLK_SET_RATE_PARENT, 1, 2);
972 clks[TEGRA30_CLK_PLL_X_OUT0] = clk;
973
974
975 clk = tegra_clk_register_pll("pll_u", "pll_ref", clk_base, pmc_base, 0,
976 &pll_u_params, NULL);
977 clks[TEGRA30_CLK_PLL_U] = clk;
978
979 tegra30_utmi_param_configure();
980
981
982 clk = tegra_clk_register_pll("pll_d", "pll_ref", clk_base, pmc_base, 0,
983 &pll_d_params, &pll_d_lock);
984 clks[TEGRA30_CLK_PLL_D] = clk;
985
986
987 clk = clk_register_fixed_factor(NULL, "pll_d_out0", "pll_d",
988 CLK_SET_RATE_PARENT, 1, 2);
989 clks[TEGRA30_CLK_PLL_D_OUT0] = clk;
990
991
992 clk = tegra_clk_register_pll("pll_d2", "pll_ref", clk_base, pmc_base, 0,
993 &pll_d2_params, NULL);
994 clks[TEGRA30_CLK_PLL_D2] = clk;
995
996
997 clk = clk_register_fixed_factor(NULL, "pll_d2_out0", "pll_d2",
998 CLK_SET_RATE_PARENT, 1, 2);
999 clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;
1000
1001
1002 clk = clk_register_mux(NULL, "pll_e_mux", pll_e_parents,
1003 ARRAY_SIZE(pll_e_parents),
1004 CLK_SET_RATE_NO_REPARENT,
1005 clk_base + PLLE_AUX, 2, 1, 0, NULL);
1006 clk = tegra_clk_register_plle("pll_e", "pll_e_mux", clk_base, pmc_base,
1007 CLK_GET_RATE_NOCACHE, &pll_e_params, NULL);
1008 clks[TEGRA30_CLK_PLL_E] = clk;
1009}
1010
1011static const char *cclk_g_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1012 "pll_p_cclkg", "pll_p_out4_cclkg",
1013 "pll_p_out3_cclkg", "unused", "pll_x" };
1014static const char *cclk_lp_parents[] = { "clk_m", "pll_c", "clk_32k", "pll_m",
1015 "pll_p_cclklp", "pll_p_out4_cclklp",
1016 "pll_p_out3_cclklp", "unused", "pll_x",
1017 "pll_x_out0" };
1018static const char *sclk_parents[] = { "clk_m", "pll_c_out1", "pll_p_out4",
1019 "pll_p_out3", "pll_p_out2", "unused",
1020 "clk_32k", "pll_m_out1" };
1021
1022static void __init tegra30_super_clk_init(void)
1023{
1024 struct clk *clk;
1025
1026
1027
1028
1029
1030 clk = tegra_clk_register_divider("pll_p_cclkg", "pll_p",
1031 clk_base + SUPER_CCLKG_DIVIDER, 0,
1032 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1033 clk_register_clkdev(clk, "pll_p_cclkg", NULL);
1034
1035
1036
1037
1038
1039 clk = tegra_clk_register_divider("pll_p_out3_cclkg", "pll_p_out3",
1040 clk_base + SUPER_CCLKG_DIVIDER, 0,
1041 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1042 clk_register_clkdev(clk, "pll_p_out3_cclkg", NULL);
1043
1044
1045
1046
1047
1048 clk = tegra_clk_register_divider("pll_p_out4_cclkg", "pll_p_out4",
1049 clk_base + SUPER_CCLKG_DIVIDER, 0,
1050 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1051 clk_register_clkdev(clk, "pll_p_out4_cclkg", NULL);
1052
1053
1054 clk = tegra_clk_register_super_mux("cclk_g", cclk_g_parents,
1055 ARRAY_SIZE(cclk_g_parents),
1056 CLK_SET_RATE_PARENT,
1057 clk_base + CCLKG_BURST_POLICY,
1058 0, 4, 0, 0, NULL);
1059 clks[TEGRA30_CLK_CCLK_G] = clk;
1060
1061
1062
1063
1064
1065 clk = tegra_clk_register_divider("pll_p_cclklp", "pll_p",
1066 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1067 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1068 clk_register_clkdev(clk, "pll_p_cclklp", NULL);
1069
1070
1071
1072
1073
1074 clk = tegra_clk_register_divider("pll_p_out3_cclklp", "pll_p_out3",
1075 clk_base + SUPER_CCLKG_DIVIDER, 0,
1076 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1077 clk_register_clkdev(clk, "pll_p_out3_cclklp", NULL);
1078
1079
1080
1081
1082
1083 clk = tegra_clk_register_divider("pll_p_out4_cclklp", "pll_p_out4",
1084 clk_base + SUPER_CCLKLP_DIVIDER, 0,
1085 TEGRA_DIVIDER_INT, 16, 8, 1, NULL);
1086 clk_register_clkdev(clk, "pll_p_out4_cclklp", NULL);
1087
1088
1089 clk = tegra_clk_register_super_mux("cclk_lp", cclk_lp_parents,
1090 ARRAY_SIZE(cclk_lp_parents),
1091 CLK_SET_RATE_PARENT,
1092 clk_base + CCLKLP_BURST_POLICY,
1093 TEGRA_DIVIDER_2, 4, 8, 9,
1094 NULL);
1095 clks[TEGRA30_CLK_CCLK_LP] = clk;
1096
1097
1098 clk = tegra_clk_register_super_mux("sclk", sclk_parents,
1099 ARRAY_SIZE(sclk_parents),
1100 CLK_SET_RATE_PARENT,
1101 clk_base + SCLK_BURST_POLICY,
1102 0, 4, 0, 0, NULL);
1103 clks[TEGRA30_CLK_SCLK] = clk;
1104
1105
1106 clk = clk_register_fixed_factor(NULL, "twd", "cclk_g",
1107 CLK_SET_RATE_PARENT, 1, 2);
1108 clks[TEGRA30_CLK_TWD] = clk;
1109
1110 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra30_clks, NULL);
1111}
1112
1113static const char *mux_pllacp_clkm[] = { "pll_a_out0", "unused", "pll_p",
1114 "clk_m" };
1115static const char *mux_pllpcm_clkm[] = { "pll_p", "pll_c", "pll_m", "clk_m" };
1116static const char *mux_pllmcp_clkm[] = { "pll_m", "pll_c", "pll_p", "clk_m" };
1117static const char *spdif_out_parents[] = { "pll_a_out0", "spdif_2x", "pll_p",
1118 "clk_m" };
1119static const char *mux_pllmcpa[] = { "pll_m", "pll_c", "pll_p", "pll_a_out0" };
1120static const char *mux_pllpmdacd2_clkm[] = { "pll_p", "pll_m", "pll_d_out0",
1121 "pll_a_out0", "pll_c",
1122 "pll_d2_out0", "clk_m" };
1123static const char *mux_plld_out0_plld2_out0[] = { "pll_d_out0",
1124 "pll_d2_out0" };
1125static const char *pwm_parents[] = { "pll_p", "pll_c", "clk_32k", "clk_m" };
1126
1127static struct tegra_periph_init_data tegra_periph_clk_list[] = {
1128 TEGRA_INIT_DATA_MUX("spdif_out", spdif_out_parents, CLK_SOURCE_SPDIF_OUT, 10, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_SPDIF_OUT),
1129 TEGRA_INIT_DATA_MUX("d_audio", mux_pllacp_clkm, CLK_SOURCE_D_AUDIO, 106, 0, TEGRA30_CLK_D_AUDIO),
1130 TEGRA_INIT_DATA_MUX("dam0", mux_pllacp_clkm, CLK_SOURCE_DAM0, 108, 0, TEGRA30_CLK_DAM0),
1131 TEGRA_INIT_DATA_MUX("dam1", mux_pllacp_clkm, CLK_SOURCE_DAM1, 109, 0, TEGRA30_CLK_DAM1),
1132 TEGRA_INIT_DATA_MUX("dam2", mux_pllacp_clkm, CLK_SOURCE_DAM2, 110, 0, TEGRA30_CLK_DAM2),
1133 TEGRA_INIT_DATA_INT("3d2", mux_pllmcpa, CLK_SOURCE_3D2, 98, TEGRA_PERIPH_MANUAL_RESET, TEGRA30_CLK_GR3D2),
1134 TEGRA_INIT_DATA_INT("se", mux_pllpcm_clkm, CLK_SOURCE_SE, 127, 0, TEGRA30_CLK_SE),
1135 TEGRA_INIT_DATA_MUX8("hdmi", mux_pllpmdacd2_clkm, CLK_SOURCE_HDMI, 51, 0, TEGRA30_CLK_HDMI),
1136 TEGRA_INIT_DATA("pwm", NULL, NULL, pwm_parents, CLK_SOURCE_PWM, 28, 2, 0, 0, 8, 1, 0, 17, TEGRA_PERIPH_ON_APB, TEGRA30_CLK_PWM),
1137};
1138
1139static struct tegra_periph_init_data tegra_periph_nodiv_clk_list[] = {
1140 TEGRA_INIT_DATA_NODIV("dsib", mux_plld_out0_plld2_out0, CLK_SOURCE_DSIB, 25, 1, 82, 0, TEGRA30_CLK_DSIB),
1141};
1142
1143static void __init tegra30_periph_clk_init(void)
1144{
1145 struct tegra_periph_init_data *data;
1146 struct clk *clk;
1147 unsigned int i;
1148
1149
1150 clk = tegra_clk_register_periph_gate("dsia", "pll_d_out0", 0, clk_base,
1151 0, 48, periph_clk_enb_refcnt);
1152 clks[TEGRA30_CLK_DSIA] = clk;
1153
1154
1155 clk = tegra_clk_register_periph_gate("pcie", "clk_m", 0, clk_base, 0,
1156 70, periph_clk_enb_refcnt);
1157 clks[TEGRA30_CLK_PCIE] = clk;
1158
1159
1160 clk = tegra_clk_register_periph_gate("afi", "clk_m", 0, clk_base, 0, 72,
1161 periph_clk_enb_refcnt);
1162 clks[TEGRA30_CLK_AFI] = clk;
1163
1164
1165 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm,
1166 ARRAY_SIZE(mux_pllmcp_clkm),
1167 CLK_SET_RATE_NO_REPARENT,
1168 clk_base + CLK_SOURCE_EMC,
1169 30, 2, 0, &emc_lock);
1170 clk = tegra_clk_register_periph_gate("emc", "emc_mux", 0, clk_base, 0,
1171 57, periph_clk_enb_refcnt);
1172 clks[TEGRA30_CLK_EMC] = clk;
1173
1174 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC,
1175 &emc_lock);
1176 clks[TEGRA30_CLK_MC] = clk;
1177
1178
1179 clk = clk_register_gate(NULL, "cml0", "pll_e", 0, clk_base + PLLE_AUX,
1180 0, 0, &cml_lock);
1181 clks[TEGRA30_CLK_CML0] = clk;
1182
1183
1184 clk = clk_register_gate(NULL, "cml1", "pll_e", 0, clk_base + PLLE_AUX,
1185 1, 0, &cml_lock);
1186 clks[TEGRA30_CLK_CML1] = clk;
1187
1188 for (i = 0; i < ARRAY_SIZE(tegra_periph_clk_list); i++) {
1189 data = &tegra_periph_clk_list[i];
1190 clk = tegra_clk_register_periph(data->name, data->p.parent_names,
1191 data->num_parents, &data->periph,
1192 clk_base, data->offset, data->flags);
1193 clks[data->clk_id] = clk;
1194 }
1195
1196 for (i = 0; i < ARRAY_SIZE(tegra_periph_nodiv_clk_list); i++) {
1197 data = &tegra_periph_nodiv_clk_list[i];
1198 clk = tegra_clk_register_periph_nodiv(data->name,
1199 data->p.parent_names,
1200 data->num_parents, &data->periph,
1201 clk_base, data->offset);
1202 clks[data->clk_id] = clk;
1203 }
1204
1205 tegra_periph_clk_init(clk_base, pmc_base, tegra30_clks, &pll_p_params);
1206}
1207
1208
1209static void tegra30_wait_cpu_in_reset(u32 cpu)
1210{
1211 unsigned int reg;
1212
1213 do {
1214 reg = readl(clk_base +
1215 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1216 cpu_relax();
1217 } while (!(reg & (1 << cpu)));
1218
1219 return;
1220}
1221
1222static void tegra30_put_cpu_in_reset(u32 cpu)
1223{
1224 writel(CPU_RESET(cpu),
1225 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
1226 dmb();
1227}
1228
1229static void tegra30_cpu_out_of_reset(u32 cpu)
1230{
1231 writel(CPU_RESET(cpu),
1232 clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
1233 wmb();
1234}
1235
1236static void tegra30_enable_cpu_clock(u32 cpu)
1237{
1238 unsigned int reg;
1239
1240 writel(CPU_CLOCK(cpu),
1241 clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1242 reg = readl(clk_base +
1243 TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
1244}
1245
1246static void tegra30_disable_cpu_clock(u32 cpu)
1247{
1248 unsigned int reg;
1249
1250 reg = readl(clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1251 writel(reg | CPU_CLOCK(cpu),
1252 clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
1253}
1254
1255#ifdef CONFIG_PM_SLEEP
1256static bool tegra30_cpu_rail_off_ready(void)
1257{
1258 unsigned int cpu_rst_status;
1259 int cpu_pwr_status;
1260
1261 cpu_rst_status = readl(clk_base +
1262 TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
1263 cpu_pwr_status = tegra_powergate_is_powered(TEGRA_POWERGATE_CPU1) ||
1264 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU2) ||
1265 tegra_powergate_is_powered(TEGRA_POWERGATE_CPU3);
1266
1267 if (((cpu_rst_status & 0xE) != 0xE) || cpu_pwr_status)
1268 return false;
1269
1270 return true;
1271}
1272
1273static void tegra30_cpu_clock_suspend(void)
1274{
1275
1276 tegra30_cpu_clk_sctx.clk_csite_src =
1277 readl(clk_base + CLK_RESET_SOURCE_CSITE);
1278 writel(3 << 30, clk_base + CLK_RESET_SOURCE_CSITE);
1279
1280 tegra30_cpu_clk_sctx.cpu_burst =
1281 readl(clk_base + CLK_RESET_CCLK_BURST);
1282 tegra30_cpu_clk_sctx.pllx_base =
1283 readl(clk_base + CLK_RESET_PLLX_BASE);
1284 tegra30_cpu_clk_sctx.pllx_misc =
1285 readl(clk_base + CLK_RESET_PLLX_MISC);
1286 tegra30_cpu_clk_sctx.cclk_divider =
1287 readl(clk_base + CLK_RESET_CCLK_DIVIDER);
1288}
1289
1290static void tegra30_cpu_clock_resume(void)
1291{
1292 unsigned int reg, policy;
1293
1294
1295 reg = readl(clk_base + CLK_RESET_CCLK_BURST);
1296 policy = (reg >> CLK_RESET_CCLK_BURST_POLICY_SHIFT) & 0xF;
1297
1298 if (policy == CLK_RESET_CCLK_IDLE_POLICY)
1299 reg = (reg >> CLK_RESET_CCLK_IDLE_POLICY_SHIFT) & 0xF;
1300 else if (policy == CLK_RESET_CCLK_RUN_POLICY)
1301 reg = (reg >> CLK_RESET_CCLK_RUN_POLICY_SHIFT) & 0xF;
1302 else
1303 BUG();
1304
1305 if (reg != CLK_RESET_CCLK_BURST_POLICY_PLLX) {
1306
1307 writel(tegra30_cpu_clk_sctx.pllx_misc,
1308 clk_base + CLK_RESET_PLLX_MISC);
1309 writel(tegra30_cpu_clk_sctx.pllx_base,
1310 clk_base + CLK_RESET_PLLX_BASE);
1311
1312
1313 if (tegra30_cpu_clk_sctx.pllx_base & (1 << 30))
1314 udelay(300);
1315 }
1316
1317
1318
1319
1320
1321 writel(tegra30_cpu_clk_sctx.cclk_divider,
1322 clk_base + CLK_RESET_CCLK_DIVIDER);
1323 writel(tegra30_cpu_clk_sctx.cpu_burst,
1324 clk_base + CLK_RESET_CCLK_BURST);
1325
1326 writel(tegra30_cpu_clk_sctx.clk_csite_src,
1327 clk_base + CLK_RESET_SOURCE_CSITE);
1328}
1329#endif
1330
1331static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
1332 .wait_for_reset = tegra30_wait_cpu_in_reset,
1333 .put_in_reset = tegra30_put_cpu_in_reset,
1334 .out_of_reset = tegra30_cpu_out_of_reset,
1335 .enable_clock = tegra30_enable_cpu_clock,
1336 .disable_clock = tegra30_disable_cpu_clock,
1337#ifdef CONFIG_PM_SLEEP
1338 .rail_off_ready = tegra30_cpu_rail_off_ready,
1339 .suspend = tegra30_cpu_clock_suspend,
1340 .resume = tegra30_cpu_clock_resume,
1341#endif
1342};
1343
1344static struct tegra_clk_init_table init_table[] __initdata = {
1345 { TEGRA30_CLK_UARTA, TEGRA30_CLK_PLL_P, 408000000, 0 },
1346 { TEGRA30_CLK_UARTB, TEGRA30_CLK_PLL_P, 408000000, 0 },
1347 { TEGRA30_CLK_UARTC, TEGRA30_CLK_PLL_P, 408000000, 0 },
1348 { TEGRA30_CLK_UARTD, TEGRA30_CLK_PLL_P, 408000000, 0 },
1349 { TEGRA30_CLK_UARTE, TEGRA30_CLK_PLL_P, 408000000, 0 },
1350 { TEGRA30_CLK_PLL_A, TEGRA30_CLK_CLK_MAX, 564480000, 1 },
1351 { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 1 },
1352 { TEGRA30_CLK_EXTERN1, TEGRA30_CLK_PLL_A_OUT0, 0, 1 },
1353 { TEGRA30_CLK_CLK_OUT_1_MUX, TEGRA30_CLK_EXTERN1, 0, 0 },
1354 { TEGRA30_CLK_CLK_OUT_1, TEGRA30_CLK_CLK_MAX, 0, 1 },
1355 { TEGRA30_CLK_BLINK, TEGRA30_CLK_CLK_MAX, 0, 1 },
1356 { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1357 { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1358 { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1359 { TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1360 { TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1361 { TEGRA30_CLK_SDMMC1, TEGRA30_CLK_PLL_P, 48000000, 0 },
1362 { TEGRA30_CLK_SDMMC2, TEGRA30_CLK_PLL_P, 48000000, 0 },
1363 { TEGRA30_CLK_SDMMC3, TEGRA30_CLK_PLL_P, 48000000, 0 },
1364 { TEGRA30_CLK_PLL_M, TEGRA30_CLK_CLK_MAX, 0, 1 },
1365 { TEGRA30_CLK_PCLK, TEGRA30_CLK_CLK_MAX, 0, 1 },
1366 { TEGRA30_CLK_CSITE, TEGRA30_CLK_CLK_MAX, 0, 1 },
1367 { TEGRA30_CLK_EMC, TEGRA30_CLK_CLK_MAX, 0, 1 },
1368 { TEGRA30_CLK_MSELECT, TEGRA30_CLK_CLK_MAX, 0, 1 },
1369 { TEGRA30_CLK_SBC1, TEGRA30_CLK_PLL_P, 100000000, 0 },
1370 { TEGRA30_CLK_SBC2, TEGRA30_CLK_PLL_P, 100000000, 0 },
1371 { TEGRA30_CLK_SBC3, TEGRA30_CLK_PLL_P, 100000000, 0 },
1372 { TEGRA30_CLK_SBC4, TEGRA30_CLK_PLL_P, 100000000, 0 },
1373 { TEGRA30_CLK_SBC5, TEGRA30_CLK_PLL_P, 100000000, 0 },
1374 { TEGRA30_CLK_SBC6, TEGRA30_CLK_PLL_P, 100000000, 0 },
1375 { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
1376 { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },
1377 { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },
1378 { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },
1379 { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1380 { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1381 { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
1382
1383 { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
1384};
1385
1386static void __init tegra30_clock_apply_init_table(void)
1387{
1388 tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
1389}
1390
1391
1392
1393
1394
1395
1396static struct tegra_clk_duplicate tegra_clk_duplicates[] = {
1397 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "utmip-pad", NULL),
1398 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-ehci.0", NULL),
1399 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_USBD, "tegra-otg", NULL),
1400 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "tegra-avp", "bsev"),
1401 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEV, "nvavp", "bsev"),
1402 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VDE, "tegra-aes", "vde"),
1403 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "tegra-aes", "bsea"),
1404 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_BSEA, "nvavp", "bsea"),
1405 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML1, "tegra_sata_cml", NULL),
1406 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CML0, "tegra_pcie", "cml"),
1407 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_VCP, "nvavp", "vcp"),
1408
1409 TEGRA_CLK_DUPLICATE(TEGRA30_CLK_CLK_MAX, NULL, NULL),
1410};
1411
1412static const struct of_device_id pmc_match[] __initconst = {
1413 { .compatible = "nvidia,tegra30-pmc" },
1414 { },
1415};
1416
1417static struct tegra_audio_clk_info tegra30_audio_plls[] = {
1418 { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" },
1419};
1420
1421static void __init tegra30_clock_init(struct device_node *np)
1422{
1423 struct device_node *node;
1424
1425 clk_base = of_iomap(np, 0);
1426 if (!clk_base) {
1427 pr_err("ioremap tegra30 CAR failed\n");
1428 return;
1429 }
1430
1431 node = of_find_matching_node(NULL, pmc_match);
1432 if (!node) {
1433 pr_err("Failed to find pmc node\n");
1434 BUG();
1435 }
1436
1437 pmc_base = of_iomap(node, 0);
1438 if (!pmc_base) {
1439 pr_err("Can't map pmc registers\n");
1440 BUG();
1441 }
1442
1443 clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,
1444 TEGRA30_CLK_PERIPH_BANKS);
1445 if (!clks)
1446 return;
1447
1448 if (tegra_osc_clk_init(clk_base, tegra30_clks, tegra30_input_freq,
1449 ARRAY_SIZE(tegra30_input_freq), 1, &input_freq,
1450 NULL) < 0)
1451 return;
1452
1453 tegra_fixed_clk_init(tegra30_clks);
1454 tegra30_pll_init();
1455 tegra30_super_clk_init();
1456 tegra30_periph_clk_init();
1457 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
1458 tegra30_audio_plls,
1459 ARRAY_SIZE(tegra30_audio_plls));
1460 tegra_pmc_clk_init(pmc_base, tegra30_clks);
1461
1462 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
1463
1464 tegra_add_of_provider(np);
1465 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1466
1467 tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
1468
1469 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1470}
1471CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
1472
