LXR linux/drivers/dma/qcom/hidma.h

   1/*
   2 * Qualcomm Technologies HIDMA data structures
   3 *
   4 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 and
   8 * only version 2 as published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 */
  15
  16#ifndef QCOM_HIDMA_H
  17#define QCOM_HIDMA_H
  18
  19#include <linux/kfifo.h>
  20#include <linux/interrupt.h>
  21#include <linux/dmaengine.h>
  22
  23#define TRE_SIZE                        32 /* each TRE is 32 bytes  */
  24#define TRE_CFG_IDX                     0
  25#define TRE_LEN_IDX                     1
  26#define TRE_SRC_LOW_IDX         2
  27#define TRE_SRC_HI_IDX                  3
  28#define TRE_DEST_LOW_IDX                4
  29#define TRE_DEST_HI_IDX         5
  30
  31struct hidma_tx_status {
  32        u8 err_info;                    /* error record in this transfer    */
  33        u8 err_code;                    /* completion code                  */
  34};
  35
  36struct hidma_tre {
  37        atomic_t allocated;             /* if this channel is allocated     */
  38        bool queued;                    /* flag whether this is pending     */
  39        u16 status;                     /* status                           */
  40        u32 chidx;                      /* index of the tre                 */
  41        u32 dma_sig;                    /* signature of the tre             */
  42        const char *dev_name;           /* name of the device               */
  43        void (*callback)(void *data);   /* requester callback               */
  44        void *data;                     /* Data associated with this channel*/
  45        struct hidma_lldev *lldev;      /* lldma device pointer             */
  46        u32 tre_local[TRE_SIZE / sizeof(u32) + 1]; /* TRE local copy        */
  47        u32 tre_index;                  /* the offset where this was written*/
  48        u32 int_flags;                  /* interrupt flags                  */
  49};
  50
  51struct hidma_lldev {
  52        bool initialized;               /* initialized flag               */
  53        u8 trch_state;                  /* trch_state of the device       */
  54        u8 evch_state;                  /* evch_state of the device       */
  55        u8 chidx;                       /* channel index in the core      */
  56        u32 nr_tres;                    /* max number of configs          */
  57        spinlock_t lock;                /* reentrancy                     */
  58        struct hidma_tre *trepool;      /* trepool of user configs */
  59        struct device *dev;             /* device                         */
  60        void __iomem *trca;             /* Transfer Channel address       */
  61        void __iomem *evca;             /* Event Channel address          */
  62        struct hidma_tre
  63                **pending_tre_list;     /* Pointers to pending TREs       */
  64        struct hidma_tx_status
  65                *tx_status_list;        /* Pointers to pending TREs status*/
  66        s32 pending_tre_count;          /* Number of TREs pending         */
  67
  68        void *tre_ring;                 /* TRE ring                       */
  69        dma_addr_t tre_ring_handle;     /* TRE ring to be shared with HW  */
  70        u32 tre_ring_size;              /* Byte size of the ring          */
  71        u32 tre_processed_off;          /* last processed TRE             */
  72
  73        void *evre_ring;                /* EVRE ring                       */
  74        dma_addr_t evre_ring_handle;    /* EVRE ring to be shared with HW  */
  75        u32 evre_ring_size;             /* Byte size of the ring           */
  76        u32 evre_processed_off;         /* last processed EVRE             */
  77
  78        u32 tre_write_offset;           /* TRE write location              */
  79        struct tasklet_struct task;     /* task delivering notifications   */
  80        DECLARE_KFIFO_PTR(handoff_fifo,
  81                struct hidma_tre *);    /* pending TREs FIFO               */
  82};
  83
  84struct hidma_desc {
  85        struct dma_async_tx_descriptor  desc;
  86        /* link list node for this channel*/
  87        struct list_head                node;
  88        u32                             tre_ch;
  89};
  90
  91struct hidma_chan {
  92        bool                            paused;
  93        bool                            allocated;
  94        char                            dbg_name[16];
  95        u32                             dma_sig;
  96
  97        /*
  98         * active descriptor on this channel
  99         * It is used by the DMA complete notification to
 100         * locate the descriptor that initiated the transfer.
 101         */
 102        struct dentry                   *debugfs;
 103        struct dentry                   *stats;
 104        struct hidma_dev                *dmadev;
 105        struct hidma_desc               *running;
 106
 107        struct dma_chan                 chan;
 108        struct list_head                free;
 109        struct list_head                prepared;
 110        struct list_head                active;
 111        struct list_head                completed;
 112
 113        /* Lock for this structure */
 114        spinlock_t                      lock;
 115};
 116
 117struct hidma_dev {
 118        int                             irq;
 119        int                             chidx;
 120        u32                             nr_descriptors;
 121
 122        struct hidma_lldev              *lldev;
 123        void                            __iomem *dev_trca;
 124        struct resource                 *trca_resource;
 125        void                            __iomem *dev_evca;
 126        struct resource                 *evca_resource;
 127
 128        /* used to protect the pending channel list*/
 129        spinlock_t                      lock;
 130        struct dma_device               ddev;
 131
 132        struct dentry                   *debugfs;
 133        struct dentry                   *stats;
 134
 135        /* Task delivering issue_pending */
 136        struct tasklet_struct           task;
 137};
 138
 139int hidma_ll_request(struct hidma_lldev *llhndl, u32 dev_id,
 140                        const char *dev_name,
 141                        void (*callback)(void *data), void *data, u32 *tre_ch);
 142
 143void hidma_ll_free(struct hidma_lldev *llhndl, u32 tre_ch);
 144enum dma_status hidma_ll_status(struct hidma_lldev *llhndl, u32 tre_ch);
 145bool hidma_ll_isenabled(struct hidma_lldev *llhndl);
 146void hidma_ll_queue_request(struct hidma_lldev *llhndl, u32 tre_ch);
 147void hidma_ll_start(struct hidma_lldev *llhndl);
 148int hidma_ll_pause(struct hidma_lldev *llhndl);
 149int hidma_ll_resume(struct hidma_lldev *llhndl);
 150void hidma_ll_set_transfer_params(struct hidma_lldev *llhndl, u32 tre_ch,
 151        dma_addr_t src, dma_addr_t dest, u32 len, u32 flags);
 152int hidma_ll_setup(struct hidma_lldev *lldev);
 153struct hidma_lldev *hidma_ll_init(struct device *dev, u32 max_channels,
 154                        void __iomem *trca, void __iomem *evca,
 155                        u8 chidx);
 156int hidma_ll_uninit(struct hidma_lldev *llhndl);
 157irqreturn_t hidma_ll_inthandler(int irq, void *arg);
 158void hidma_cleanup_pending_tre(struct hidma_lldev *llhndl, u8 err_info,
 159                                u8 err_code);
 160#endif
 161