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29#include <linux/seq_file.h>
30#include <linux/slab.h>
31#include <drm/drmP.h>
32#include <drm/amdgpu_drm.h>
33#include "amdgpu.h"
34#include "atom.h"
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45static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev);
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58int amdgpu_ib_get(struct amdgpu_device *adev, struct amdgpu_vm *vm,
59 unsigned size, struct amdgpu_ib *ib)
60{
61 int r;
62
63 if (size) {
64 r = amdgpu_sa_bo_new(&adev->ring_tmp_bo,
65 &ib->sa_bo, size, 256);
66 if (r) {
67 dev_err(adev->dev, "failed to get a new IB (%d)\n", r);
68 return r;
69 }
70
71 ib->ptr = amdgpu_sa_bo_cpu_addr(ib->sa_bo);
72
73 if (!vm)
74 ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
75 }
76
77 ib->vm = vm;
78 ib->vm_id = 0;
79
80 return 0;
81}
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91
92void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f)
93{
94 amdgpu_sa_bo_free(adev, &ib->sa_bo, f);
95}
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118int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
119 struct amdgpu_ib *ibs, struct fence *last_vm_update,
120 struct fence **f)
121{
122 struct amdgpu_device *adev = ring->adev;
123 struct amdgpu_ib *ib = &ibs[0];
124 struct amdgpu_ctx *ctx, *old_ctx;
125 struct amdgpu_vm *vm;
126 struct fence *hwf;
127 unsigned i;
128 int r = 0;
129
130 if (num_ibs == 0)
131 return -EINVAL;
132
133 ctx = ibs->ctx;
134 vm = ibs->vm;
135
136 if (!ring->ready) {
137 dev_err(adev->dev, "couldn't schedule ib\n");
138 return -EINVAL;
139 }
140
141 if (vm && !ibs->vm_id) {
142 dev_err(adev->dev, "VM IB without ID\n");
143 return -EINVAL;
144 }
145
146 r = amdgpu_ring_alloc(ring, 256 * num_ibs);
147 if (r) {
148 dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
149 return r;
150 }
151
152 if (vm) {
153
154 amdgpu_vm_flush(ring, ib->vm_id, ib->vm_pd_addr,
155 ib->gds_base, ib->gds_size,
156 ib->gws_base, ib->gws_size,
157 ib->oa_base, ib->oa_size);
158
159 if (ring->funcs->emit_hdp_flush)
160 amdgpu_ring_emit_hdp_flush(ring);
161 }
162
163 old_ctx = ring->current_ctx;
164 for (i = 0; i < num_ibs; ++i) {
165 ib = &ibs[i];
166
167 if (ib->ctx != ctx || ib->vm != vm) {
168 ring->current_ctx = old_ctx;
169 if (ib->vm_id)
170 amdgpu_vm_reset_id(adev, ib->vm_id);
171 amdgpu_ring_undo(ring);
172 return -EINVAL;
173 }
174 amdgpu_ring_emit_ib(ring, ib);
175 ring->current_ctx = ctx;
176 }
177
178 if (vm) {
179 if (ring->funcs->emit_hdp_invalidate)
180 amdgpu_ring_emit_hdp_invalidate(ring);
181 }
182
183 r = amdgpu_fence_emit(ring, &hwf);
184 if (r) {
185 dev_err(adev->dev, "failed to emit fence (%d)\n", r);
186 ring->current_ctx = old_ctx;
187 if (ib->vm_id)
188 amdgpu_vm_reset_id(adev, ib->vm_id);
189 amdgpu_ring_undo(ring);
190 return r;
191 }
192
193
194 if (ib->user) {
195 uint64_t addr = amdgpu_bo_gpu_offset(ib->user->bo);
196 addr += ib->user->offset;
197 amdgpu_ring_emit_fence(ring, addr, ib->sequence,
198 AMDGPU_FENCE_FLAG_64BIT);
199 }
200
201 if (f)
202 *f = fence_get(hwf);
203
204 amdgpu_ring_commit(ring);
205 return 0;
206}
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217int amdgpu_ib_pool_init(struct amdgpu_device *adev)
218{
219 int r;
220
221 if (adev->ib_pool_ready) {
222 return 0;
223 }
224 r = amdgpu_sa_bo_manager_init(adev, &adev->ring_tmp_bo,
225 AMDGPU_IB_POOL_SIZE*64*1024,
226 AMDGPU_GPU_PAGE_SIZE,
227 AMDGPU_GEM_DOMAIN_GTT);
228 if (r) {
229 return r;
230 }
231
232 r = amdgpu_sa_bo_manager_start(adev, &adev->ring_tmp_bo);
233 if (r) {
234 return r;
235 }
236
237 adev->ib_pool_ready = true;
238 if (amdgpu_debugfs_sa_init(adev)) {
239 dev_err(adev->dev, "failed to register debugfs file for SA\n");
240 }
241 return 0;
242}
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252void amdgpu_ib_pool_fini(struct amdgpu_device *adev)
253{
254 if (adev->ib_pool_ready) {
255 amdgpu_sa_bo_manager_suspend(adev, &adev->ring_tmp_bo);
256 amdgpu_sa_bo_manager_fini(adev, &adev->ring_tmp_bo);
257 adev->ib_pool_ready = false;
258 }
259}
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271int amdgpu_ib_ring_tests(struct amdgpu_device *adev)
272{
273 unsigned i;
274 int r;
275
276 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
277 struct amdgpu_ring *ring = adev->rings[i];
278
279 if (!ring || !ring->ready)
280 continue;
281
282 r = amdgpu_ring_test_ib(ring);
283 if (r) {
284 ring->ready = false;
285
286 if (ring == &adev->gfx.gfx_ring[0]) {
287
288 DRM_ERROR("amdgpu: failed testing IB on GFX ring (%d).\n", r);
289 adev->accel_working = false;
290 return r;
291
292 } else {
293
294 DRM_ERROR("amdgpu: failed testing IB on ring %d (%d).\n", i, r);
295 }
296 }
297 }
298 return 0;
299}
300
301
302
303
304#if defined(CONFIG_DEBUG_FS)
305
306static int amdgpu_debugfs_sa_info(struct seq_file *m, void *data)
307{
308 struct drm_info_node *node = (struct drm_info_node *) m->private;
309 struct drm_device *dev = node->minor->dev;
310 struct amdgpu_device *adev = dev->dev_private;
311
312 amdgpu_sa_bo_dump_debug_info(&adev->ring_tmp_bo, m);
313
314 return 0;
315
316}
317
318static struct drm_info_list amdgpu_debugfs_sa_list[] = {
319 {"amdgpu_sa_info", &amdgpu_debugfs_sa_info, 0, NULL},
320};
321
322#endif
323
324static int amdgpu_debugfs_sa_init(struct amdgpu_device *adev)
325{
326#if defined(CONFIG_DEBUG_FS)
327 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_sa_list, 1);
328#else
329 return 0;
330#endif
331}
332