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28#ifndef __AMDGPU_OBJECT_H__
29#define __AMDGPU_OBJECT_H__
30
31#include <drm/amdgpu_drm.h>
32#include "amdgpu.h"
33
34
35
36
37
38
39
40static inline unsigned amdgpu_mem_type_to_domain(u32 mem_type)
41{
42 switch (mem_type) {
43 case TTM_PL_VRAM:
44 return AMDGPU_GEM_DOMAIN_VRAM;
45 case TTM_PL_TT:
46 return AMDGPU_GEM_DOMAIN_GTT;
47 case TTM_PL_SYSTEM:
48 return AMDGPU_GEM_DOMAIN_CPU;
49 case AMDGPU_PL_GDS:
50 return AMDGPU_GEM_DOMAIN_GDS;
51 case AMDGPU_PL_GWS:
52 return AMDGPU_GEM_DOMAIN_GWS;
53 case AMDGPU_PL_OA:
54 return AMDGPU_GEM_DOMAIN_OA;
55 default:
56 break;
57 }
58 return 0;
59}
60
61
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63
64
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66
67
68
69
70static inline int amdgpu_bo_reserve(struct amdgpu_bo *bo, bool no_intr)
71{
72 int r;
73
74 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, false, 0);
75 if (unlikely(r != 0)) {
76 if (r != -ERESTARTSYS)
77 dev_err(bo->adev->dev, "%p reserve failed\n", bo);
78 return r;
79 }
80 return 0;
81}
82
83static inline void amdgpu_bo_unreserve(struct amdgpu_bo *bo)
84{
85 ttm_bo_unreserve(&bo->tbo);
86}
87
88
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94
95
96
97static inline u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
98{
99 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
100 return bo->tbo.offset;
101}
102
103static inline unsigned long amdgpu_bo_size(struct amdgpu_bo *bo)
104{
105 return bo->tbo.num_pages << PAGE_SHIFT;
106}
107
108static inline unsigned amdgpu_bo_ngpu_pages(struct amdgpu_bo *bo)
109{
110 return (bo->tbo.num_pages << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
111}
112
113static inline unsigned amdgpu_bo_gpu_page_alignment(struct amdgpu_bo *bo)
114{
115 return (bo->tbo.mem.page_alignment << PAGE_SHIFT) / AMDGPU_GPU_PAGE_SIZE;
116}
117
118
119
120
121
122
123
124static inline u64 amdgpu_bo_mmap_offset(struct amdgpu_bo *bo)
125{
126 return drm_vma_node_offset_addr(&bo->tbo.vma_node);
127}
128
129int amdgpu_bo_create(struct amdgpu_device *adev,
130 unsigned long size, int byte_align,
131 bool kernel, u32 domain, u64 flags,
132 struct sg_table *sg,
133 struct reservation_object *resv,
134 struct amdgpu_bo **bo_ptr);
135int amdgpu_bo_create_restricted(struct amdgpu_device *adev,
136 unsigned long size, int byte_align,
137 bool kernel, u32 domain, u64 flags,
138 struct sg_table *sg,
139 struct ttm_placement *placement,
140 struct reservation_object *resv,
141 struct amdgpu_bo **bo_ptr);
142int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr);
143void amdgpu_bo_kunmap(struct amdgpu_bo *bo);
144struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo);
145void amdgpu_bo_unref(struct amdgpu_bo **bo);
146int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr);
147int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
148 u64 min_offset, u64 max_offset,
149 u64 *gpu_addr);
150int amdgpu_bo_unpin(struct amdgpu_bo *bo);
151int amdgpu_bo_evict_vram(struct amdgpu_device *adev);
152int amdgpu_bo_init(struct amdgpu_device *adev);
153void amdgpu_bo_fini(struct amdgpu_device *adev);
154int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
155 struct vm_area_struct *vma);
156int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags);
157void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags);
158int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
159 uint32_t metadata_size, uint64_t flags);
160int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
161 size_t buffer_size, uint32_t *metadata_size,
162 uint64_t *flags);
163void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
164 struct ttm_mem_reg *new_mem);
165int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
166void amdgpu_bo_fence(struct amdgpu_bo *bo, struct fence *fence,
167 bool shared);
168
169
170
171
172
173static inline uint64_t amdgpu_sa_bo_gpu_addr(struct amdgpu_sa_bo *sa_bo)
174{
175 return sa_bo->manager->gpu_addr + sa_bo->soffset;
176}
177
178static inline void * amdgpu_sa_bo_cpu_addr(struct amdgpu_sa_bo *sa_bo)
179{
180 return sa_bo->manager->cpu_ptr + sa_bo->soffset;
181}
182
183int amdgpu_sa_bo_manager_init(struct amdgpu_device *adev,
184 struct amdgpu_sa_manager *sa_manager,
185 unsigned size, u32 align, u32 domain);
186void amdgpu_sa_bo_manager_fini(struct amdgpu_device *adev,
187 struct amdgpu_sa_manager *sa_manager);
188int amdgpu_sa_bo_manager_start(struct amdgpu_device *adev,
189 struct amdgpu_sa_manager *sa_manager);
190int amdgpu_sa_bo_manager_suspend(struct amdgpu_device *adev,
191 struct amdgpu_sa_manager *sa_manager);
192int amdgpu_sa_bo_new(struct amdgpu_sa_manager *sa_manager,
193 struct amdgpu_sa_bo **sa_bo,
194 unsigned size, unsigned align);
195void amdgpu_sa_bo_free(struct amdgpu_device *adev,
196 struct amdgpu_sa_bo **sa_bo,
197 struct fence *fence);
198#if defined(CONFIG_DEBUG_FS)
199void amdgpu_sa_bo_dump_debug_info(struct amdgpu_sa_manager *sa_manager,
200 struct seq_file *m);
201#endif
202
203
204#endif
205