LXR linux/drivers/gpu/drm/amd/powerplay/inc/amd

   1/*
   2 * Copyright 2015 Advanced Micro Devices, Inc.
   3 *
   4 * Permission is hereby granted, free of charge, to any person obtaining a
   5 * copy of this software and associated documentation files (the "Software"),
   6 * to deal in the Software without restriction, including without limitation
   7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8 * and/or sell copies of the Software, and to permit persons to whom the
   9 * Software is furnished to do so, subject to the following conditions:
  10 *
  11 * The above copyright notice and this permission notice shall be included in
  12 * all copies or substantial portions of the Software.
  13 *
  14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20 * OTHER DEALINGS IN THE SOFTWARE.
  21 *
  22 */
  23#ifndef _AMD_POWERPLAY_H_
  24#define _AMD_POWERPLAY_H_
  25
  26#include <linux/seq_file.h>
  27#include <linux/types.h>
  28#include <linux/errno.h>
  29#include "amd_shared.h"
  30#include "cgs_common.h"
  31
  32
  33enum amd_pp_event {
  34        AMD_PP_EVENT_INITIALIZE = 0,
  35        AMD_PP_EVENT_UNINITIALIZE,
  36        AMD_PP_EVENT_POWER_SOURCE_CHANGE,
  37        AMD_PP_EVENT_SUSPEND,
  38        AMD_PP_EVENT_RESUME,
  39        AMD_PP_EVENT_ENTER_REST_STATE,
  40        AMD_PP_EVENT_EXIT_REST_STATE,
  41        AMD_PP_EVENT_DISPLAY_CONFIG_CHANGE,
  42        AMD_PP_EVENT_THERMAL_NOTIFICATION,
  43        AMD_PP_EVENT_VBIOS_NOTIFICATION,
  44        AMD_PP_EVENT_ENTER_THERMAL_STATE,
  45        AMD_PP_EVENT_EXIT_THERMAL_STATE,
  46        AMD_PP_EVENT_ENTER_FORCED_STATE,
  47        AMD_PP_EVENT_EXIT_FORCED_STATE,
  48        AMD_PP_EVENT_ENTER_EXCLUSIVE_MODE,
  49        AMD_PP_EVENT_EXIT_EXCLUSIVE_MODE,
  50        AMD_PP_EVENT_ENTER_SCREEN_SAVER,
  51        AMD_PP_EVENT_EXIT_SCREEN_SAVER,
  52        AMD_PP_EVENT_VPU_RECOVERY_BEGIN,
  53        AMD_PP_EVENT_VPU_RECOVERY_END,
  54        AMD_PP_EVENT_ENABLE_POWER_PLAY,
  55        AMD_PP_EVENT_DISABLE_POWER_PLAY,
  56        AMD_PP_EVENT_CHANGE_POWER_SOURCE_UI_LABEL,
  57        AMD_PP_EVENT_ENABLE_USER2D_PERFORMANCE,
  58        AMD_PP_EVENT_DISABLE_USER2D_PERFORMANCE,
  59        AMD_PP_EVENT_ENABLE_USER3D_PERFORMANCE,
  60        AMD_PP_EVENT_DISABLE_USER3D_PERFORMANCE,
  61        AMD_PP_EVENT_ENABLE_OVER_DRIVE_TEST,
  62        AMD_PP_EVENT_DISABLE_OVER_DRIVE_TEST,
  63        AMD_PP_EVENT_ENABLE_REDUCED_REFRESH_RATE,
  64        AMD_PP_EVENT_DISABLE_REDUCED_REFRESH_RATE,
  65        AMD_PP_EVENT_ENABLE_GFX_CLOCK_GATING,
  66        AMD_PP_EVENT_DISABLE_GFX_CLOCK_GATING,
  67        AMD_PP_EVENT_ENABLE_CGPG,
  68        AMD_PP_EVENT_DISABLE_CGPG,
  69        AMD_PP_EVENT_ENTER_TEXT_MODE,
  70        AMD_PP_EVENT_EXIT_TEXT_MODE,
  71        AMD_PP_EVENT_VIDEO_START,
  72        AMD_PP_EVENT_VIDEO_STOP,
  73        AMD_PP_EVENT_ENABLE_USER_STATE,
  74        AMD_PP_EVENT_DISABLE_USER_STATE,
  75        AMD_PP_EVENT_READJUST_POWER_STATE,
  76        AMD_PP_EVENT_START_INACTIVITY,
  77        AMD_PP_EVENT_STOP_INACTIVITY,
  78        AMD_PP_EVENT_LINKED_ADAPTERS_READY,
  79        AMD_PP_EVENT_ADAPTER_SAFE_TO_DISABLE,
  80        AMD_PP_EVENT_COMPLETE_INIT,
  81        AMD_PP_EVENT_CRITICAL_THERMAL_FAULT,
  82        AMD_PP_EVENT_BACKLIGHT_CHANGED,
  83        AMD_PP_EVENT_ENABLE_VARI_BRIGHT,
  84        AMD_PP_EVENT_DISABLE_VARI_BRIGHT,
  85        AMD_PP_EVENT_ENABLE_VARI_BRIGHT_ON_POWER_XPRESS,
  86        AMD_PP_EVENT_DISABLE_VARI_BRIGHT_ON_POWER_XPRESS,
  87        AMD_PP_EVENT_SET_VARI_BRIGHT_LEVEL,
  88        AMD_PP_EVENT_VARI_BRIGHT_MONITOR_MEASUREMENT,
  89        AMD_PP_EVENT_SCREEN_ON,
  90        AMD_PP_EVENT_SCREEN_OFF,
  91        AMD_PP_EVENT_PRE_DISPLAY_CONFIG_CHANGE,
  92        AMD_PP_EVENT_ENTER_ULP_STATE,
  93        AMD_PP_EVENT_EXIT_ULP_STATE,
  94        AMD_PP_EVENT_REGISTER_IP_STATE,
  95        AMD_PP_EVENT_UNREGISTER_IP_STATE,
  96        AMD_PP_EVENT_ENTER_MGPU_MODE,
  97        AMD_PP_EVENT_EXIT_MGPU_MODE,
  98        AMD_PP_EVENT_ENTER_MULTI_GPU_MODE,
  99        AMD_PP_EVENT_PRE_SUSPEND,
 100        AMD_PP_EVENT_PRE_RESUME,
 101        AMD_PP_EVENT_ENTER_BACOS,
 102        AMD_PP_EVENT_EXIT_BACOS,
 103        AMD_PP_EVENT_RESUME_BACO,
 104        AMD_PP_EVENT_RESET_BACO,
 105        AMD_PP_EVENT_PRE_DISPLAY_PHY_ACCESS,
 106        AMD_PP_EVENT_POST_DISPLAY_PHY_CCESS,
 107        AMD_PP_EVENT_START_COMPUTE_APPLICATION,
 108        AMD_PP_EVENT_STOP_COMPUTE_APPLICATION,
 109        AMD_PP_EVENT_REDUCE_POWER_LIMIT,
 110        AMD_PP_EVENT_ENTER_FRAME_LOCK,
 111        AMD_PP_EVENT_EXIT_FRAME_LOOCK,
 112        AMD_PP_EVENT_LONG_IDLE_REQUEST_BACO,
 113        AMD_PP_EVENT_LONG_IDLE_ENTER_BACO,
 114        AMD_PP_EVENT_LONG_IDLE_EXIT_BACO,
 115        AMD_PP_EVENT_HIBERNATE,
 116        AMD_PP_EVENT_CONNECTED_STANDBY,
 117        AMD_PP_EVENT_ENTER_SELF_REFRESH,
 118        AMD_PP_EVENT_EXIT_SELF_REFRESH,
 119        AMD_PP_EVENT_START_AVFS_BTC,
 120        AMD_PP_EVENT_MAX
 121};
 122
 123enum amd_dpm_forced_level {
 124        AMD_DPM_FORCED_LEVEL_AUTO = 0,
 125        AMD_DPM_FORCED_LEVEL_LOW = 1,
 126        AMD_DPM_FORCED_LEVEL_HIGH = 2,
 127        AMD_DPM_FORCED_LEVEL_MANUAL = 3,
 128};
 129
 130struct amd_pp_init {
 131        struct cgs_device *device;
 132        uint32_t chip_family;
 133        uint32_t chip_id;
 134        uint32_t rev_id;
 135};
 136enum amd_pp_display_config_type{
 137        AMD_PP_DisplayConfigType_None = 0,
 138        AMD_PP_DisplayConfigType_DP54 ,
 139        AMD_PP_DisplayConfigType_DP432 ,
 140        AMD_PP_DisplayConfigType_DP324 ,
 141        AMD_PP_DisplayConfigType_DP27,
 142        AMD_PP_DisplayConfigType_DP243,
 143        AMD_PP_DisplayConfigType_DP216,
 144        AMD_PP_DisplayConfigType_DP162,
 145        AMD_PP_DisplayConfigType_HDMI6G ,
 146        AMD_PP_DisplayConfigType_HDMI297 ,
 147        AMD_PP_DisplayConfigType_HDMI162,
 148        AMD_PP_DisplayConfigType_LVDS,
 149        AMD_PP_DisplayConfigType_DVI,
 150        AMD_PP_DisplayConfigType_WIRELESS,
 151        AMD_PP_DisplayConfigType_VGA
 152};
 153
 154struct single_display_configuration
 155{
 156        uint32_t controller_index;
 157        uint32_t controller_id;
 158        uint32_t signal_type;
 159        uint32_t display_state;
 160        /* phy id for the primary internal transmitter */
 161        uint8_t primary_transmitter_phyi_d;
 162        /* bitmap with the active lanes */
 163        uint8_t primary_transmitter_active_lanemap;
 164        /* phy id for the secondary internal transmitter (for dual-link dvi) */
 165        uint8_t secondary_transmitter_phy_id;
 166        /* bitmap with the active lanes */
 167        uint8_t secondary_transmitter_active_lanemap;
 168        /* misc phy settings for SMU. */
 169        uint32_t config_flags;
 170        uint32_t display_type;
 171        uint32_t view_resolution_cx;
 172        uint32_t view_resolution_cy;
 173        enum amd_pp_display_config_type displayconfigtype;
 174        uint32_t vertical_refresh; /* for active display */
 175};
 176
 177#define MAX_NUM_DISPLAY 32
 178
 179struct amd_pp_display_configuration {
 180        bool nb_pstate_switch_disable;/* controls NB PState switch */
 181        bool cpu_cc6_disable; /* controls CPU CState switch ( on or off) */
 182        bool cpu_pstate_disable;
 183        uint32_t cpu_pstate_separation_time;
 184
 185        uint32_t num_display;  /* total number of display*/
 186        uint32_t num_path_including_non_display;
 187        uint32_t crossfire_display_index;
 188        uint32_t min_mem_set_clock;
 189        uint32_t min_core_set_clock;
 190        /* unit 10KHz x bit*/
 191        uint32_t min_bus_bandwidth;
 192        /* minimum required stutter sclk, in 10khz uint32_t ulMinCoreSetClk;*/
 193        uint32_t min_core_set_clock_in_sr;
 194
 195        struct single_display_configuration displays[MAX_NUM_DISPLAY];
 196
 197        uint32_t vrefresh; /* for active display*/
 198
 199        uint32_t min_vblank_time; /* for active display*/
 200        bool multi_monitor_in_sync;
 201        /* Controller Index of primary display - used in MCLK SMC switching hang
 202         * SW Workaround*/
 203        uint32_t crtc_index;
 204        /* htotal*1000/pixelclk - used in MCLK SMC switching hang SW Workaround*/
 205        uint32_t line_time_in_us;
 206        bool invalid_vblank_time;
 207
 208        uint32_t display_clk;
 209        /*
 210         * for given display configuration if multimonitormnsync == false then
 211         * Memory clock DPMS with this latency or below is allowed, DPMS with
 212         * higher latency not allowed.
 213         */
 214        uint32_t dce_tolerable_mclk_in_active_latency;
 215};
 216
 217struct amd_pp_simple_clock_info {
 218        uint32_t        engine_max_clock;
 219        uint32_t        memory_max_clock;
 220        uint32_t        level;
 221};
 222
 223enum PP_DAL_POWERLEVEL {
 224        PP_DAL_POWERLEVEL_INVALID = 0,
 225        PP_DAL_POWERLEVEL_ULTRALOW,
 226        PP_DAL_POWERLEVEL_LOW,
 227        PP_DAL_POWERLEVEL_NOMINAL,
 228        PP_DAL_POWERLEVEL_PERFORMANCE,
 229
 230        PP_DAL_POWERLEVEL_0 = PP_DAL_POWERLEVEL_ULTRALOW,
 231        PP_DAL_POWERLEVEL_1 = PP_DAL_POWERLEVEL_LOW,
 232        PP_DAL_POWERLEVEL_2 = PP_DAL_POWERLEVEL_NOMINAL,
 233        PP_DAL_POWERLEVEL_3 = PP_DAL_POWERLEVEL_PERFORMANCE,
 234        PP_DAL_POWERLEVEL_4 = PP_DAL_POWERLEVEL_3+1,
 235        PP_DAL_POWERLEVEL_5 = PP_DAL_POWERLEVEL_4+1,
 236        PP_DAL_POWERLEVEL_6 = PP_DAL_POWERLEVEL_5+1,
 237        PP_DAL_POWERLEVEL_7 = PP_DAL_POWERLEVEL_6+1,
 238};
 239
 240struct amd_pp_clock_info {
 241        uint32_t min_engine_clock;
 242        uint32_t max_engine_clock;
 243        uint32_t min_memory_clock;
 244        uint32_t max_memory_clock;
 245        uint32_t min_bus_bandwidth;
 246        uint32_t max_bus_bandwidth;
 247        uint32_t max_engine_clock_in_sr;
 248        uint32_t min_engine_clock_in_sr;
 249        enum PP_DAL_POWERLEVEL max_clocks_state;
 250};
 251
 252enum amd_pp_clock_type {
 253        amd_pp_disp_clock = 1,
 254        amd_pp_sys_clock,
 255        amd_pp_mem_clock
 256};
 257
 258#define MAX_NUM_CLOCKS 16
 259
 260struct amd_pp_clocks {
 261        uint32_t count;
 262        uint32_t clock[MAX_NUM_CLOCKS];
 263};
 264
 265
 266enum {
 267        PP_GROUP_UNKNOWN = 0,
 268        PP_GROUP_GFX = 1,
 269        PP_GROUP_SYS,
 270        PP_GROUP_MAX
 271};
 272
 273enum pp_clock_type {
 274        PP_SCLK,
 275        PP_MCLK,
 276        PP_PCIE,
 277};
 278
 279struct pp_states_info {
 280        uint32_t nums;
 281        uint32_t states[16];
 282};
 283
 284#define PP_GROUP_MASK        0xF0000000
 285#define PP_GROUP_SHIFT       28
 286
 287#define PP_BLOCK_MASK        0x0FFFFF00
 288#define PP_BLOCK_SHIFT       8
 289
 290#define PP_BLOCK_GFX_CG         0x01
 291#define PP_BLOCK_GFX_MG         0x02
 292#define PP_BLOCK_SYS_BIF        0x01
 293#define PP_BLOCK_SYS_MC         0x02
 294#define PP_BLOCK_SYS_ROM        0x04
 295#define PP_BLOCK_SYS_DRM        0x08
 296#define PP_BLOCK_SYS_HDP        0x10
 297#define PP_BLOCK_SYS_SDMA       0x20
 298
 299#define PP_STATE_MASK           0x0000000F
 300#define PP_STATE_SHIFT          0
 301#define PP_STATE_SUPPORT_MASK   0x000000F0
 302#define PP_STATE_SUPPORT_SHIFT  0
 303
 304#define PP_STATE_CG             0x01
 305#define PP_STATE_LS             0x02
 306#define PP_STATE_DS             0x04
 307#define PP_STATE_SD             0x08
 308#define PP_STATE_SUPPORT_CG     0x10
 309#define PP_STATE_SUPPORT_LS     0x20
 310#define PP_STATE_SUPPORT_DS     0x40
 311#define PP_STATE_SUPPORT_SD     0x80
 312
 313#define PP_CG_MSG_ID(group, block, support, state) (group << PP_GROUP_SHIFT |\
 314                                                                block << PP_BLOCK_SHIFT |\
 315                                                                support << PP_STATE_SUPPORT_SHIFT |\
 316                                                                state << PP_STATE_SHIFT)
 317
 318struct amd_powerplay_funcs {
 319        int (*get_temperature)(void *handle);
 320        int (*load_firmware)(void *handle);
 321        int (*wait_for_fw_loading_complete)(void *handle);
 322        int (*force_performance_level)(void *handle, enum amd_dpm_forced_level level);
 323        enum amd_dpm_forced_level (*get_performance_level)(void *handle);
 324        enum amd_pm_state_type (*get_current_power_state)(void *handle);
 325        int (*get_sclk)(void *handle, bool low);
 326        int (*get_mclk)(void *handle, bool low);
 327        int (*powergate_vce)(void *handle, bool gate);
 328        int (*powergate_uvd)(void *handle, bool gate);
 329        int (*dispatch_tasks)(void *handle, enum amd_pp_event event_id,
 330                                   void *input, void *output);
 331        void (*print_current_performance_level)(void *handle,
 332                                                      struct seq_file *m);
 333        int (*set_fan_control_mode)(void *handle, uint32_t mode);
 334        int (*get_fan_control_mode)(void *handle);
 335        int (*set_fan_speed_percent)(void *handle, uint32_t percent);
 336        int (*get_fan_speed_percent)(void *handle, uint32_t *speed);
 337        int (*get_pp_num_states)(void *handle, struct pp_states_info *data);
 338        int (*get_pp_table)(void *handle, char **table);
 339        int (*set_pp_table)(void *handle, const char *buf, size_t size);
 340        int (*force_clock_level)(void *handle, enum pp_clock_type type, int level);
 341        int (*print_clock_levels)(void *handle, enum pp_clock_type type, char *buf);
 342};
 343
 344struct amd_powerplay {
 345        void *pp_handle;
 346        const struct amd_ip_funcs *ip_funcs;
 347        const struct amd_powerplay_funcs *pp_funcs;
 348};
 349
 350int amd_powerplay_init(struct amd_pp_init *pp_init,
 351                       struct amd_powerplay *amd_pp);
 352
 353int amd_powerplay_fini(void *handle);
 354
 355int amd_powerplay_display_configuration_change(void *handle,
 356                const struct amd_pp_display_configuration *input);
 357
 358int amd_powerplay_get_display_power_level(void *handle,
 359                struct amd_pp_simple_clock_info *output);
 360
 361int amd_powerplay_get_current_clocks(void *handle,
 362                struct amd_pp_clock_info *output);
 363
 364int amd_powerplay_get_clock_by_type(void *handle,
 365                enum amd_pp_clock_type type,
 366                struct amd_pp_clocks *clocks);
 367
 368int amd_powerplay_get_display_mode_validation_clocks(void *handle,
 369                struct amd_pp_simple_clock_info *output);
 370
 371#endif /* _AMD_POWERPLAY_H_ */
 372