1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#ifndef _HARDWARE_MANAGER_H_
24#define _HARDWARE_MANAGER_H_
25
26
27
28struct pp_hwmgr;
29struct pp_hw_power_state;
30struct pp_power_state;
31enum amd_dpm_forced_level;
32struct PP_TemperatureRange;
33
34
35struct phm_fan_speed_info {
36 uint32_t min_percent;
37 uint32_t max_percent;
38 uint32_t min_rpm;
39 uint32_t max_rpm;
40 bool supports_percent_read;
41 bool supports_percent_write;
42 bool supports_rpm_read;
43 bool supports_rpm_write;
44};
45
46
47enum PHM_AutoThrottleSource
48{
49 PHM_AutoThrottleSource_Thermal,
50 PHM_AutoThrottleSource_External
51};
52
53typedef enum PHM_AutoThrottleSource PHM_AutoThrottleSource;
54
55enum phm_platform_caps {
56 PHM_PlatformCaps_AtomBiosPpV1 = 0,
57 PHM_PlatformCaps_PowerPlaySupport,
58 PHM_PlatformCaps_ACOverdriveSupport,
59 PHM_PlatformCaps_BacklightSupport,
60 PHM_PlatformCaps_ThermalController,
61 PHM_PlatformCaps_BiosPowerSourceControl,
62 PHM_PlatformCaps_DisableVoltageTransition,
63 PHM_PlatformCaps_DisableEngineTransition,
64 PHM_PlatformCaps_DisableMemoryTransition,
65 PHM_PlatformCaps_DynamicPowerManagement,
66 PHM_PlatformCaps_EnableASPML0s,
67 PHM_PlatformCaps_EnableASPML1,
68 PHM_PlatformCaps_OD5inACSupport,
69 PHM_PlatformCaps_OD5inDCSupport,
70 PHM_PlatformCaps_SoftStateOD5,
71 PHM_PlatformCaps_NoOD5Support,
72 PHM_PlatformCaps_ContinuousHardwarePerformanceRange,
73 PHM_PlatformCaps_ActivityReporting,
74 PHM_PlatformCaps_EnableBackbias,
75 PHM_PlatformCaps_OverdriveDisabledByPowerBudget,
76 PHM_PlatformCaps_ShowPowerBudgetWarning,
77 PHM_PlatformCaps_PowerBudgetWaiverAvailable,
78 PHM_PlatformCaps_GFXClockGatingSupport,
79 PHM_PlatformCaps_MMClockGatingSupport,
80 PHM_PlatformCaps_AutomaticDCTransition,
81 PHM_PlatformCaps_GeminiPrimary,
82 PHM_PlatformCaps_MemorySpreadSpectrumSupport,
83 PHM_PlatformCaps_EngineSpreadSpectrumSupport,
84 PHM_PlatformCaps_StepVddc,
85 PHM_PlatformCaps_DynamicPCIEGen2Support,
86 PHM_PlatformCaps_SMC,
87 PHM_PlatformCaps_FaultyInternalThermalReading,
88 PHM_PlatformCaps_EnableVoltageControl,
89 PHM_PlatformCaps_EnableSideportControl,
90 PHM_PlatformCaps_VideoPlaybackEEUNotification,
91 PHM_PlatformCaps_TurnOffPll_ASPML1,
92 PHM_PlatformCaps_EnableHTLinkControl,
93 PHM_PlatformCaps_PerformanceStateOnly,
94 PHM_PlatformCaps_ExclusiveModeAlwaysHigh,
95 PHM_PlatformCaps_DisableMGClockGating,
96 PHM_PlatformCaps_DisableMGCGTSSM,
97 PHM_PlatformCaps_UVDAlwaysHigh,
98 PHM_PlatformCaps_DisablePowerGating,
99 PHM_PlatformCaps_CustomThermalPolicy,
100 PHM_PlatformCaps_StayInBootState,
101 PHM_PlatformCaps_SMCAllowSeparateSWThermalState,
102 PHM_PlatformCaps_MultiUVDStateSupport,
103 PHM_PlatformCaps_EnableSCLKDeepSleepForUVD,
104 PHM_PlatformCaps_EnableMCUHTLinkControl,
105 PHM_PlatformCaps_ABM,
106 PHM_PlatformCaps_KongThermalPolicy,
107 PHM_PlatformCaps_SwitchVDDNB,
108 PHM_PlatformCaps_ULPS,
109 PHM_PlatformCaps_NativeULPS,
110 PHM_PlatformCaps_EnableMVDDControl,
111 PHM_PlatformCaps_ControlVDDCI,
112 PHM_PlatformCaps_DisableDCODT,
113 PHM_PlatformCaps_DynamicACTiming,
114 PHM_PlatformCaps_EnableThermalIntByGPIO,
115 PHM_PlatformCaps_BootStateOnAlert,
116 PHM_PlatformCaps_DontWaitForVBlankOnAlert,
117 PHM_PlatformCaps_Force3DClockSupport,
118 PHM_PlatformCaps_MicrocodeFanControl,
119 PHM_PlatformCaps_AdjustUVDPriorityForSP,
120 PHM_PlatformCaps_DisableLightSleep,
121 PHM_PlatformCaps_DisableMCLS,
122 PHM_PlatformCaps_RegulatorHot,
123 PHM_PlatformCaps_BACO,
124 PHM_PlatformCaps_DisableDPM,
125 PHM_PlatformCaps_DynamicM3Arbiter,
126 PHM_PlatformCaps_SclkDeepSleep,
127 PHM_PlatformCaps_DynamicPatchPowerState,
128 PHM_PlatformCaps_ThermalAutoThrottling,
129 PHM_PlatformCaps_SumoThermalPolicy,
130 PHM_PlatformCaps_PCIEPerformanceRequest,
131 PHM_PlatformCaps_BLControlledByGPU,
132 PHM_PlatformCaps_PowerContainment,
133 PHM_PlatformCaps_SQRamping,
134 PHM_PlatformCaps_CAC,
135 PHM_PlatformCaps_NIChipsets,
136 PHM_PlatformCaps_TrinityChipsets,
137 PHM_PlatformCaps_EvergreenChipsets,
138 PHM_PlatformCaps_PowerControl,
139 PHM_PlatformCaps_DisableLSClockGating,
140 PHM_PlatformCaps_BoostState,
141 PHM_PlatformCaps_UserMaxClockForMultiDisplays,
142 PHM_PlatformCaps_RegWriteDelay,
143 PHM_PlatformCaps_NonABMSupportInPPLib,
144 PHM_PlatformCaps_GFXDynamicMGPowerGating,
145 PHM_PlatformCaps_DisableSMUUVDHandshake,
146 PHM_PlatformCaps_DTE,
147 PHM_PlatformCaps_W5100Specifc_SmuSkipMsgDTE,
148 PHM_PlatformCaps_UVDPowerGating,
149 PHM_PlatformCaps_UVDDynamicPowerGating,
150 PHM_PlatformCaps_VCEPowerGating,
151 PHM_PlatformCaps_SamuPowerGating,
152 PHM_PlatformCaps_UVDDPM,
153 PHM_PlatformCaps_VCEDPM,
154 PHM_PlatformCaps_SamuDPM,
155 PHM_PlatformCaps_AcpDPM,
156 PHM_PlatformCaps_SclkDeepSleepAboveLow,
157 PHM_PlatformCaps_DynamicUVDState,
158 PHM_PlatformCaps_WantSAMClkWithDummyBackEnd,
159 PHM_PlatformCaps_WantUVDClkWithDummyBackEnd,
160 PHM_PlatformCaps_WantVCEClkWithDummyBackEnd,
161 PHM_PlatformCaps_WantACPClkWithDummyBackEnd,
162 PHM_PlatformCaps_OD6inACSupport,
163 PHM_PlatformCaps_OD6inDCSupport,
164 PHM_PlatformCaps_EnablePlatformPowerManagement,
165 PHM_PlatformCaps_SurpriseRemoval,
166 PHM_PlatformCaps_NewCACVoltage,
167 PHM_PlatformCaps_DBRamping,
168 PHM_PlatformCaps_TDRamping,
169 PHM_PlatformCaps_TCPRamping,
170 PHM_PlatformCaps_EnableSMU7ThermalManagement,
171 PHM_PlatformCaps_FPS,
172 PHM_PlatformCaps_ACP,
173 PHM_PlatformCaps_SclkThrottleLowNotification,
174 PHM_PlatformCaps_XDMAEnabled,
175 PHM_PlatformCaps_UseDummyBackEnd,
176 PHM_PlatformCaps_EnableDFSBypass,
177 PHM_PlatformCaps_VddNBDirectRequest,
178 PHM_PlatformCaps_PauseMMSessions,
179 PHM_PlatformCaps_UnTabledHardwareInterface,
180 PHM_PlatformCaps_SMU7,
181 PHM_PlatformCaps_RevertGPIO5Polarity,
182 PHM_PlatformCaps_Thermal2GPIO17,
183 PHM_PlatformCaps_ThermalOutGPIO,
184 PHM_PlatformCaps_DisableMclkSwitchingForFrameLock,
185 PHM_PlatformCaps_VRHotGPIOConfigurable,
186 PHM_PlatformCaps_TempInversion,
187 PHM_PlatformCaps_IOIC3,
188 PHM_PlatformCaps_ConnectedStandby,
189 PHM_PlatformCaps_EVV,
190 PHM_PlatformCaps_EnableLongIdleBACOSupport,
191 PHM_PlatformCaps_CombinePCCWithThermalSignal,
192 PHM_PlatformCaps_DisableUsingActualTemperatureForPowerCalc,
193 PHM_PlatformCaps_StablePState,
194 PHM_PlatformCaps_OD6PlusinACSupport,
195 PHM_PlatformCaps_OD6PlusinDCSupport,
196 PHM_PlatformCaps_ODThermalLimitUnlock,
197 PHM_PlatformCaps_ReducePowerLimit,
198 PHM_PlatformCaps_ODFuzzyFanControlSupport,
199 PHM_PlatformCaps_GeminiRegulatorFanControlSupport,
200 PHM_PlatformCaps_ControlVDDGFX,
201 PHM_PlatformCaps_BBBSupported,
202 PHM_PlatformCaps_DisableVoltageIsland,
203 PHM_PlatformCaps_FanSpeedInTableIsRPM,
204 PHM_PlatformCaps_GFXClockGatingManagedInCAIL,
205 PHM_PlatformCaps_IcelandULPSSWWorkAround,
206 PHM_PlatformCaps_FPSEnhancement,
207 PHM_PlatformCaps_LoadPostProductionFirmware,
208 PHM_PlatformCaps_VpuRecoveryInProgress,
209 PHM_PlatformCaps_Falcon_QuickTransition,
210 PHM_PlatformCaps_AVFS,
211 PHM_PlatformCaps_ClockStretcher,
212 PHM_PlatformCaps_TablelessHardwareInterface,
213 PHM_PlatformCaps_EnableDriverEVV,
214 PHM_PlatformCaps_Max
215};
216
217#define PHM_MAX_NUM_CAPS_BITS_PER_FIELD (sizeof(uint32_t)*8)
218
219
220#define PHM_MAX_NUM_CAPS_ULONG_ENTRIES \
221 ((PHM_PlatformCaps_Max + ((PHM_MAX_NUM_CAPS_BITS_PER_FIELD) - 1)) / (PHM_MAX_NUM_CAPS_BITS_PER_FIELD))
222
223struct pp_hw_descriptor {
224 uint32_t hw_caps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
225};
226
227enum PHM_PerformanceLevelDesignation {
228 PHM_PerformanceLevelDesignation_Activity,
229 PHM_PerformanceLevelDesignation_PowerContainment
230};
231
232typedef enum PHM_PerformanceLevelDesignation PHM_PerformanceLevelDesignation;
233
234struct PHM_PerformanceLevel {
235 uint32_t coreClock;
236 uint32_t memory_clock;
237 uint32_t vddc;
238 uint32_t vddci;
239 uint32_t nonLocalMemoryFreq;
240 uint32_t nonLocalMemoryWidth;
241};
242
243typedef struct PHM_PerformanceLevel PHM_PerformanceLevel;
244
245
246static inline void phm_cap_set(uint32_t *caps,
247 enum phm_platform_caps c)
248{
249 caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] |= (1UL <<
250 (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
251}
252
253static inline void phm_cap_unset(uint32_t *caps,
254 enum phm_platform_caps c)
255{
256 caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &= ~(1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)));
257}
258
259static inline bool phm_cap_enabled(const uint32_t *caps, enum phm_platform_caps c)
260{
261 return (0 != (caps[c / PHM_MAX_NUM_CAPS_BITS_PER_FIELD] &
262 (1UL << (c & (PHM_MAX_NUM_CAPS_BITS_PER_FIELD - 1)))));
263}
264
265#define PP_PCIEGenInvalid 0xffff
266enum PP_PCIEGen {
267 PP_PCIEGen1 = 0,
268 PP_PCIEGen2,
269 PP_PCIEGen3
270};
271
272typedef enum PP_PCIEGen PP_PCIEGen;
273
274#define PP_Min_PCIEGen PP_PCIEGen1
275#define PP_Max_PCIEGen PP_PCIEGen3
276#define PP_Min_PCIELane 1
277#define PP_Max_PCIELane 32
278
279enum phm_clock_Type {
280 PHM_DispClock = 1,
281 PHM_SClock,
282 PHM_MemClock
283};
284
285#define MAX_NUM_CLOCKS 16
286
287struct PP_Clocks {
288 uint32_t engineClock;
289 uint32_t memoryClock;
290 uint32_t BusBandwidth;
291 uint32_t engineClockInSR;
292};
293
294struct pp_clock_info {
295 uint32_t min_mem_clk;
296 uint32_t max_mem_clk;
297 uint32_t min_eng_clk;
298 uint32_t max_eng_clk;
299 uint32_t min_bus_bandwidth;
300 uint32_t max_bus_bandwidth;
301};
302
303struct phm_platform_descriptor {
304 uint32_t platformCaps[PHM_MAX_NUM_CAPS_ULONG_ENTRIES];
305 uint32_t vbiosInterruptId;
306 struct PP_Clocks overdriveLimit;
307 struct PP_Clocks clockStep;
308 uint32_t hardwareActivityPerformanceLevels;
309 uint32_t minimumClocksReductionPercentage;
310 uint32_t minOverdriveVDDC;
311 uint32_t maxOverdriveVDDC;
312 uint32_t overdriveVDDCStep;
313 uint32_t hardwarePerformanceLevels;
314 uint16_t powerBudget;
315 uint32_t TDPLimit;
316 uint32_t nearTDPLimit;
317 uint32_t nearTDPLimitAdjusted;
318 uint32_t SQRampingThreshold;
319 uint32_t CACLeakage;
320 uint16_t TDPODLimit;
321 uint32_t TDPAdjustment;
322 bool TDPAdjustmentPolarity;
323 uint16_t LoadLineSlope;
324 uint32_t VidMinLimit;
325 uint32_t VidMaxLimit;
326 uint32_t VidStep;
327 uint32_t VidAdjustment;
328 bool VidAdjustmentPolarity;
329};
330
331struct phm_clocks {
332 uint32_t num_of_entries;
333 uint32_t clock[MAX_NUM_CLOCKS];
334};
335
336extern int phm_enable_clock_power_gatings(struct pp_hwmgr *hwmgr);
337extern int phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool gate);
338extern int phm_powergate_vce(struct pp_hwmgr *hwmgr, bool gate);
339extern int phm_powerdown_uvd(struct pp_hwmgr *hwmgr);
340extern int phm_setup_asic(struct pp_hwmgr *hwmgr);
341extern int phm_enable_dynamic_state_management(struct pp_hwmgr *hwmgr);
342extern void phm_init_dynamic_caps(struct pp_hwmgr *hwmgr);
343extern bool phm_is_hw_access_blocked(struct pp_hwmgr *hwmgr);
344extern int phm_block_hw_access(struct pp_hwmgr *hwmgr, bool block);
345extern int phm_set_power_state(struct pp_hwmgr *hwmgr,
346 const struct pp_hw_power_state *pcurrent_state,
347 const struct pp_hw_power_state *pnew_power_state);
348
349extern int phm_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
350 struct pp_power_state *adjusted_ps,
351 const struct pp_power_state *current_ps);
352
353extern int phm_force_dpm_levels(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level);
354extern int phm_display_configuration_changed(struct pp_hwmgr *hwmgr);
355extern int phm_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr);
356extern int phm_register_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *info);
357extern int phm_start_thermal_controller(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *temperature_range);
358extern int phm_stop_thermal_controller(struct pp_hwmgr *hwmgr);
359extern bool phm_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr);
360
361extern int phm_check_states_equal(struct pp_hwmgr *hwmgr,
362 const struct pp_hw_power_state *pstate1,
363 const struct pp_hw_power_state *pstate2,
364 bool *equal);
365
366extern int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
367 const struct amd_pp_display_configuration *display_config);
368
369extern int phm_get_dal_power_level(struct pp_hwmgr *hwmgr,
370 struct amd_pp_simple_clock_info *info);
371
372extern int phm_set_cpu_power_state(struct pp_hwmgr *hwmgr);
373
374extern int phm_power_down_asic(struct pp_hwmgr *hwmgr);
375
376extern int phm_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
377 PHM_PerformanceLevelDesignation designation, uint32_t index,
378 PHM_PerformanceLevel *level);
379
380extern int phm_get_clock_info(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
381 struct pp_clock_info *pclock_info,
382 PHM_PerformanceLevelDesignation designation);
383
384extern int phm_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state, struct pp_clock_info *clock_info);
385
386extern int phm_get_clock_by_type(struct pp_hwmgr *hwmgr, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks);
387
388extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
389
390#endif
391
392