linux/drivers/gpu/drm/drm_dp_helper.c
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   1/*
   2 * Copyright © 2009 Keith Packard
   3 *
   4 * Permission to use, copy, modify, distribute, and sell this software and its
   5 * documentation for any purpose is hereby granted without fee, provided that
   6 * the above copyright notice appear in all copies and that both that copyright
   7 * notice and this permission notice appear in supporting documentation, and
   8 * that the name of the copyright holders not be used in advertising or
   9 * publicity pertaining to distribution of the software without specific,
  10 * written prior permission.  The copyright holders make no representations
  11 * about the suitability of this software for any purpose.  It is provided "as
  12 * is" without express or implied warranty.
  13 *
  14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
  15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
  16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
  17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
  18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
  20 * OF THIS SOFTWARE.
  21 */
  22
  23#include <linux/kernel.h>
  24#include <linux/module.h>
  25#include <linux/delay.h>
  26#include <linux/init.h>
  27#include <linux/errno.h>
  28#include <linux/sched.h>
  29#include <linux/i2c.h>
  30#include <drm/drm_dp_helper.h>
  31#include <drm/drm_dp_aux_dev.h>
  32#include <drm/drmP.h>
  33
  34/**
  35 * DOC: dp helpers
  36 *
  37 * These functions contain some common logic and helpers at various abstraction
  38 * levels to deal with Display Port sink devices and related things like DP aux
  39 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
  40 * blocks, ...
  41 */
  42
  43/* Helpers for DP link training */
  44static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
  45{
  46        return link_status[r - DP_LANE0_1_STATUS];
  47}
  48
  49static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
  50                             int lane)
  51{
  52        int i = DP_LANE0_1_STATUS + (lane >> 1);
  53        int s = (lane & 1) * 4;
  54        u8 l = dp_link_status(link_status, i);
  55        return (l >> s) & 0xf;
  56}
  57
  58bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  59                          int lane_count)
  60{
  61        u8 lane_align;
  62        u8 lane_status;
  63        int lane;
  64
  65        lane_align = dp_link_status(link_status,
  66                                    DP_LANE_ALIGN_STATUS_UPDATED);
  67        if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
  68                return false;
  69        for (lane = 0; lane < lane_count; lane++) {
  70                lane_status = dp_get_lane_status(link_status, lane);
  71                if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
  72                        return false;
  73        }
  74        return true;
  75}
  76EXPORT_SYMBOL(drm_dp_channel_eq_ok);
  77
  78bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
  79                              int lane_count)
  80{
  81        int lane;
  82        u8 lane_status;
  83
  84        for (lane = 0; lane < lane_count; lane++) {
  85                lane_status = dp_get_lane_status(link_status, lane);
  86                if ((lane_status & DP_LANE_CR_DONE) == 0)
  87                        return false;
  88        }
  89        return true;
  90}
  91EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
  92
  93u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
  94                                     int lane)
  95{
  96        int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
  97        int s = ((lane & 1) ?
  98                 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
  99                 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
 100        u8 l = dp_link_status(link_status, i);
 101
 102        return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
 103}
 104EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
 105
 106u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
 107                                          int lane)
 108{
 109        int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
 110        int s = ((lane & 1) ?
 111                 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
 112                 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
 113        u8 l = dp_link_status(link_status, i);
 114
 115        return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
 116}
 117EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
 118
 119void drm_dp_link_train_clock_recovery_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
 120        if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
 121                udelay(100);
 122        else
 123                mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
 124}
 125EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
 126
 127void drm_dp_link_train_channel_eq_delay(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) {
 128        if (dpcd[DP_TRAINING_AUX_RD_INTERVAL] == 0)
 129                udelay(400);
 130        else
 131                mdelay(dpcd[DP_TRAINING_AUX_RD_INTERVAL] * 4);
 132}
 133EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
 134
 135u8 drm_dp_link_rate_to_bw_code(int link_rate)
 136{
 137        switch (link_rate) {
 138        case 162000:
 139        default:
 140                return DP_LINK_BW_1_62;
 141        case 270000:
 142                return DP_LINK_BW_2_7;
 143        case 540000:
 144                return DP_LINK_BW_5_4;
 145        }
 146}
 147EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
 148
 149int drm_dp_bw_code_to_link_rate(u8 link_bw)
 150{
 151        switch (link_bw) {
 152        case DP_LINK_BW_1_62:
 153        default:
 154                return 162000;
 155        case DP_LINK_BW_2_7:
 156                return 270000;
 157        case DP_LINK_BW_5_4:
 158                return 540000;
 159        }
 160}
 161EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
 162
 163#define AUX_RETRY_INTERVAL 500 /* us */
 164
 165/**
 166 * DOC: dp helpers
 167 *
 168 * The DisplayPort AUX channel is an abstraction to allow generic, driver-
 169 * independent access to AUX functionality. Drivers can take advantage of
 170 * this by filling in the fields of the drm_dp_aux structure.
 171 *
 172 * Transactions are described using a hardware-independent drm_dp_aux_msg
 173 * structure, which is passed into a driver's .transfer() implementation.
 174 * Both native and I2C-over-AUX transactions are supported.
 175 */
 176
 177static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
 178                              unsigned int offset, void *buffer, size_t size)
 179{
 180        struct drm_dp_aux_msg msg;
 181        unsigned int retry;
 182        int err = 0;
 183
 184        memset(&msg, 0, sizeof(msg));
 185        msg.address = offset;
 186        msg.request = request;
 187        msg.buffer = buffer;
 188        msg.size = size;
 189
 190        mutex_lock(&aux->hw_mutex);
 191
 192        /*
 193         * The specification doesn't give any recommendation on how often to
 194         * retry native transactions. We used to retry 7 times like for
 195         * aux i2c transactions but real world devices this wasn't
 196         * sufficient, bump to 32 which makes Dell 4k monitors happier.
 197         */
 198        for (retry = 0; retry < 32; retry++) {
 199
 200                err = aux->transfer(aux, &msg);
 201                if (err < 0) {
 202                        if (err == -EBUSY)
 203                                continue;
 204
 205                        goto unlock;
 206                }
 207
 208
 209                switch (msg.reply & DP_AUX_NATIVE_REPLY_MASK) {
 210                case DP_AUX_NATIVE_REPLY_ACK:
 211                        if (err < size)
 212                                err = -EPROTO;
 213                        goto unlock;
 214
 215                case DP_AUX_NATIVE_REPLY_NACK:
 216                        err = -EIO;
 217                        goto unlock;
 218
 219                case DP_AUX_NATIVE_REPLY_DEFER:
 220                        usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
 221                        break;
 222                }
 223        }
 224
 225        DRM_DEBUG_KMS("too many retries, giving up\n");
 226        err = -EIO;
 227
 228unlock:
 229        mutex_unlock(&aux->hw_mutex);
 230        return err;
 231}
 232
 233/**
 234 * drm_dp_dpcd_read() - read a series of bytes from the DPCD
 235 * @aux: DisplayPort AUX channel
 236 * @offset: address of the (first) register to read
 237 * @buffer: buffer to store the register values
 238 * @size: number of bytes in @buffer
 239 *
 240 * Returns the number of bytes transferred on success, or a negative error
 241 * code on failure. -EIO is returned if the request was NAKed by the sink or
 242 * if the retry count was exceeded. If not all bytes were transferred, this
 243 * function returns -EPROTO. Errors from the underlying AUX channel transfer
 244 * function, with the exception of -EBUSY (which causes the transaction to
 245 * be retried), are propagated to the caller.
 246 */
 247ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
 248                         void *buffer, size_t size)
 249{
 250        return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, buffer,
 251                                  size);
 252}
 253EXPORT_SYMBOL(drm_dp_dpcd_read);
 254
 255/**
 256 * drm_dp_dpcd_write() - write a series of bytes to the DPCD
 257 * @aux: DisplayPort AUX channel
 258 * @offset: address of the (first) register to write
 259 * @buffer: buffer containing the values to write
 260 * @size: number of bytes in @buffer
 261 *
 262 * Returns the number of bytes transferred on success, or a negative error
 263 * code on failure. -EIO is returned if the request was NAKed by the sink or
 264 * if the retry count was exceeded. If not all bytes were transferred, this
 265 * function returns -EPROTO. Errors from the underlying AUX channel transfer
 266 * function, with the exception of -EBUSY (which causes the transaction to
 267 * be retried), are propagated to the caller.
 268 */
 269ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
 270                          void *buffer, size_t size)
 271{
 272        return drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer,
 273                                  size);
 274}
 275EXPORT_SYMBOL(drm_dp_dpcd_write);
 276
 277/**
 278 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
 279 * @aux: DisplayPort AUX channel
 280 * @status: buffer to store the link status in (must be at least 6 bytes)
 281 *
 282 * Returns the number of bytes transferred on success or a negative error
 283 * code on failure.
 284 */
 285int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
 286                                 u8 status[DP_LINK_STATUS_SIZE])
 287{
 288        return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
 289                                DP_LINK_STATUS_SIZE);
 290}
 291EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
 292
 293/**
 294 * drm_dp_link_probe() - probe a DisplayPort link for capabilities
 295 * @aux: DisplayPort AUX channel
 296 * @link: pointer to structure in which to return link capabilities
 297 *
 298 * The structure filled in by this function can usually be passed directly
 299 * into drm_dp_link_power_up() and drm_dp_link_configure() to power up and
 300 * configure the link based on the link's capabilities.
 301 *
 302 * Returns 0 on success or a negative error code on failure.
 303 */
 304int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
 305{
 306        u8 values[3];
 307        int err;
 308
 309        memset(link, 0, sizeof(*link));
 310
 311        err = drm_dp_dpcd_read(aux, DP_DPCD_REV, values, sizeof(values));
 312        if (err < 0)
 313                return err;
 314
 315        link->revision = values[0];
 316        link->rate = drm_dp_bw_code_to_link_rate(values[1]);
 317        link->num_lanes = values[2] & DP_MAX_LANE_COUNT_MASK;
 318
 319        if (values[2] & DP_ENHANCED_FRAME_CAP)
 320                link->capabilities |= DP_LINK_CAP_ENHANCED_FRAMING;
 321
 322        return 0;
 323}
 324EXPORT_SYMBOL(drm_dp_link_probe);
 325
 326/**
 327 * drm_dp_link_power_up() - power up a DisplayPort link
 328 * @aux: DisplayPort AUX channel
 329 * @link: pointer to a structure containing the link configuration
 330 *
 331 * Returns 0 on success or a negative error code on failure.
 332 */
 333int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link)
 334{
 335        u8 value;
 336        int err;
 337
 338        /* DP_SET_POWER register is only available on DPCD v1.1 and later */
 339        if (link->revision < 0x11)
 340                return 0;
 341
 342        err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
 343        if (err < 0)
 344                return err;
 345
 346        value &= ~DP_SET_POWER_MASK;
 347        value |= DP_SET_POWER_D0;
 348
 349        err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
 350        if (err < 0)
 351                return err;
 352
 353        /*
 354         * According to the DP 1.1 specification, a "Sink Device must exit the
 355         * power saving state within 1 ms" (Section 2.5.3.1, Table 5-52, "Sink
 356         * Control Field" (register 0x600).
 357         */
 358        usleep_range(1000, 2000);
 359
 360        return 0;
 361}
 362EXPORT_SYMBOL(drm_dp_link_power_up);
 363
 364/**
 365 * drm_dp_link_power_down() - power down a DisplayPort link
 366 * @aux: DisplayPort AUX channel
 367 * @link: pointer to a structure containing the link configuration
 368 *
 369 * Returns 0 on success or a negative error code on failure.
 370 */
 371int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link)
 372{
 373        u8 value;
 374        int err;
 375
 376        /* DP_SET_POWER register is only available on DPCD v1.1 and later */
 377        if (link->revision < 0x11)
 378                return 0;
 379
 380        err = drm_dp_dpcd_readb(aux, DP_SET_POWER, &value);
 381        if (err < 0)
 382                return err;
 383
 384        value &= ~DP_SET_POWER_MASK;
 385        value |= DP_SET_POWER_D3;
 386
 387        err = drm_dp_dpcd_writeb(aux, DP_SET_POWER, value);
 388        if (err < 0)
 389                return err;
 390
 391        return 0;
 392}
 393EXPORT_SYMBOL(drm_dp_link_power_down);
 394
 395/**
 396 * drm_dp_link_configure() - configure a DisplayPort link
 397 * @aux: DisplayPort AUX channel
 398 * @link: pointer to a structure containing the link configuration
 399 *
 400 * Returns 0 on success or a negative error code on failure.
 401 */
 402int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link)
 403{
 404        u8 values[2];
 405        int err;
 406
 407        values[0] = drm_dp_link_rate_to_bw_code(link->rate);
 408        values[1] = link->num_lanes;
 409
 410        if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
 411                values[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 412
 413        err = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, values, sizeof(values));
 414        if (err < 0)
 415                return err;
 416
 417        return 0;
 418}
 419EXPORT_SYMBOL(drm_dp_link_configure);
 420
 421/*
 422 * I2C-over-AUX implementation
 423 */
 424
 425static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
 426{
 427        return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
 428               I2C_FUNC_SMBUS_READ_BLOCK_DATA |
 429               I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
 430               I2C_FUNC_10BIT_ADDR;
 431}
 432
 433static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
 434{
 435        /*
 436         * In case of i2c defer or short i2c ack reply to a write,
 437         * we need to switch to WRITE_STATUS_UPDATE to drain the
 438         * rest of the message
 439         */
 440        if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
 441                msg->request &= DP_AUX_I2C_MOT;
 442                msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
 443        }
 444}
 445
 446#define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
 447#define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
 448#define AUX_STOP_LEN 4
 449#define AUX_CMD_LEN 4
 450#define AUX_ADDRESS_LEN 20
 451#define AUX_REPLY_PAD_LEN 4
 452#define AUX_LENGTH_LEN 8
 453
 454/*
 455 * Calculate the duration of the AUX request/reply in usec. Gives the
 456 * "best" case estimate, ie. successful while as short as possible.
 457 */
 458static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
 459{
 460        int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
 461                AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
 462
 463        if ((msg->request & DP_AUX_I2C_READ) == 0)
 464                len += msg->size * 8;
 465
 466        return len;
 467}
 468
 469static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
 470{
 471        int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
 472                AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
 473
 474        /*
 475         * For read we expect what was asked. For writes there will
 476         * be 0 or 1 data bytes. Assume 0 for the "best" case.
 477         */
 478        if (msg->request & DP_AUX_I2C_READ)
 479                len += msg->size * 8;
 480
 481        return len;
 482}
 483
 484#define I2C_START_LEN 1
 485#define I2C_STOP_LEN 1
 486#define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
 487#define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
 488
 489/*
 490 * Calculate the length of the i2c transfer in usec, assuming
 491 * the i2c bus speed is as specified. Gives the the "worst"
 492 * case estimate, ie. successful while as long as possible.
 493 * Doesn't account the the "MOT" bit, and instead assumes each
 494 * message includes a START, ADDRESS and STOP. Neither does it
 495 * account for additional random variables such as clock stretching.
 496 */
 497static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
 498                                   int i2c_speed_khz)
 499{
 500        /* AUX bitrate is 1MHz, i2c bitrate as specified */
 501        return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
 502                             msg->size * I2C_DATA_LEN +
 503                             I2C_STOP_LEN) * 1000, i2c_speed_khz);
 504}
 505
 506/*
 507 * Deterine how many retries should be attempted to successfully transfer
 508 * the specified message, based on the estimated durations of the
 509 * i2c and AUX transfers.
 510 */
 511static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
 512                              int i2c_speed_khz)
 513{
 514        int aux_time_us = drm_dp_aux_req_duration(msg) +
 515                drm_dp_aux_reply_duration(msg);
 516        int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
 517
 518        return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
 519}
 520
 521/*
 522 * FIXME currently assumes 10 kHz as some real world devices seem
 523 * to require it. We should query/set the speed via DPCD if supported.
 524 */
 525static int dp_aux_i2c_speed_khz __read_mostly = 10;
 526module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
 527MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
 528                 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
 529
 530/*
 531 * Transfer a single I2C-over-AUX message and handle various error conditions,
 532 * retrying the transaction as appropriate.  It is assumed that the
 533 * aux->transfer function does not modify anything in the msg other than the
 534 * reply field.
 535 *
 536 * Returns bytes transferred on success, or a negative error code on failure.
 537 */
 538static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 539{
 540        unsigned int retry, defer_i2c;
 541        int ret;
 542        /*
 543         * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
 544         * is required to retry at least seven times upon receiving AUX_DEFER
 545         * before giving up the AUX transaction.
 546         *
 547         * We also try to account for the i2c bus speed.
 548         */
 549        int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
 550
 551        for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
 552                ret = aux->transfer(aux, msg);
 553                if (ret < 0) {
 554                        if (ret == -EBUSY)
 555                                continue;
 556
 557                        DRM_DEBUG_KMS("transaction failed: %d\n", ret);
 558                        return ret;
 559                }
 560
 561
 562                switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
 563                case DP_AUX_NATIVE_REPLY_ACK:
 564                        /*
 565                         * For I2C-over-AUX transactions this isn't enough, we
 566                         * need to check for the I2C ACK reply.
 567                         */
 568                        break;
 569
 570                case DP_AUX_NATIVE_REPLY_NACK:
 571                        DRM_DEBUG_KMS("native nack (result=%d, size=%zu)\n", ret, msg->size);
 572                        return -EREMOTEIO;
 573
 574                case DP_AUX_NATIVE_REPLY_DEFER:
 575                        DRM_DEBUG_KMS("native defer\n");
 576                        /*
 577                         * We could check for I2C bit rate capabilities and if
 578                         * available adjust this interval. We could also be
 579                         * more careful with DP-to-legacy adapters where a
 580                         * long legacy cable may force very low I2C bit rates.
 581                         *
 582                         * For now just defer for long enough to hopefully be
 583                         * safe for all use-cases.
 584                         */
 585                        usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
 586                        continue;
 587
 588                default:
 589                        DRM_ERROR("invalid native reply %#04x\n", msg->reply);
 590                        return -EREMOTEIO;
 591                }
 592
 593                switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
 594                case DP_AUX_I2C_REPLY_ACK:
 595                        /*
 596                         * Both native ACK and I2C ACK replies received. We
 597                         * can assume the transfer was successful.
 598                         */
 599                        if (ret != msg->size)
 600                                drm_dp_i2c_msg_write_status_update(msg);
 601                        return ret;
 602
 603                case DP_AUX_I2C_REPLY_NACK:
 604                        DRM_DEBUG_KMS("I2C nack (result=%d, size=%zu\n", ret, msg->size);
 605                        aux->i2c_nack_count++;
 606                        return -EREMOTEIO;
 607
 608                case DP_AUX_I2C_REPLY_DEFER:
 609                        DRM_DEBUG_KMS("I2C defer\n");
 610                        /* DP Compliance Test 4.2.2.5 Requirement:
 611                         * Must have at least 7 retries for I2C defers on the
 612                         * transaction to pass this test
 613                         */
 614                        aux->i2c_defer_count++;
 615                        if (defer_i2c < 7)
 616                                defer_i2c++;
 617                        usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
 618                        drm_dp_i2c_msg_write_status_update(msg);
 619
 620                        continue;
 621
 622                default:
 623                        DRM_ERROR("invalid I2C reply %#04x\n", msg->reply);
 624                        return -EREMOTEIO;
 625                }
 626        }
 627
 628        DRM_DEBUG_KMS("too many retries, giving up\n");
 629        return -EREMOTEIO;
 630}
 631
 632static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
 633                                       const struct i2c_msg *i2c_msg)
 634{
 635        msg->request = (i2c_msg->flags & I2C_M_RD) ?
 636                DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
 637        msg->request |= DP_AUX_I2C_MOT;
 638}
 639
 640/*
 641 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
 642 *
 643 * Returns an error code on failure, or a recommended transfer size on success.
 644 */
 645static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
 646{
 647        int err, ret = orig_msg->size;
 648        struct drm_dp_aux_msg msg = *orig_msg;
 649
 650        while (msg.size > 0) {
 651                err = drm_dp_i2c_do_msg(aux, &msg);
 652                if (err <= 0)
 653                        return err == 0 ? -EPROTO : err;
 654
 655                if (err < msg.size && err < ret) {
 656                        DRM_DEBUG_KMS("Partial I2C reply: requested %zu bytes got %d bytes\n",
 657                                      msg.size, err);
 658                        ret = err;
 659                }
 660
 661                msg.size -= err;
 662                msg.buffer += err;
 663        }
 664
 665        return ret;
 666}
 667
 668/*
 669 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
 670 * packets to be as large as possible. If not, the I2C transactions never
 671 * succeed. Hence the default is maximum.
 672 */
 673static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
 674module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
 675MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
 676                 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
 677
 678static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
 679                           int num)
 680{
 681        struct drm_dp_aux *aux = adapter->algo_data;
 682        unsigned int i, j;
 683        unsigned transfer_size;
 684        struct drm_dp_aux_msg msg;
 685        int err = 0;
 686
 687        dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
 688
 689        memset(&msg, 0, sizeof(msg));
 690
 691        mutex_lock(&aux->hw_mutex);
 692
 693        for (i = 0; i < num; i++) {
 694                msg.address = msgs[i].addr;
 695                drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
 696                /* Send a bare address packet to start the transaction.
 697                 * Zero sized messages specify an address only (bare
 698                 * address) transaction.
 699                 */
 700                msg.buffer = NULL;
 701                msg.size = 0;
 702                err = drm_dp_i2c_do_msg(aux, &msg);
 703
 704                /*
 705                 * Reset msg.request in case in case it got
 706                 * changed into a WRITE_STATUS_UPDATE.
 707                 */
 708                drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
 709
 710                if (err < 0)
 711                        break;
 712                /* We want each transaction to be as large as possible, but
 713                 * we'll go to smaller sizes if the hardware gives us a
 714                 * short reply.
 715                 */
 716                transfer_size = dp_aux_i2c_transfer_size;
 717                for (j = 0; j < msgs[i].len; j += msg.size) {
 718                        msg.buffer = msgs[i].buf + j;
 719                        msg.size = min(transfer_size, msgs[i].len - j);
 720
 721                        err = drm_dp_i2c_drain_msg(aux, &msg);
 722
 723                        /*
 724                         * Reset msg.request in case in case it got
 725                         * changed into a WRITE_STATUS_UPDATE.
 726                         */
 727                        drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
 728
 729                        if (err < 0)
 730                                break;
 731                        transfer_size = err;
 732                }
 733                if (err < 0)
 734                        break;
 735        }
 736        if (err >= 0)
 737                err = num;
 738        /* Send a bare address packet to close out the transaction.
 739         * Zero sized messages specify an address only (bare
 740         * address) transaction.
 741         */
 742        msg.request &= ~DP_AUX_I2C_MOT;
 743        msg.buffer = NULL;
 744        msg.size = 0;
 745        (void)drm_dp_i2c_do_msg(aux, &msg);
 746
 747        mutex_unlock(&aux->hw_mutex);
 748
 749        return err;
 750}
 751
 752static const struct i2c_algorithm drm_dp_i2c_algo = {
 753        .functionality = drm_dp_i2c_functionality,
 754        .master_xfer = drm_dp_i2c_xfer,
 755};
 756
 757/**
 758 * drm_dp_aux_register() - initialise and register aux channel
 759 * @aux: DisplayPort AUX channel
 760 *
 761 * Returns 0 on success or a negative error code on failure.
 762 */
 763int drm_dp_aux_register(struct drm_dp_aux *aux)
 764{
 765        int ret;
 766
 767        mutex_init(&aux->hw_mutex);
 768
 769        aux->ddc.algo = &drm_dp_i2c_algo;
 770        aux->ddc.algo_data = aux;
 771        aux->ddc.retries = 3;
 772
 773        aux->ddc.class = I2C_CLASS_DDC;
 774        aux->ddc.owner = THIS_MODULE;
 775        aux->ddc.dev.parent = aux->dev;
 776        aux->ddc.dev.of_node = aux->dev->of_node;
 777
 778        strlcpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
 779                sizeof(aux->ddc.name));
 780
 781        ret = drm_dp_aux_register_devnode(aux);
 782        if (ret)
 783                return ret;
 784
 785        ret = i2c_add_adapter(&aux->ddc);
 786        if (ret) {
 787                drm_dp_aux_unregister_devnode(aux);
 788                return ret;
 789        }
 790
 791        return 0;
 792}
 793EXPORT_SYMBOL(drm_dp_aux_register);
 794
 795/**
 796 * drm_dp_aux_unregister() - unregister an AUX adapter
 797 * @aux: DisplayPort AUX channel
 798 */
 799void drm_dp_aux_unregister(struct drm_dp_aux *aux)
 800{
 801        drm_dp_aux_unregister_devnode(aux);
 802        i2c_del_adapter(&aux->ddc);
 803}
 804EXPORT_SYMBOL(drm_dp_aux_unregister);
 805