/*
 * Copyright © 2008 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
 * IN THE SOFTWARE.
 *
 * Authors:
 *    Keith Packard <keithp@keithp.com>
 *
 */

#include <linux/i2c.h>
#include <linux/slab.h>
#include <linux/export.h>
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <drm/drmP.h>
#include <drm/drm_atomic_helper.h>
#include <drm/drm_crtc.h>
#include <drm/drm_crtc_helper.h>
#include <drm/drm_edid.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"

#define DP_LINK_CHECK_TIMEOUT   (10 * 1000)

/* Compliance test status bits  */
#define INTEL_DP_RESOLUTION_SHIFT_MASK  0
#define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
#define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)

struct dp_link_dpll {
        int clock;
        struct dpll dpll;
};

static const struct dp_link_dpll gen4_dpll[] = {
        { 162000,
                { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
        { 270000,
                { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
};

static const struct dp_link_dpll pch_dpll[] = {
        { 162000,
                { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
        { 270000,
                { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
};

static const struct dp_link_dpll vlv_dpll[] = {
        { 162000,
                { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
        { 270000,
                { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
};

/*
 * CHV supports eDP 1.4 that have  more link rates.
 * Below only provides the fixed rate but exclude variable rate.
 */
static const struct dp_link_dpll chv_dpll[] = {
        /*
         * CHV requires to program fractional division for m2.
         * m2 is stored in fixed point format using formula below
         * (m2_int << 22) | m2_fraction
         */
        { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
                { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
        { 270000,       /* m2_int = 27, m2_fraction = 0 */
                { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
        { 540000,       /* m2_int = 27, m2_fraction = 0 */
                { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
};

static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
                                  324000, 432000, 540000 };
static const int skl_rates[] = { 162000, 216000, 270000,
                                  324000, 432000, 540000 };
static const int default_rates[] = { 162000, 270000, 540000 };

/**
 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 * @intel_dp: DP struct
 *
 * If a CPU or PCH DP output is attached to an eDP panel, this function
 * will return true, and false otherwise.
 */
static bool is_edp(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

        return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
}

static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);

        return intel_dig_port->base.base.dev;
}

static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
{
        return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
}

static void intel_dp_link_down(struct intel_dp *intel_dp);
static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
static void vlv_steal_power_sequencer(struct drm_device *dev,
                                      enum pipe pipe);

static unsigned int intel_dp_unused_lane_mask(int lane_count)
{
        return ~((1 << lane_count) - 1) & 0xf;
}

static int
intel_dp_max_link_bw(struct intel_dp  *intel_dp)
{
        int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];

        switch (max_link_bw) {
        case DP_LINK_BW_1_62:
        case DP_LINK_BW_2_7:
        case DP_LINK_BW_5_4:
                break;
        default:
                WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
                     max_link_bw);
                max_link_bw = DP_LINK_BW_1_62;
                break;
        }
        return max_link_bw;
}

static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        u8 source_max, sink_max;

        source_max = intel_dig_port->max_lanes;
        sink_max = drm_dp_max_lane_count(intel_dp->dpcd);

        return min(source_max, sink_max);
}

/*
 * The units on the numbers in the next two are... bizarre.  Examples will
 * make it clearer; this one parallels an example in the eDP spec.
 *
 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 *
 *     270000 * 1 * 8 / 10 == 216000
 *
 * The actual data capacity of that configuration is 2.16Gbit/s, so the
 * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 * 119000.  At 18bpp that's 2142000 kilobits per second.
 *
 * Thus the strange-looking division by 10 in intel_dp_link_required, to
 * get the result in decakilobits instead of kilobits.
 */

static int
intel_dp_link_required(int pixel_clock, int bpp)
{
        return (pixel_clock * bpp + 9) / 10;
}

static int
intel_dp_max_data_rate(int max_link_clock, int max_lanes)
{
        return (max_link_clock * max_lanes * 8) / 10;
}

static enum drm_mode_status
intel_dp_mode_valid(struct drm_connector *connector,
                    struct drm_display_mode *mode)
{
        struct intel_dp *intel_dp = intel_attached_dp(connector);
        struct intel_connector *intel_connector = to_intel_connector(connector);
        struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
        int target_clock = mode->clock;
        int max_rate, mode_rate, max_lanes, max_link_clock;
        int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;

        if (is_edp(intel_dp) && fixed_mode) {
                if (mode->hdisplay > fixed_mode->hdisplay)
                        return MODE_PANEL;

                if (mode->vdisplay > fixed_mode->vdisplay)
                        return MODE_PANEL;

                target_clock = fixed_mode->clock;
        }

        max_link_clock = intel_dp_max_link_rate(intel_dp);
        max_lanes = intel_dp_max_lane_count(intel_dp);

        max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
        mode_rate = intel_dp_link_required(target_clock, 18);

        if (mode_rate > max_rate || target_clock > max_dotclk)
                return MODE_CLOCK_HIGH;

        if (mode->clock < 10000)
                return MODE_CLOCK_LOW;

        if (mode->flags & DRM_MODE_FLAG_DBLCLK)
                return MODE_H_ILLEGAL;

        return MODE_OK;
}

uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
{
        int     i;
        uint32_t v = 0;

        if (src_bytes > 4)
                src_bytes = 4;
        for (i = 0; i < src_bytes; i++)
                v |= ((uint32_t) src[i]) << ((3-i) * 8);
        return v;
}

static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
{
        int i;
        if (dst_bytes > 4)
                dst_bytes = 4;
        for (i = 0; i < dst_bytes; i++)
                dst[i] = src >> ((3-i) * 8);
}

static void
intel_dp_init_panel_power_sequencer(struct drm_device *dev,
                                    struct intel_dp *intel_dp);
static void
intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
                                              struct intel_dp *intel_dp);

static void pps_lock(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct intel_encoder *encoder = &intel_dig_port->base;
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        enum intel_display_power_domain power_domain;

        /*
         * See vlv_power_sequencer_reset() why we need
         * a power domain reference here.
         */
        power_domain = intel_display_port_aux_power_domain(encoder);
        intel_display_power_get(dev_priv, power_domain);

        mutex_lock(&dev_priv->pps_mutex);
}

static void pps_unlock(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct intel_encoder *encoder = &intel_dig_port->base;
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        enum intel_display_power_domain power_domain;

        mutex_unlock(&dev_priv->pps_mutex);

        power_domain = intel_display_port_aux_power_domain(encoder);
        intel_display_power_put(dev_priv, power_domain);
}

static void
vlv_power_sequencer_kick(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = intel_dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        enum pipe pipe = intel_dp->pps_pipe;
        bool pll_enabled, release_cl_override = false;
        enum dpio_phy phy = DPIO_PHY(pipe);
        enum dpio_channel ch = vlv_pipe_to_channel(pipe);
        uint32_t DP;

        if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
                 "skipping pipe %c power seqeuncer kick due to port %c being active\n",
                 pipe_name(pipe), port_name(intel_dig_port->port)))
                return;

        DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
                      pipe_name(pipe), port_name(intel_dig_port->port));

        /* Preserve the BIOS-computed detected bit. This is
         * supposed to be read-only.
         */
        DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
        DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
        DP |= DP_PORT_WIDTH(1);
        DP |= DP_LINK_TRAIN_PAT_1;

        if (IS_CHERRYVIEW(dev))
                DP |= DP_PIPE_SELECT_CHV(pipe);
        else if (pipe == PIPE_B)
                DP |= DP_PIPEB_SELECT;

        pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;

        /*
         * The DPLL for the pipe must be enabled for this to work.
         * So enable temporarily it if it's not already enabled.
         */
        if (!pll_enabled) {
                release_cl_override = IS_CHERRYVIEW(dev) &&
                        !chv_phy_powergate_ch(dev_priv, phy, ch, true);

                if (vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
                                     &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
                        DRM_ERROR("Failed to force on pll for pipe %c!\n",
                                  pipe_name(pipe));
                        return;
                }
        }

        /*
         * Similar magic as in intel_dp_enable_port().
         * We _must_ do this port enable + disable trick
         * to make this power seqeuencer lock onto the port.
         * Otherwise even VDD force bit won't work.
         */
        I915_WRITE(intel_dp->output_reg, DP);
        POSTING_READ(intel_dp->output_reg);

        I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
        POSTING_READ(intel_dp->output_reg);

        I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
        POSTING_READ(intel_dp->output_reg);

        if (!pll_enabled) {
                vlv_force_pll_off(dev, pipe);

                if (release_cl_override)
                        chv_phy_powergate_ch(dev_priv, phy, ch, false);
        }
}

static enum pipe
vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = intel_dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_encoder *encoder;
        unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
        enum pipe pipe;

        lockdep_assert_held(&dev_priv->pps_mutex);

        /* We should never land here with regular DP ports */
        WARN_ON(!is_edp(intel_dp));

        if (intel_dp->pps_pipe != INVALID_PIPE)
                return intel_dp->pps_pipe;

        /*
         * We don't have power sequencer currently.
         * Pick one that's not used by other ports.
         */
        for_each_intel_encoder(dev, encoder) {
                struct intel_dp *tmp;

                if (encoder->type != INTEL_OUTPUT_EDP)
                        continue;

                tmp = enc_to_intel_dp(&encoder->base);

                if (tmp->pps_pipe != INVALID_PIPE)
                        pipes &= ~(1 << tmp->pps_pipe);
        }

        /*
         * Didn't find one. This should not happen since there
         * are two power sequencers and up to two eDP ports.
         */
        if (WARN_ON(pipes == 0))
                pipe = PIPE_A;
        else
                pipe = ffs(pipes) - 1;

        vlv_steal_power_sequencer(dev, pipe);
        intel_dp->pps_pipe = pipe;

        DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
                      pipe_name(intel_dp->pps_pipe),
                      port_name(intel_dig_port->port));

        /* init power sequencer on this pipe and port */
        intel_dp_init_panel_power_sequencer(dev, intel_dp);
        intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);

        /*
         * Even vdd force doesn't work until we've made
         * the power sequencer lock in on the port.
         */
        vlv_power_sequencer_kick(intel_dp);

        return intel_dp->pps_pipe;
}

typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
                               enum pipe pipe);

static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
                               enum pipe pipe)
{
        return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
}

static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
                                enum pipe pipe)
{
        return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
}

static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
                         enum pipe pipe)
{
        return true;
}

static enum pipe
vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
                     enum port port,
                     vlv_pipe_check pipe_check)
{
        enum pipe pipe;

        for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
                u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
                        PANEL_PORT_SELECT_MASK;

                if (port_sel != PANEL_PORT_SELECT_VLV(port))
                        continue;

                if (!pipe_check(dev_priv, pipe))
                        continue;

                return pipe;
        }

        return INVALID_PIPE;
}

static void
vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = intel_dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        enum port port = intel_dig_port->port;

        lockdep_assert_held(&dev_priv->pps_mutex);

        /* try to find a pipe with this port selected */
        /* first pick one where the panel is on */
        intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
                                                  vlv_pipe_has_pp_on);
        /* didn't find one? pick one where vdd is on */
        if (intel_dp->pps_pipe == INVALID_PIPE)
                intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
                                                          vlv_pipe_has_vdd_on);
        /* didn't find one? pick one with just the correct port */
        if (intel_dp->pps_pipe == INVALID_PIPE)
                intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
                                                          vlv_pipe_any);

        /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
        if (intel_dp->pps_pipe == INVALID_PIPE) {
                DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
                              port_name(port));
                return;
        }

        DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
                      port_name(port), pipe_name(intel_dp->pps_pipe));

        intel_dp_init_panel_power_sequencer(dev, intel_dp);
        intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
}

void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
{
        struct drm_device *dev = dev_priv->dev;
        struct intel_encoder *encoder;

        if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
                return;

        /*
         * We can't grab pps_mutex here due to deadlock with power_domain
         * mutex when power_domain functions are called while holding pps_mutex.
         * That also means that in order to use pps_pipe the code needs to
         * hold both a power domain reference and pps_mutex, and the power domain
         * reference get/put must be done while _not_ holding pps_mutex.
         * pps_{lock,unlock}() do these steps in the correct order, so one
         * should use them always.
         */

        for_each_intel_encoder(dev, encoder) {
                struct intel_dp *intel_dp;

                if (encoder->type != INTEL_OUTPUT_EDP)
                        continue;

                intel_dp = enc_to_intel_dp(&encoder->base);
                intel_dp->pps_pipe = INVALID_PIPE;
        }
}

static i915_reg_t
_pp_ctrl_reg(struct intel_dp *intel_dp)
{
        struct drm_device *dev = intel_dp_to_dev(intel_dp);

        if (IS_BROXTON(dev))
                return BXT_PP_CONTROL(0);
        else if (HAS_PCH_SPLIT(dev))
                return PCH_PP_CONTROL;
        else
                return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
}

static i915_reg_t
_pp_stat_reg(struct intel_dp *intel_dp)
{
        struct drm_device *dev = intel_dp_to_dev(intel_dp);

        if (IS_BROXTON(dev))
                return BXT_PP_STATUS(0);
        else if (HAS_PCH_SPLIT(dev))
                return PCH_PP_STATUS;
        else
                return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
}

/* Reboot notifier handler to shutdown panel power to guarantee T12 timing
   This function only applicable when panel PM state is not to be tracked */
static int edp_notify_handler(struct notifier_block *this, unsigned long code,
                              void *unused)
{
        struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
                                                 edp_notifier);
        struct drm_device *dev = intel_dp_to_dev(intel_dp);
        struct drm_i915_private *dev_priv = dev->dev_private;

        if (!is_edp(intel_dp) || code != SYS_RESTART)
                return 0;

        pps_lock(intel_dp);

        if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
                enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
                i915_reg_t pp_ctrl_reg, pp_div_reg;
                u32 pp_div;

                pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
                pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
                pp_div = I915_READ(pp_div_reg);
                pp_div &= PP_REFERENCE_DIVIDER_MASK;

                /* 0x1F write to PP_DIV_REG sets max cycle delay */
                I915_WRITE(pp_div_reg, pp_div | 0x1F);
                I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
                msleep(intel_dp->panel_power_cycle_delay);
        }

        pps_unlock(intel_dp);

        return 0;
}

static bool edp_have_panel_power(struct intel_dp *intel_dp)
{
        struct drm_device *dev = intel_dp_to_dev(intel_dp);
        struct drm_i915_private *dev_priv = dev->dev_private;

        lockdep_assert_held(&dev_priv->pps_mutex);

        if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
            intel_dp->pps_pipe == INVALID_PIPE)
                return false;

        return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
}

static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
{
        struct drm_device *dev = intel_dp_to_dev(intel_dp);
        struct drm_i915_private *dev_priv = dev->dev_private;

        lockdep_assert_held(&dev_priv->pps_mutex);

        if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
            intel_dp->pps_pipe == INVALID_PIPE)
                return false;

        return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
}

static void
intel_dp_check_edp(struct intel_dp *intel_dp)
{
        struct drm_device *dev = intel_dp_to_dev(intel_dp);
        struct drm_i915_private *dev_priv = dev->dev_private;

        if (!is_edp(intel_dp))
                return;

        if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
                WARN(1, "eDP powered off while attempting aux channel communication.\n");
                DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
                              I915_READ(_pp_stat_reg(intel_dp)),
                              I915_READ(_pp_ctrl_reg(intel_dp)));
        }
}

static uint32_t
intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = intel_dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
        uint32_t status;
        bool done;

#define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
        if (has_aux_irq)
                done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
                                          msecs_to_jiffies_timeout(10));
        else
                done = wait_for_atomic(C, 10) == 0;
        if (!done)
                DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
                          has_aux_irq);
#undef C

        return status;
}

static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = intel_dig_port->base.base.dev;

        /*
         * The clock divider is based off the hrawclk, and would like to run at
         * 2MHz.  So, take the hrawclk value and divide by 2 and use that
         */
        return index ? 0 : DIV_ROUND_CLOSEST(intel_hrawclk(dev), 2);
}

static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = intel_dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;

        if (index)
                return 0;

        if (intel_dig_port->port == PORT_A) {
                return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);

        } else {
                return DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2);
        }
}

static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = intel_dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;

        if (intel_dig_port->port == PORT_A) {
                if (index)
                        return 0;
                return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
        } else if (HAS_PCH_LPT_H(dev_priv)) {
                /* Workaround for non-ULT HSW */
                switch (index) {
                case 0: return 63;
                case 1: return 72;
                default: return 0;
                }
        } else  {
                return index ? 0 : DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2);
        }
}

static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
        return index ? 0 : 100;
}

static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
{
        /*
         * SKL doesn't need us to program the AUX clock divider (Hardware will
         * derive the clock from CDCLK automatically). We still implement the
         * get_aux_clock_divider vfunc to plug-in into the existing code.
         */
        return index ? 0 : 1;
}

static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
                                      bool has_aux_irq,
                                      int send_bytes,
                                      uint32_t aux_clock_divider)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = intel_dig_port->base.base.dev;
        uint32_t precharge, timeout;

        if (IS_GEN6(dev))
                precharge = 3;
        else
                precharge = 5;

        if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
                timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
        else
                timeout = DP_AUX_CH_CTL_TIME_OUT_400us;

        return DP_AUX_CH_CTL_SEND_BUSY |
               DP_AUX_CH_CTL_DONE |
               (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
               DP_AUX_CH_CTL_TIME_OUT_ERROR |
               timeout |
               DP_AUX_CH_CTL_RECEIVE_ERROR |
               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
               (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
               (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
}

static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
                                      bool has_aux_irq,
                                      int send_bytes,
                                      uint32_t unused)
{
        return DP_AUX_CH_CTL_SEND_BUSY |
               DP_AUX_CH_CTL_DONE |
               (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
               DP_AUX_CH_CTL_TIME_OUT_ERROR |
               DP_AUX_CH_CTL_TIME_OUT_1600us |
               DP_AUX_CH_CTL_RECEIVE_ERROR |
               (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
               DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
}

static int
intel_dp_aux_ch(struct intel_dp *intel_dp,
                const uint8_t *send, int send_bytes,
                uint8_t *recv, int recv_size)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = intel_dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
        uint32_t aux_clock_divider;
        int i, ret, recv_bytes;
        uint32_t status;
        int try, clock = 0;
        bool has_aux_irq = HAS_AUX_IRQ(dev);
        bool vdd;

        pps_lock(intel_dp);

        /*
         * We will be called with VDD already enabled for dpcd/edid/oui reads.
         * In such cases we want to leave VDD enabled and it's up to upper layers
         * to turn it off. But for eg. i2c-dev access we need to turn it on/off
         * ourselves.
         */
        vdd = edp_panel_vdd_on(intel_dp);

        /* dp aux is extremely sensitive to irq latency, hence request the
         * lowest possible wakeup latency and so prevent the cpu from going into
         * deep sleep states.
         */
        pm_qos_update_request(&dev_priv->pm_qos, 0);

        intel_dp_check_edp(intel_dp);

        /* Try to wait for any previous AUX channel activity */
        for (try = 0; try < 3; try++) {
                status = I915_READ_NOTRACE(ch_ctl);
                if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
                        break;
                msleep(1);
        }

        if (try == 3) {
                static u32 last_status = -1;
                const u32 status = I915_READ(ch_ctl);

                if (status != last_status) {
                        WARN(1, "dp_aux_ch not started status 0x%08x\n",
                             status);
                        last_status = status;
                }

                ret = -EBUSY;
                goto out;
        }

        /* Only 5 data registers! */
        if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
                ret = -E2BIG;
                goto out;
        }

        while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
                u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
                                                          has_aux_irq,
                                                          send_bytes,
                                                          aux_clock_divider);

                /* Must try at least 3 times according to DP spec */
                for (try = 0; try < 5; try++) {
                        /* Load the send data into the aux channel data registers */
                        for (i = 0; i < send_bytes; i += 4)
                                I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
                                           intel_dp_pack_aux(send + i,
                                                             send_bytes - i));

                        /* Send the command and wait for it to complete */
                        I915_WRITE(ch_ctl, send_ctl);

                        status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);

                        /* Clear done status and any errors */
                        I915_WRITE(ch_ctl,
                                   status |
                                   DP_AUX_CH_CTL_DONE |
                                   DP_AUX_CH_CTL_TIME_OUT_ERROR |
                                   DP_AUX_CH_CTL_RECEIVE_ERROR);

                        if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
                                continue;

                        /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
                         *   400us delay required for errors and timeouts
                         *   Timeout errors from the HW already meet this
                         *   requirement so skip to next iteration
                         */
                        if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
                                usleep_range(400, 500);
                                continue;
                        }
                        if (status & DP_AUX_CH_CTL_DONE)
                                goto done;
                }
        }

        if ((status & DP_AUX_CH_CTL_DONE) == 0) {
                DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
                ret = -EBUSY;
                goto out;
        }

done:
        /* Check for timeout or receive error.
         * Timeouts occur when the sink is not connected
         */
        if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
                DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
                ret = -EIO;
                goto out;
        }

        /* Timeouts occur when the device isn't connected, so they're
         * "normal" -- don't fill the kernel log with these */
        if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
                DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
                ret = -ETIMEDOUT;
                goto out;
        }

        /* Unload any bytes sent back from the other side */
        recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
                      DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);

        /*
         * By BSpec: "Message sizes of 0 or >20 are not allowed."
         * We have no idea of what happened so we return -EBUSY so
         * drm layer takes care for the necessary retries.
         */
        if (recv_bytes == 0 || recv_bytes > 20) {
                DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
                              recv_bytes);
                /*
                 * FIXME: This patch was created on top of a series that
                 * organize the retries at drm level. There EBUSY should
                 * also take care for 1ms wait before retrying.
                 * That aux retries re-org is still needed and after that is
                 * merged we remove this sleep from here.
                 */
                usleep_range(1000, 1500);
                ret = -EBUSY;
                goto out;
        }

        if (recv_bytes > recv_size)
                recv_bytes = recv_size;

        for (i = 0; i < recv_bytes; i += 4)
                intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
                                    recv + i, recv_bytes - i);

        ret = recv_bytes;
out:
        pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);

        if (vdd)
                edp_panel_vdd_off(intel_dp, false);

        pps_unlock(intel_dp);

        return ret;
}

#define BARE_ADDRESS_SIZE       3
#define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
static ssize_t
intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
{
        struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
        uint8_t txbuf[20], rxbuf[20];
        size_t txsize, rxsize;
        int ret;

        txbuf[0] = (msg->request << 4) |
                ((msg->address >> 16) & 0xf);
        txbuf[1] = (msg->address >> 8) & 0xff;
        txbuf[2] = msg->address & 0xff;
        txbuf[3] = msg->size - 1;

        switch (msg->request & ~DP_AUX_I2C_MOT) {
        case DP_AUX_NATIVE_WRITE:
        case DP_AUX_I2C_WRITE:
        case DP_AUX_I2C_WRITE_STATUS_UPDATE:
                txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
                rxsize = 2; /* 0 or 1 data bytes */

                if (WARN_ON(txsize > 20))
                        return -E2BIG;

                if (msg->buffer)
                        memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
                else
                        WARN_ON(msg->size);

                ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
                if (ret > 0) {
                        msg->reply = rxbuf[0] >> 4;

                        if (ret > 1) {
                                /* Number of bytes written in a short write. */
                                ret = clamp_t(int, rxbuf[1], 0, msg->size);
                        } else {
                                /* Return payload size. */
                                ret = msg->size;
                        }
                }
                break;

        case DP_AUX_NATIVE_READ:
        case DP_AUX_I2C_READ:
                txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
                rxsize = msg->size + 1;

                if (WARN_ON(rxsize > 20))
                        return -E2BIG;

                ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
                if (ret > 0) {
                        msg->reply = rxbuf[0] >> 4;
                        /*
                         * Assume happy day, and copy the data. The caller is
                         * expected to check msg->reply before touching it.
                         *
                         * Return payload size.
                         */
                        ret--;
                        memcpy(msg->buffer, rxbuf + 1, ret);
                }
                break;

        default:
                ret = -EINVAL;
                break;
        }

        return ret;
}

static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
                                       enum port port)
{
        switch (port) {
        case PORT_B:
        case PORT_C:
        case PORT_D:
                return DP_AUX_CH_CTL(port);
        default:
                MISSING_CASE(port);
                return DP_AUX_CH_CTL(PORT_B);
        }
}

static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
                                        enum port port, int index)
{
        switch (port) {
        case PORT_B:
        case PORT_C:
        case PORT_D:
                return DP_AUX_CH_DATA(port, index);
        default:
                MISSING_CASE(port);
                return DP_AUX_CH_DATA(PORT_B, index);
        }
}

static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
                                       enum port port)
{
        switch (port) {
        case PORT_A:
                return DP_AUX_CH_CTL(port);
        case PORT_B:
        case PORT_C:
        case PORT_D:
                return PCH_DP_AUX_CH_CTL(port);
        default:
                MISSING_CASE(port);
                return DP_AUX_CH_CTL(PORT_A);
        }
}

static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
                                        enum port port, int index)
{
        switch (port) {
        case PORT_A:
                return DP_AUX_CH_DATA(port, index);
        case PORT_B:
        case PORT_C:
        case PORT_D:
                return PCH_DP_AUX_CH_DATA(port, index);
        default:
                MISSING_CASE(port);
                return DP_AUX_CH_DATA(PORT_A, index);
        }
}

/*
 * On SKL we don't have Aux for port E so we rely
 * on VBT to set a proper alternate aux channel.
 */
static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
{
        const struct ddi_vbt_port_info *info =
                &dev_priv->vbt.ddi_port_info[PORT_E];

        switch (info->alternate_aux_channel) {
        case DP_AUX_A:
                return PORT_A;
        case DP_AUX_B:
                return PORT_B;
        case DP_AUX_C:
                return PORT_C;
        case DP_AUX_D:
                return PORT_D;
        default:
                MISSING_CASE(info->alternate_aux_channel);
                return PORT_A;
        }
}

static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
                                       enum port port)
{
        if (port == PORT_E)
                port = skl_porte_aux_port(dev_priv);

        switch (port) {
        case PORT_A:
        case PORT_B:
        case PORT_C:
        case PORT_D:
                return DP_AUX_CH_CTL(port);
        default:
                MISSING_CASE(port);
                return DP_AUX_CH_CTL(PORT_A);
        }
}

static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
                                        enum port port, int index)
{
        if (port == PORT_E)
                port = skl_porte_aux_port(dev_priv);

        switch (port) {
        case PORT_A:
        case PORT_B:
        case PORT_C:
        case PORT_D:
                return DP_AUX_CH_DATA(port, index);
        default:
                MISSING_CASE(port);
                return DP_AUX_CH_DATA(PORT_A, index);
        }
}

static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
                                         enum port port)
{
        if (INTEL_INFO(dev_priv)->gen >= 9)
                return skl_aux_ctl_reg(dev_priv, port);
        else if (HAS_PCH_SPLIT(dev_priv))
                return ilk_aux_ctl_reg(dev_priv, port);
        else
                return g4x_aux_ctl_reg(dev_priv, port);
}

static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
                                          enum port port, int index)
{
        if (INTEL_INFO(dev_priv)->gen >= 9)
                return skl_aux_data_reg(dev_priv, port, index);
        else if (HAS_PCH_SPLIT(dev_priv))
                return ilk_aux_data_reg(dev_priv, port, index);
        else
                return g4x_aux_data_reg(dev_priv, port, index);
}

static void intel_aux_reg_init(struct intel_dp *intel_dp)
{
        struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
        enum port port = dp_to_dig_port(intel_dp)->port;
        int i;

        intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
        for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
                intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
}

static void
intel_dp_aux_fini(struct intel_dp *intel_dp)
{
        drm_dp_aux_unregister(&intel_dp->aux);
        kfree(intel_dp->aux.name);
}

static int
intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        enum port port = intel_dig_port->port;
        int ret;

        intel_aux_reg_init(intel_dp);

        intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
        if (!intel_dp->aux.name)
                return -ENOMEM;

        intel_dp->aux.dev = connector->base.kdev;
        intel_dp->aux.transfer = intel_dp_aux_transfer;

        DRM_DEBUG_KMS("registering %s bus for %s\n",
                      intel_dp->aux.name,
                      connector->base.kdev->kobj.name);

        ret = drm_dp_aux_register(&intel_dp->aux);
        if (ret < 0) {
                DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
                          intel_dp->aux.name, ret);
                kfree(intel_dp->aux.name);
                return ret;
        }

        return 0;
}

static void
intel_dp_connector_unregister(struct intel_connector *intel_connector)
{
        struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);

        intel_dp_aux_fini(intel_dp);
        intel_connector_unregister(intel_connector);
}

static void
skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
{
        u32 ctrl1;

        memset(&pipe_config->dpll_hw_state, 0,
               sizeof(pipe_config->dpll_hw_state));

        pipe_config->ddi_pll_sel = SKL_DPLL0;
        pipe_config->dpll_hw_state.cfgcr1 = 0;
        pipe_config->dpll_hw_state.cfgcr2 = 0;

        ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
        switch (pipe_config->port_clock / 2) {
        case 81000:
                ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
                                              SKL_DPLL0);
                break;
        case 135000:
                ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
                                              SKL_DPLL0);
                break;
        case 270000:
                ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
                                              SKL_DPLL0);
                break;
        case 162000:
                ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
                                              SKL_DPLL0);
                break;
        /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
        results in CDCLK change. Need to handle the change of CDCLK by
        disabling pipes and re-enabling them */
        case 108000:
                ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
                                              SKL_DPLL0);
                break;
        case 216000:
                ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
                                              SKL_DPLL0);
                break;

        }
        pipe_config->dpll_hw_state.ctrl1 = ctrl1;
}

void
hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
{
        memset(&pipe_config->dpll_hw_state, 0,
               sizeof(pipe_config->dpll_hw_state));

        switch (pipe_config->port_clock / 2) {
        case 81000:
                pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
                break;
        case 135000:
                pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
                break;
        case 270000:
                pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
                break;
        }
}

static int
intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
{
        if (intel_dp->num_sink_rates) {
                *sink_rates = intel_dp->sink_rates;
                return intel_dp->num_sink_rates;
        }

        *sink_rates = default_rates;

        return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
}

bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
{
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = dig_port->base.base.dev;

        /* WaDisableHBR2:skl */
        if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
                return false;

        if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
            (INTEL_INFO(dev)->gen >= 9))
                return true;
        else
                return false;
}

static int
intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
{
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = dig_port->base.base.dev;
        int size;

        if (IS_BROXTON(dev)) {
                *source_rates = bxt_rates;
                size = ARRAY_SIZE(bxt_rates);
        } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
                *source_rates = skl_rates;
                size = ARRAY_SIZE(skl_rates);
        } else {
                *source_rates = default_rates;
                size = ARRAY_SIZE(default_rates);
        }

        /* This depends on the fact that 5.4 is last value in the array */
        if (!intel_dp_source_supports_hbr2(intel_dp))
                size--;

        return size;
}

static void
intel_dp_set_clock(struct intel_encoder *encoder,
                   struct intel_crtc_state *pipe_config)
{
        struct drm_device *dev = encoder->base.dev;
        const struct dp_link_dpll *divisor = NULL;
        int i, count = 0;

        if (IS_G4X(dev)) {
                divisor = gen4_dpll;
                count = ARRAY_SIZE(gen4_dpll);
        } else if (HAS_PCH_SPLIT(dev)) {
                divisor = pch_dpll;
                count = ARRAY_SIZE(pch_dpll);
        } else if (IS_CHERRYVIEW(dev)) {
                divisor = chv_dpll;
                count = ARRAY_SIZE(chv_dpll);
        } else if (IS_VALLEYVIEW(dev)) {
                divisor = vlv_dpll;
                count = ARRAY_SIZE(vlv_dpll);
        }

        if (divisor && count) {
                for (i = 0; i < count; i++) {
                        if (pipe_config->port_clock == divisor[i].clock) {
                                pipe_config->dpll = divisor[i].dpll;
                                pipe_config->clock_set = true;
                                break;
                        }
                }
        }
}

static int intersect_rates(const int *source_rates, int source_len,
                           const int *sink_rates, int sink_len,
                           int *common_rates)
{
        int i = 0, j = 0, k = 0;

        while (i < source_len && j < sink_len) {
                if (source_rates[i] == sink_rates[j]) {
                        if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
                                return k;
                        common_rates[k] = source_rates[i];
                        ++k;
                        ++i;
                        ++j;
                } else if (source_rates[i] < sink_rates[j]) {
                        ++i;
                } else {
                        ++j;
                }
        }
        return k;
}

static int intel_dp_common_rates(struct intel_dp *intel_dp,
                                 int *common_rates)
{
        const int *source_rates, *sink_rates;
        int source_len, sink_len;

        sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
        source_len = intel_dp_source_rates(intel_dp, &source_rates);

        return intersect_rates(source_rates, source_len,
                               sink_rates, sink_len,
                               common_rates);
}

static void snprintf_int_array(char *str, size_t len,
                               const int *array, int nelem)
{
        int i;

        str[0] = '\0';

        for (i = 0; i < nelem; i++) {
                int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
                if (r >= len)
                        return;
                str += r;
                len -= r;
        }
}

static void intel_dp_print_rates(struct intel_dp *intel_dp)
{
        const int *source_rates, *sink_rates;
        int source_len, sink_len, common_len;
        int common_rates[DP_MAX_SUPPORTED_RATES];
        char str[128]; /* FIXME: too big for stack? */

        if ((drm_debug & DRM_UT_KMS) == 0)
                return;

        source_len = intel_dp_source_rates(intel_dp, &source_rates);
        snprintf_int_array(str, sizeof(str), source_rates, source_len);
        DRM_DEBUG_KMS("source rates: %s\n", str);

        sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
        snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
        DRM_DEBUG_KMS("sink rates: %s\n", str);

        common_len = intel_dp_common_rates(intel_dp, common_rates);
        snprintf_int_array(str, sizeof(str), common_rates, common_len);
        DRM_DEBUG_KMS("common rates: %s\n", str);
}

static int rate_to_index(int find, const int *rates)
{
        int i = 0;

        for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
                if (find == rates[i])
                        break;

        return i;
}

int
intel_dp_max_link_rate(struct intel_dp *intel_dp)
{
        int rates[DP_MAX_SUPPORTED_RATES] = {};
        int len;

        len = intel_dp_common_rates(intel_dp, rates);
        if (WARN_ON(len <= 0))
                return 162000;

        return rates[rate_to_index(0, rates) - 1];
}

int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
{
        return rate_to_index(rate, intel_dp->sink_rates);
}

void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
                           uint8_t *link_bw, uint8_t *rate_select)
{
        if (intel_dp->num_sink_rates) {
                *link_bw = 0;
                *rate_select =
                        intel_dp_rate_select(intel_dp, port_clock);
        } else {
                *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
                *rate_select = 0;
        }
}

bool
intel_dp_compute_config(struct intel_encoder *encoder,
                        struct intel_crtc_state *pipe_config)
{
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        enum port port = dp_to_dig_port(intel_dp)->port;
        struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
        struct intel_connector *intel_connector = intel_dp->attached_connector;
        int lane_count, clock;
        int min_lane_count = 1;
        int max_lane_count = intel_dp_max_lane_count(intel_dp);
        /* Conveniently, the link BW constants become indices with a shift...*/
        int min_clock = 0;
        int max_clock;
        int bpp, mode_rate;
        int link_avail, link_clock;
        int common_rates[DP_MAX_SUPPORTED_RATES] = {};
        int common_len;
        uint8_t link_bw, rate_select;

        common_len = intel_dp_common_rates(intel_dp, common_rates);

        /* No common link rates between source and sink */
        WARN_ON(common_len <= 0);

        max_clock = common_len - 1;

        if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
                pipe_config->has_pch_encoder = true;

        pipe_config->has_dp_encoder = true;
        pipe_config->has_drrs = false;
        pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;

        if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
                intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
                                       adjusted_mode);

                if (INTEL_INFO(dev)->gen >= 9) {
                        int ret;
                        ret = skl_update_scaler_crtc(pipe_config);
                        if (ret)
                                return ret;
                }

                if (HAS_GMCH_DISPLAY(dev))
                        intel_gmch_panel_fitting(intel_crtc, pipe_config,
                                                 intel_connector->panel.fitting_mode);
                else
                        intel_pch_panel_fitting(intel_crtc, pipe_config,
                                                intel_connector->panel.fitting_mode);
        }

        if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
                return false;

        DRM_DEBUG_KMS("DP link computation with max lane count %i "
                      "max bw %d pixel clock %iKHz\n",
                      max_lane_count, common_rates[max_clock],
                      adjusted_mode->crtc_clock);

        /* Walk through all bpp values. Luckily they're all nicely spaced with 2
         * bpc in between. */
        bpp = pipe_config->pipe_bpp;
        if (is_edp(intel_dp)) {

                /* Get bpp from vbt only for panels that dont have bpp in edid */
                if (intel_connector->base.display_info.bpc == 0 &&
                        (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
                        DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
                                      dev_priv->vbt.edp_bpp);
                        bpp = dev_priv->vbt.edp_bpp;
                }

                /*
                 * Use the maximum clock and number of lanes the eDP panel
                 * advertizes being capable of. The panels are generally
                 * designed to support only a single clock and lane
                 * configuration, and typically these values correspond to the
                 * native resolution of the panel.
                 */
                min_lane_count = max_lane_count;
                min_clock = max_clock;
        }

        for (; bpp >= 6*3; bpp -= 2*3) {
                mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
                                                   bpp);

                for (clock = min_clock; clock <= max_clock; clock++) {
                        for (lane_count = min_lane_count;
                                lane_count <= max_lane_count;
                                lane_count <<= 1) {

                                link_clock = common_rates[clock];
                                link_avail = intel_dp_max_data_rate(link_clock,
                                                                    lane_count);

                                if (mode_rate <= link_avail) {
                                        goto found;
                                }
                        }
                }
        }

        return false;

found:
        if (intel_dp->color_range_auto) {
                /*
                 * See:
                 * CEA-861-E - 5.1 Default Encoding Parameters
                 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
                 */
                pipe_config->limited_color_range =
                        bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
        } else {
                pipe_config->limited_color_range =
                        intel_dp->limited_color_range;
        }

        pipe_config->lane_count = lane_count;

        pipe_config->pipe_bpp = bpp;
        pipe_config->port_clock = common_rates[clock];

        intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
                              &link_bw, &rate_select);

        DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
                      link_bw, rate_select, pipe_config->lane_count,
                      pipe_config->port_clock, bpp);
        DRM_DEBUG_KMS("DP link bw required %i available %i\n",
                      mode_rate, link_avail);

        intel_link_compute_m_n(bpp, lane_count,
                               adjusted_mode->crtc_clock,
                               pipe_config->port_clock,
                               &pipe_config->dp_m_n);

        if (intel_connector->panel.downclock_mode != NULL &&
                dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
                        pipe_config->has_drrs = true;
                        intel_link_compute_m_n(bpp, lane_count,
                                intel_connector->panel.downclock_mode->clock,
                                pipe_config->port_clock,
                                &pipe_config->dp_m2_n2);
        }

        if ((IS_SKYLAKE(dev)  || IS_KABYLAKE(dev)) && is_edp(intel_dp))
                skl_edp_set_pll_config(pipe_config);
        else if (IS_BROXTON(dev))
                /* handled in ddi */;
        else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
                hsw_dp_set_ddi_pll_sel(pipe_config);
        else
                intel_dp_set_clock(encoder, pipe_config);

        return true;
}

void intel_dp_set_link_params(struct intel_dp *intel_dp,
                              const struct intel_crtc_state *pipe_config)
{
        intel_dp->link_rate = pipe_config->port_clock;
        intel_dp->lane_count = pipe_config->lane_count;
}

static void intel_dp_prepare(struct intel_encoder *encoder)
{
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        enum port port = dp_to_dig_port(intel_dp)->port;
        struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
        const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;

        intel_dp_set_link_params(intel_dp, crtc->config);

        /*
         * There are four kinds of DP registers:
         *
         *      IBX PCH
         *      SNB CPU
         *      IVB CPU
         *      CPT PCH
         *
         * IBX PCH and CPU are the same for almost everything,
         * except that the CPU DP PLL is configured in this
         * register
         *
         * CPT PCH is quite different, having many bits moved
         * to the TRANS_DP_CTL register instead. That
         * configuration happens (oddly) in ironlake_pch_enable
         */

        /* Preserve the BIOS-computed detected bit. This is
         * supposed to be read-only.
         */
        intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;

        /* Handle DP bits in common between all three register formats */
        intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
        intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);

        /* Split out the IBX/CPU vs CPT settings */

        if (IS_GEN7(dev) && port == PORT_A) {
                if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
                        intel_dp->DP |= DP_SYNC_HS_HIGH;
                if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
                        intel_dp->DP |= DP_SYNC_VS_HIGH;
                intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

                if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
                        intel_dp->DP |= DP_ENHANCED_FRAMING;

                intel_dp->DP |= crtc->pipe << 29;
        } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
                u32 trans_dp;

                intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;

                trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
                if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
                        trans_dp |= TRANS_DP_ENH_FRAMING;
                else
                        trans_dp &= ~TRANS_DP_ENH_FRAMING;
                I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
        } else {
                if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
                    !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
                        intel_dp->DP |= DP_COLOR_RANGE_16_235;

                if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
                        intel_dp->DP |= DP_SYNC_HS_HIGH;
                if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
                        intel_dp->DP |= DP_SYNC_VS_HIGH;
                intel_dp->DP |= DP_LINK_TRAIN_OFF;

                if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
                        intel_dp->DP |= DP_ENHANCED_FRAMING;

                if (IS_CHERRYVIEW(dev))
                        intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
                else if (crtc->pipe == PIPE_B)
                        intel_dp->DP |= DP_PIPEB_SELECT;
        }
}

#define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
#define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)

#define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
#define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)

#define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
#define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)

static void wait_panel_status(struct intel_dp *intel_dp,
                                       u32 mask,
                                       u32 value)
{
        struct drm_device *dev = intel_dp_to_dev(intel_dp);
        struct drm_i915_private *dev_priv = dev->dev_private;
        i915_reg_t pp_stat_reg, pp_ctrl_reg;

        lockdep_assert_held(&dev_priv->pps_mutex);

        pp_stat_reg = _pp_stat_reg(intel_dp);
        pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

        DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
                        mask, value,
                        I915_READ(pp_stat_reg),
                        I915_READ(pp_ctrl_reg));

        if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
                DRM_ERROR("Panel status timeout: status %08x control %08x\n",
                                I915_READ(pp_stat_reg),
                                I915_READ(pp_ctrl_reg));
        }

        DRM_DEBUG_KMS("Wait complete\n");
}

static void wait_panel_on(struct intel_dp *intel_dp)
{
        DRM_DEBUG_KMS("Wait for panel power on\n");
        wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
}

static void wait_panel_off(struct intel_dp *intel_dp)
{
        DRM_DEBUG_KMS("Wait for panel power off time\n");
        wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
}

static void wait_panel_power_cycle(struct intel_dp *intel_dp)
{
        ktime_t panel_power_on_time;
        s64 panel_power_off_duration;

        DRM_DEBUG_KMS("Wait for panel power cycle\n");

        /* take the difference of currrent time and panel power off time
         * and then make panel wait for t11_t12 if needed. */
        panel_power_on_time = ktime_get_boottime();
        panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);

        /* When we disable the VDD override bit last we have to do the manual
         * wait. */
        if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
                wait_remaining_ms_from_jiffies(jiffies,
                                       intel_dp->panel_power_cycle_delay - panel_power_off_duration);

        wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
}

static void wait_backlight_on(struct intel_dp *intel_dp)
{
        wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
                                       intel_dp->backlight_on_delay);
}

static void edp_wait_backlight_off(struct intel_dp *intel_dp)
{
        wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
                                       intel_dp->backlight_off_delay);
}

/* Read the current pp_control value, unlocking the register if it
 * is locked
 */

static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
{
        struct drm_device *dev = intel_dp_to_dev(intel_dp);
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 control;

        lockdep_assert_held(&dev_priv->pps_mutex);

        control = I915_READ(_pp_ctrl_reg(intel_dp));
        if (!IS_BROXTON(dev)) {
                control &= ~PANEL_UNLOCK_MASK;
                control |= PANEL_UNLOCK_REGS;
        }
        return control;
}

/*
 * Must be paired with edp_panel_vdd_off().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
{
        struct drm_device *dev = intel_dp_to_dev(intel_dp);
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct intel_encoder *intel_encoder = &intel_dig_port->base;
        struct drm_i915_private *dev_priv = dev->dev_private;
        enum intel_display_power_domain power_domain;
        u32 pp;
        i915_reg_t pp_stat_reg, pp_ctrl_reg;
        bool need_to_disable = !intel_dp->want_panel_vdd;

        lockdep_assert_held(&dev_priv->pps_mutex);

        if (!is_edp(intel_dp))
                return false;

        cancel_delayed_work(&intel_dp->panel_vdd_work);
        intel_dp->want_panel_vdd = true;

        if (edp_have_panel_vdd(intel_dp))
                return need_to_disable;

        power_domain = intel_display_port_aux_power_domain(intel_encoder);
        intel_display_power_get(dev_priv, power_domain);

        DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
                      port_name(intel_dig_port->port));

        if (!edp_have_panel_power(intel_dp))
                wait_panel_power_cycle(intel_dp);

        pp = ironlake_get_pp_control(intel_dp);
        pp |= EDP_FORCE_VDD;

        pp_stat_reg = _pp_stat_reg(intel_dp);
        pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

        I915_WRITE(pp_ctrl_reg, pp);
        POSTING_READ(pp_ctrl_reg);
        DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
                        I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
        /*
         * If the panel wasn't on, delay before accessing aux channel
         */
        if (!edp_have_panel_power(intel_dp)) {
                DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
                              port_name(intel_dig_port->port));
                msleep(intel_dp->panel_power_up_delay);
        }

        return need_to_disable;
}

/*
 * Must be paired with intel_edp_panel_vdd_off() or
 * intel_edp_panel_off().
 * Nested calls to these functions are not allowed since
 * we drop the lock. Caller must use some higher level
 * locking to prevent nested calls from other threads.
 */
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
{
        bool vdd;

        if (!is_edp(intel_dp))
                return;

        pps_lock(intel_dp);
        vdd = edp_panel_vdd_on(intel_dp);
        pps_unlock(intel_dp);

        I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
             port_name(dp_to_dig_port(intel_dp)->port));
}

static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
{
        struct drm_device *dev = intel_dp_to_dev(intel_dp);
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_digital_port *intel_dig_port =
                dp_to_dig_port(intel_dp);
        struct intel_encoder *intel_encoder = &intel_dig_port->base;
        enum intel_display_power_domain power_domain;
        u32 pp;
        i915_reg_t pp_stat_reg, pp_ctrl_reg;

        lockdep_assert_held(&dev_priv->pps_mutex);

        WARN_ON(intel_dp->want_panel_vdd);

        if (!edp_have_panel_vdd(intel_dp))
                return;

        DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
                      port_name(intel_dig_port->port));

        pp = ironlake_get_pp_control(intel_dp);
        pp &= ~EDP_FORCE_VDD;

        pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
        pp_stat_reg = _pp_stat_reg(intel_dp);

        I915_WRITE(pp_ctrl_reg, pp);
        POSTING_READ(pp_ctrl_reg);

        /* Make sure sequencer is idle before allowing subsequent activity */
        DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
        I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));

        if ((pp & POWER_TARGET_ON) == 0)
                intel_dp->panel_power_off_time = ktime_get_boottime();

        power_domain = intel_display_port_aux_power_domain(intel_encoder);
        intel_display_power_put(dev_priv, power_domain);
}

static void edp_panel_vdd_work(struct work_struct *__work)
{
        struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
                                                 struct intel_dp, panel_vdd_work);

        pps_lock(intel_dp);
        if (!intel_dp->want_panel_vdd)
                edp_panel_vdd_off_sync(intel_dp);
        pps_unlock(intel_dp);
}

static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
{
        unsigned long delay;

        /*
         * Queue the timer to fire a long time from now (relative to the power
         * down delay) to keep the panel power up across a sequence of
         * operations.
         */
        delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
        schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
}

/*
 * Must be paired with edp_panel_vdd_on().
 * Must hold pps_mutex around the whole on/off sequence.
 * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
 */
static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
{
        struct drm_i915_private *dev_priv =
                intel_dp_to_dev(intel_dp)->dev_private;

        lockdep_assert_held(&dev_priv->pps_mutex);

        if (!is_edp(intel_dp))
                return;

        I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
             port_name(dp_to_dig_port(intel_dp)->port));

        intel_dp->want_panel_vdd = false;

        if (sync)
                edp_panel_vdd_off_sync(intel_dp);
        else
                edp_panel_vdd_schedule_off(intel_dp);
}

static void edp_panel_on(struct intel_dp *intel_dp)
{
        struct drm_device *dev = intel_dp_to_dev(intel_dp);
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 pp;
        i915_reg_t pp_ctrl_reg;

        lockdep_assert_held(&dev_priv->pps_mutex);

        if (!is_edp(intel_dp))
                return;

        DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
                      port_name(dp_to_dig_port(intel_dp)->port));

        if (WARN(edp_have_panel_power(intel_dp),
                 "eDP port %c panel power already on\n",
                 port_name(dp_to_dig_port(intel_dp)->port)))
                return;

        wait_panel_power_cycle(intel_dp);

        pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
        pp = ironlake_get_pp_control(intel_dp);
        if (IS_GEN5(dev)) {
                /* ILK workaround: disable reset around power sequence */
                pp &= ~PANEL_POWER_RESET;
                I915_WRITE(pp_ctrl_reg, pp);
                POSTING_READ(pp_ctrl_reg);
        }

        pp |= POWER_TARGET_ON;
        if (!IS_GEN5(dev))
                pp |= PANEL_POWER_RESET;

        I915_WRITE(pp_ctrl_reg, pp);
        POSTING_READ(pp_ctrl_reg);

        wait_panel_on(intel_dp);
        intel_dp->last_power_on = jiffies;

        if (IS_GEN5(dev)) {
                pp |= PANEL_POWER_RESET; /* restore panel reset bit */
                I915_WRITE(pp_ctrl_reg, pp);
                POSTING_READ(pp_ctrl_reg);
        }
}

void intel_edp_panel_on(struct intel_dp *intel_dp)
{
        if (!is_edp(intel_dp))
                return;

        pps_lock(intel_dp);
        edp_panel_on(intel_dp);
        pps_unlock(intel_dp);
}


static void edp_panel_off(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct intel_encoder *intel_encoder = &intel_dig_port->base;
        struct drm_device *dev = intel_dp_to_dev(intel_dp);
        struct drm_i915_private *dev_priv = dev->dev_private;
        enum intel_display_power_domain power_domain;
        u32 pp;
        i915_reg_t pp_ctrl_reg;

        lockdep_assert_held(&dev_priv->pps_mutex);

        if (!is_edp(intel_dp))
                return;

        DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
                      port_name(dp_to_dig_port(intel_dp)->port));

        WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
             port_name(dp_to_dig_port(intel_dp)->port));

        pp = ironlake_get_pp_control(intel_dp);
        /* We need to switch off panel power _and_ force vdd, for otherwise some
         * panels get very unhappy and cease to work. */
        pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
                EDP_BLC_ENABLE);

        pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

        intel_dp->want_panel_vdd = false;

        I915_WRITE(pp_ctrl_reg, pp);
        POSTING_READ(pp_ctrl_reg);

        intel_dp->panel_power_off_time = ktime_get_boottime();
        wait_panel_off(intel_dp);

        /* We got a reference when we enabled the VDD. */
        power_domain = intel_display_port_aux_power_domain(intel_encoder);
        intel_display_power_put(dev_priv, power_domain);
}

void intel_edp_panel_off(struct intel_dp *intel_dp)
{
        if (!is_edp(intel_dp))
                return;

        pps_lock(intel_dp);
        edp_panel_off(intel_dp);
        pps_unlock(intel_dp);
}

/* Enable backlight in the panel power control. */
static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = intel_dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 pp;
        i915_reg_t pp_ctrl_reg;

        /*
         * If we enable the backlight right away following a panel power
         * on, we may see slight flicker as the panel syncs with the eDP
         * link.  So delay a bit to make sure the image is solid before
         * allowing it to appear.
         */
        wait_backlight_on(intel_dp);

        pps_lock(intel_dp);

        pp = ironlake_get_pp_control(intel_dp);
        pp |= EDP_BLC_ENABLE;

        pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

        I915_WRITE(pp_ctrl_reg, pp);
        POSTING_READ(pp_ctrl_reg);

        pps_unlock(intel_dp);
}

/* Enable backlight PWM and backlight PP control. */
void intel_edp_backlight_on(struct intel_dp *intel_dp)
{
        if (!is_edp(intel_dp))
                return;

        DRM_DEBUG_KMS("\n");

        intel_panel_enable_backlight(intel_dp->attached_connector);
        _intel_edp_backlight_on(intel_dp);
}

/* Disable backlight in the panel power control. */
static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
{
        struct drm_device *dev = intel_dp_to_dev(intel_dp);
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 pp;
        i915_reg_t pp_ctrl_reg;

        if (!is_edp(intel_dp))
                return;

        pps_lock(intel_dp);

        pp = ironlake_get_pp_control(intel_dp);
        pp &= ~EDP_BLC_ENABLE;

        pp_ctrl_reg = _pp_ctrl_reg(intel_dp);

        I915_WRITE(pp_ctrl_reg, pp);
        POSTING_READ(pp_ctrl_reg);

        pps_unlock(intel_dp);

        intel_dp->last_backlight_off = jiffies;
        edp_wait_backlight_off(intel_dp);
}

/* Disable backlight PP control and backlight PWM. */
void intel_edp_backlight_off(struct intel_dp *intel_dp)
{
        if (!is_edp(intel_dp))
                return;

        DRM_DEBUG_KMS("\n");

        _intel_edp_backlight_off(intel_dp);
        intel_panel_disable_backlight(intel_dp->attached_connector);
}

/*
 * Hook for controlling the panel power control backlight through the bl_power
 * sysfs attribute. Take care to handle multiple calls.
 */
static void intel_edp_backlight_power(struct intel_connector *connector,
                                      bool enable)
{
        struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
        bool is_enabled;

        pps_lock(intel_dp);
        is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
        pps_unlock(intel_dp);

        if (is_enabled == enable)
                return;

        DRM_DEBUG_KMS("panel power control backlight %s\n",
                      enable ? "enable" : "disable");

        if (enable)
                _intel_edp_backlight_on(intel_dp);
        else
                _intel_edp_backlight_off(intel_dp);
}

static void assert_dp_port(struct intel_dp *intel_dp, bool state)
{
        struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
        struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
        bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;

        I915_STATE_WARN(cur_state != state,
                        "DP port %c state assertion failure (expected %s, current %s)\n",
                        port_name(dig_port->port),
                        onoff(state), onoff(cur_state));
}
#define assert_dp_port_disabled(d) assert_dp_port((d), false)

static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
{
        bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;

        I915_STATE_WARN(cur_state != state,
                        "eDP PLL state assertion failure (expected %s, current %s)\n",
                        onoff(state), onoff(cur_state));
}
#define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
#define assert_edp_pll_disabled(d) assert_edp_pll((d), false)

static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        assert_pipe_disabled(dev_priv, crtc->pipe);
        assert_dp_port_disabled(intel_dp);
        assert_edp_pll_disabled(dev_priv);

        DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
                      crtc->config->port_clock);

        intel_dp->DP &= ~DP_PLL_FREQ_MASK;

        if (crtc->config->port_clock == 162000)
                intel_dp->DP |= DP_PLL_FREQ_162MHZ;
        else
                intel_dp->DP |= DP_PLL_FREQ_270MHZ;

        I915_WRITE(DP_A, intel_dp->DP);
        POSTING_READ(DP_A);
        udelay(500);

        intel_dp->DP |= DP_PLL_ENABLE;

        I915_WRITE(DP_A, intel_dp->DP);
        POSTING_READ(DP_A);
        udelay(200);
}

static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);

        assert_pipe_disabled(dev_priv, crtc->pipe);
        assert_dp_port_disabled(intel_dp);
        assert_edp_pll_enabled(dev_priv);

        DRM_DEBUG_KMS("disabling eDP PLL\n");

        intel_dp->DP &= ~DP_PLL_ENABLE;

        I915_WRITE(DP_A, intel_dp->DP);
        POSTING_READ(DP_A);
        udelay(200);
}

/* If the sink supports it, try to set the power state appropriately */
void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
{
        int ret, i;

        /* Should have a valid DPCD by this point */
        if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
                return;

        if (mode != DRM_MODE_DPMS_ON) {
                ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
                                         DP_SET_POWER_D3);
        } else {
                /*
                 * When turning on, we need to retry for 1ms to give the sink
                 * time to wake up.
                 */
                for (i = 0; i < 3; i++) {
                        ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
                                                 DP_SET_POWER_D0);
                        if (ret == 1)
                                break;
                        msleep(1);
                }
        }

        if (ret != 1)
                DRM_DEBUG_KMS("failed to %s sink power state\n",
                              mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
}

static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
                                  enum pipe *pipe)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        enum port port = dp_to_dig_port(intel_dp)->port;
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        enum intel_display_power_domain power_domain;
        u32 tmp;
        bool ret;

        power_domain = intel_display_port_power_domain(encoder);
        if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
                return false;

        ret = false;

        tmp = I915_READ(intel_dp->output_reg);

        if (!(tmp & DP_PORT_EN))
                goto out;

        if (IS_GEN7(dev) && port == PORT_A) {
                *pipe = PORT_TO_PIPE_CPT(tmp);
        } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
                enum pipe p;

                for_each_pipe(dev_priv, p) {
                        u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
                        if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
                                *pipe = p;
                                ret = true;

                                goto out;
                        }
                }

                DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
                              i915_mmio_reg_offset(intel_dp->output_reg));
        } else if (IS_CHERRYVIEW(dev)) {
                *pipe = DP_PORT_TO_PIPE_CHV(tmp);
        } else {
                *pipe = PORT_TO_PIPE(tmp);
        }

        ret = true;

out:
        intel_display_power_put(dev_priv, power_domain);

        return ret;
}

static void intel_dp_get_config(struct intel_encoder *encoder,
                                struct intel_crtc_state *pipe_config)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        u32 tmp, flags = 0;
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        enum port port = dp_to_dig_port(intel_dp)->port;
        struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
        int dotclock;

        tmp = I915_READ(intel_dp->output_reg);

        pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;

        if (HAS_PCH_CPT(dev) && port != PORT_A) {
                u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));

                if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
                        flags |= DRM_MODE_FLAG_PHSYNC;
                else
                        flags |= DRM_MODE_FLAG_NHSYNC;

                if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
                        flags |= DRM_MODE_FLAG_PVSYNC;
                else
                        flags |= DRM_MODE_FLAG_NVSYNC;
        } else {
                if (tmp & DP_SYNC_HS_HIGH)
                        flags |= DRM_MODE_FLAG_PHSYNC;
                else
                        flags |= DRM_MODE_FLAG_NHSYNC;

                if (tmp & DP_SYNC_VS_HIGH)
                        flags |= DRM_MODE_FLAG_PVSYNC;
                else
                        flags |= DRM_MODE_FLAG_NVSYNC;
        }

        pipe_config->base.adjusted_mode.flags |= flags;

        if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
            !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
                pipe_config->limited_color_range = true;

        pipe_config->has_dp_encoder = true;

        pipe_config->lane_count =
                ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;

        intel_dp_get_m_n(crtc, pipe_config);

        if (port == PORT_A) {
                if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
                        pipe_config->port_clock = 162000;
                else
                        pipe_config->port_clock = 270000;
        }

        dotclock = intel_dotclock_calculate(pipe_config->port_clock,
                                            &pipe_config->dp_m_n);

        if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
                ironlake_check_encoder_dotclock(pipe_config, dotclock);

        pipe_config->base.adjusted_mode.crtc_clock = dotclock;

        if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
            pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
                /*
                 * This is a big fat ugly hack.
                 *
                 * Some machines in UEFI boot mode provide us a VBT that has 18
                 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
                 * unknown we fail to light up. Yet the same BIOS boots up with
                 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
                 * max, not what it tells us to use.
                 *
                 * Note: This will still be broken if the eDP panel is not lit
                 * up by the BIOS, and thus we can't get the mode at module
                 * load.
                 */
                DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
                              pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
                dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
        }
}

static void intel_disable_dp(struct intel_encoder *encoder)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        struct drm_device *dev = encoder->base.dev;
        struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

        if (crtc->config->has_audio)
                intel_audio_codec_disable(encoder);

        if (HAS_PSR(dev) && !HAS_DDI(dev))
                intel_psr_disable(intel_dp);

        /* Make sure the panel is off before trying to change the mode. But also
         * ensure that we have vdd while we switch off the panel. */
        intel_edp_panel_vdd_on(intel_dp);
        intel_edp_backlight_off(intel_dp);
        intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
        intel_edp_panel_off(intel_dp);

        /* disable the port before the pipe on g4x */
        if (INTEL_INFO(dev)->gen < 5)
                intel_dp_link_down(intel_dp);
}

static void ilk_post_disable_dp(struct intel_encoder *encoder)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        enum port port = dp_to_dig_port(intel_dp)->port;

        intel_dp_link_down(intel_dp);

        /* Only ilk+ has port A */
        if (port == PORT_A)
                ironlake_edp_pll_off(intel_dp);
}

static void vlv_post_disable_dp(struct intel_encoder *encoder)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

        intel_dp_link_down(intel_dp);
}

static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
                                     bool reset)
{
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
        struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
        enum pipe pipe = crtc->pipe;
        uint32_t val;

        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
        if (reset)
                val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
        else
                val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);

        if (crtc->config->lane_count > 2) {
                val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
                if (reset)
                        val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
                else
                        val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
                vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
        }

        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
        val |= CHV_PCS_REQ_SOFTRESET_EN;
        if (reset)
                val &= ~DPIO_PCS_CLK_SOFT_RESET;
        else
                val |= DPIO_PCS_CLK_SOFT_RESET;
        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);

        if (crtc->config->lane_count > 2) {
                val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
                val |= CHV_PCS_REQ_SOFTRESET_EN;
                if (reset)
                        val &= ~DPIO_PCS_CLK_SOFT_RESET;
                else
                        val |= DPIO_PCS_CLK_SOFT_RESET;
                vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
        }
}

static void chv_post_disable_dp(struct intel_encoder *encoder)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;

        intel_dp_link_down(intel_dp);

        mutex_lock(&dev_priv->sb_lock);

        /* Assert data lane reset */
        chv_data_lane_soft_reset(encoder, true);

        mutex_unlock(&dev_priv->sb_lock);
}

static void
_intel_dp_set_link_train(struct intel_dp *intel_dp,
                         uint32_t *DP,
                         uint8_t dp_train_pat)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct drm_device *dev = intel_dig_port->base.base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        enum port port = intel_dig_port->port;

        if (HAS_DDI(dev)) {
                uint32_t temp = I915_READ(DP_TP_CTL(port));

                if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
                        temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
                else
                        temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;

                temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
                switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
                case DP_TRAINING_PATTERN_DISABLE:
                        temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;

                        break;
                case DP_TRAINING_PATTERN_1:
                        temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
                        break;
                case DP_TRAINING_PATTERN_2:
                        temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
                        break;
                case DP_TRAINING_PATTERN_3:
                        temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
                        break;
                }
                I915_WRITE(DP_TP_CTL(port), temp);

        } else if ((IS_GEN7(dev) && port == PORT_A) ||
                   (HAS_PCH_CPT(dev) && port != PORT_A)) {
                *DP &= ~DP_LINK_TRAIN_MASK_CPT;

                switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
                case DP_TRAINING_PATTERN_DISABLE:
                        *DP |= DP_LINK_TRAIN_OFF_CPT;
                        break;
                case DP_TRAINING_PATTERN_1:
                        *DP |= DP_LINK_TRAIN_PAT_1_CPT;
                        break;
                case DP_TRAINING_PATTERN_2:
                        *DP |= DP_LINK_TRAIN_PAT_2_CPT;
                        break;
                case DP_TRAINING_PATTERN_3:
                        DRM_ERROR("DP training pattern 3 not supported\n");
                        *DP |= DP_LINK_TRAIN_PAT_2_CPT;
                        break;
                }

        } else {
                if (IS_CHERRYVIEW(dev))
                        *DP &= ~DP_LINK_TRAIN_MASK_CHV;
                else
                        *DP &= ~DP_LINK_TRAIN_MASK;

                switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
                case DP_TRAINING_PATTERN_DISABLE:
                        *DP |= DP_LINK_TRAIN_OFF;
                        break;
                case DP_TRAINING_PATTERN_1:
                        *DP |= DP_LINK_TRAIN_PAT_1;
                        break;
                case DP_TRAINING_PATTERN_2:
                        *DP |= DP_LINK_TRAIN_PAT_2;
                        break;
                case DP_TRAINING_PATTERN_3:
                        if (IS_CHERRYVIEW(dev)) {
                                *DP |= DP_LINK_TRAIN_PAT_3_CHV;
                        } else {
                                DRM_ERROR("DP training pattern 3 not supported\n");
                                *DP |= DP_LINK_TRAIN_PAT_2;
                        }
                        break;
                }
        }
}

static void intel_dp_enable_port(struct intel_dp *intel_dp)
{
        struct drm_device *dev = intel_dp_to_dev(intel_dp);
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *crtc =
                to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);

        /* enable with pattern 1 (as per spec) */
        _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
                                 DP_TRAINING_PATTERN_1);

        I915_WRITE(intel_dp->output_reg, intel_dp->DP);
        POSTING_READ(intel_dp->output_reg);

        /*
         * Magic for VLV/CHV. We _must_ first set up the register
         * without actually enabling the port, and then do another
         * write to enable the port. Otherwise link training will
         * fail when the power sequencer is freshly used for this port.
         */
        intel_dp->DP |= DP_PORT_EN;
        if (crtc->config->has_audio)
                intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;

        I915_WRITE(intel_dp->output_reg, intel_dp->DP);
        POSTING_READ(intel_dp->output_reg);
}

static void intel_enable_dp(struct intel_encoder *encoder)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
        uint32_t dp_reg = I915_READ(intel_dp->output_reg);
        enum port port = dp_to_dig_port(intel_dp)->port;
        enum pipe pipe = crtc->pipe;

        if (WARN_ON(dp_reg & DP_PORT_EN))
                return;

        pps_lock(intel_dp);

        if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
                vlv_init_panel_power_sequencer(intel_dp);

        /*
         * We get an occasional spurious underrun between the port
         * enable and vdd enable, when enabling port A eDP.
         *
         * FIXME: Not sure if this applies to (PCH) port D eDP as well
         */
        if (port == PORT_A)
                intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);

        intel_dp_enable_port(intel_dp);

        if (port == PORT_A && IS_GEN5(dev_priv)) {
                /*
                 * Underrun reporting for the other pipe was disabled in
                 * g4x_pre_enable_dp(). The eDP PLL and port have now been
                 * enabled, so it's now safe to re-enable underrun reporting.
                 */
                intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
                intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
                intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
        }

        edp_panel_vdd_on(intel_dp);
        edp_panel_on(intel_dp);
        edp_panel_vdd_off(intel_dp, true);

        if (port == PORT_A)
                intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);

        pps_unlock(intel_dp);

        if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
                unsigned int lane_mask = 0x0;

                if (IS_CHERRYVIEW(dev))
                        lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);

                vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
                                    lane_mask);
        }

        intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
        intel_dp_start_link_train(intel_dp);
        intel_dp_stop_link_train(intel_dp);

        if (crtc->config->has_audio) {
                DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
                                 pipe_name(pipe));
                intel_audio_codec_enable(encoder);
        }
}

static void g4x_enable_dp(struct intel_encoder *encoder)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

        intel_enable_dp(encoder);
        intel_edp_backlight_on(intel_dp);
}

static void vlv_enable_dp(struct intel_encoder *encoder)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);

        intel_edp_backlight_on(intel_dp);
        intel_psr_enable(intel_dp);
}

static void g4x_pre_enable_dp(struct intel_encoder *encoder)
{
        struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        enum port port = dp_to_dig_port(intel_dp)->port;
        enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;

        intel_dp_prepare(encoder);

        if (port == PORT_A && IS_GEN5(dev_priv)) {
                /*
                 * We get FIFO underruns on the other pipe when
                 * enabling the CPU eDP PLL, and when enabling CPU
                 * eDP port. We could potentially avoid the PLL
                 * underrun with a vblank wait just prior to enabling
                 * the PLL, but that doesn't appear to help the port
                 * enable case. Just sweep it all under the rug.
                 */
                intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
                intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
        }

        /* Only ilk+ has port A */
        if (port == PORT_A)
                ironlake_edp_pll_on(intel_dp);
}

static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
        enum pipe pipe = intel_dp->pps_pipe;
        i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);

        edp_panel_vdd_off_sync(intel_dp);

        /*
         * VLV seems to get confused when multiple power seqeuencers
         * have the same port selected (even if only one has power/vdd
         * enabled). The failure manifests as vlv_wait_port_ready() failing
         * CHV on the other hand doesn't seem to mind having the same port
         * selected in multiple power seqeuencers, but let's clear the
         * port select always when logically disconnecting a power sequencer
         * from a port.
         */
        DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
                      pipe_name(pipe), port_name(intel_dig_port->port));
        I915_WRITE(pp_on_reg, 0);
        POSTING_READ(pp_on_reg);

        intel_dp->pps_pipe = INVALID_PIPE;
}

static void vlv_steal_power_sequencer(struct drm_device *dev,
                                      enum pipe pipe)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_encoder *encoder;

        lockdep_assert_held(&dev_priv->pps_mutex);

        if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
                return;

        for_each_intel_encoder(dev, encoder) {
                struct intel_dp *intel_dp;
                enum port port;

                if (encoder->type != INTEL_OUTPUT_EDP)
                        continue;

                intel_dp = enc_to_intel_dp(&encoder->base);
                port = dp_to_dig_port(intel_dp)->port;

                if (intel_dp->pps_pipe != pipe)
                        continue;

                DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
                              pipe_name(pipe), port_name(port));

                WARN(encoder->base.crtc,
                     "stealing pipe %c power sequencer from active eDP port %c\n",
                     pipe_name(pipe), port_name(port));

                /* make sure vdd is off before we steal it */
                vlv_detach_power_sequencer(intel_dp);
        }
}

static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
{
        struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
        struct intel_encoder *encoder = &intel_dig_port->base;
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);

        lockdep_assert_held(&dev_priv->pps_mutex);

        if (!is_edp(intel_dp))
                return;

        if (intel_dp->pps_pipe == crtc->pipe)
                return;

        /*
         * If another power sequencer was being used on this
         * port previously make sure to turn off vdd there while
         * we still have control of it.
         */
        if (intel_dp->pps_pipe != INVALID_PIPE)
                vlv_detach_power_sequencer(intel_dp);

        /*
         * We may be stealing the power
         * sequencer from another port.
         */
        vlv_steal_power_sequencer(dev, crtc->pipe);

        /* now it's all ours */
        intel_dp->pps_pipe = crtc->pipe;

        DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
                      pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));

        /* init power sequencer on this pipe and port */
        intel_dp_init_panel_power_sequencer(dev, intel_dp);
        intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
}

static void vlv_pre_enable_dp(struct intel_encoder *encoder)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
        enum dpio_channel port = vlv_dport_to_channel(dport);
        int pipe = intel_crtc->pipe;
        u32 val;

        mutex_lock(&dev_priv->sb_lock);

        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
        val = 0;
        if (pipe)
                val |= (1<<21);
        else
                val &= ~(1<<21);
        val |= 0x001000c4;
        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);

        mutex_unlock(&dev_priv->sb_lock);

        intel_enable_dp(encoder);
}

static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
{
        struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc =
                to_intel_crtc(encoder->base.crtc);
        enum dpio_channel port = vlv_dport_to_channel(dport);
        int pipe = intel_crtc->pipe;

        intel_dp_prepare(encoder);

        /* Program Tx lane resets to default */
        mutex_lock(&dev_priv->sb_lock);
        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
                         DPIO_PCS_TX_LANE2_RESET |
                         DPIO_PCS_TX_LANE1_RESET);
        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
                         DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
                         DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
                         (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
                                 DPIO_PCS_CLK_SOFT_RESET);

        /* Fix up inter-pair skew failure */
        vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
        vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
        vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
        mutex_unlock(&dev_priv->sb_lock);
}

static void chv_pre_enable_dp(struct intel_encoder *encoder)
{
        struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
        struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
        struct drm_device *dev = encoder->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc =
                to_intel_crtc(encoder->base.crtc);
        enum dpio_channel ch = vlv_dport_to_channel(dport);
        int pipe = intel_crtc->pipe;
        int data, i, stagger;
        u32 val;

        mutex_lock(&dev_priv->sb_lock);

        /* allow hardware to manage TX FIFO reset source */
        val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
        val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
        vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);