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18#include <linux/irqdomain.h>
19#include <linux/irq.h>
20
21#include "msm_drv.h"
22#include "mdp5_kms.h"
23
24void mdp5_set_irqmask(struct mdp_kms *mdp_kms, uint32_t irqmask,
25 uint32_t old_irqmask)
26{
27 mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_MDP_INTR_CLEAR(0),
28 irqmask ^ (irqmask & old_irqmask));
29 mdp5_write(to_mdp5_kms(mdp_kms), REG_MDP5_MDP_INTR_EN(0), irqmask);
30}
31
32static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus)
33{
34 DRM_ERROR_RATELIMITED("errors: %08x\n", irqstatus);
35}
36
37void mdp5_irq_preinstall(struct msm_kms *kms)
38{
39 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
40 mdp5_enable(mdp5_kms);
41 mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_CLEAR(0), 0xffffffff);
42 mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_EN(0), 0x00000000);
43 mdp5_disable(mdp5_kms);
44}
45
46int mdp5_irq_postinstall(struct msm_kms *kms)
47{
48 struct mdp_kms *mdp_kms = to_mdp_kms(kms);
49 struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
50 struct mdp_irq *error_handler = &mdp5_kms->error_handler;
51
52 error_handler->irq = mdp5_irq_error_handler;
53 error_handler->irqmask = MDP5_IRQ_INTF0_UNDER_RUN |
54 MDP5_IRQ_INTF1_UNDER_RUN |
55 MDP5_IRQ_INTF2_UNDER_RUN |
56 MDP5_IRQ_INTF3_UNDER_RUN;
57
58 mdp_irq_register(mdp_kms, error_handler);
59
60 return 0;
61}
62
63void mdp5_irq_uninstall(struct msm_kms *kms)
64{
65 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
66 mdp5_enable(mdp5_kms);
67 mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_EN(0), 0x00000000);
68 mdp5_disable(mdp5_kms);
69}
70
71static void mdp5_irq_mdp(struct mdp_kms *mdp_kms)
72{
73 struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
74 struct drm_device *dev = mdp5_kms->dev;
75 struct msm_drm_private *priv = dev->dev_private;
76 unsigned int id;
77 uint32_t status, enable;
78
79 enable = mdp5_read(mdp5_kms, REG_MDP5_MDP_INTR_EN(0));
80 status = mdp5_read(mdp5_kms, REG_MDP5_MDP_INTR_STATUS(0)) & enable;
81 mdp5_write(mdp5_kms, REG_MDP5_MDP_INTR_CLEAR(0), status);
82
83 VERB("status=%08x", status);
84
85 mdp_dispatch_irqs(mdp_kms, status);
86
87 for (id = 0; id < priv->num_crtcs; id++)
88 if (status & mdp5_crtc_vblank(priv->crtcs[id]))
89 drm_handle_vblank(dev, id);
90}
91
92irqreturn_t mdp5_irq(struct msm_kms *kms)
93{
94 struct mdp_kms *mdp_kms = to_mdp_kms(kms);
95 struct mdp5_kms *mdp5_kms = to_mdp5_kms(mdp_kms);
96 uint32_t intr;
97
98 intr = mdp5_read(mdp5_kms, REG_MDSS_HW_INTR_STATUS);
99
100 VERB("intr=%08x", intr);
101
102 if (intr & MDSS_HW_INTR_STATUS_INTR_MDP) {
103 mdp5_irq_mdp(mdp_kms);
104 intr &= ~MDSS_HW_INTR_STATUS_INTR_MDP;
105 }
106
107 while (intr) {
108 irq_hw_number_t hwirq = fls(intr) - 1;
109 generic_handle_irq(irq_find_mapping(
110 mdp5_kms->irqcontroller.domain, hwirq));
111 intr &= ~(1 << hwirq);
112 }
113
114 return IRQ_HANDLED;
115}
116
117int mdp5_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
118{
119 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
120
121 mdp5_enable(mdp5_kms);
122 mdp_update_vblank_mask(to_mdp_kms(kms),
123 mdp5_crtc_vblank(crtc), true);
124 mdp5_disable(mdp5_kms);
125
126 return 0;
127}
128
129void mdp5_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
130{
131 struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(kms));
132
133 mdp5_enable(mdp5_kms);
134 mdp_update_vblank_mask(to_mdp_kms(kms),
135 mdp5_crtc_vblank(crtc), false);
136 mdp5_disable(mdp5_kms);
137}
138
139
140
141
142
143
144#define VALID_IRQS (MDSS_HW_INTR_STATUS_INTR_DSI0 | \
145 MDSS_HW_INTR_STATUS_INTR_DSI1 | \
146 MDSS_HW_INTR_STATUS_INTR_HDMI | \
147 MDSS_HW_INTR_STATUS_INTR_EDP)
148
149static void mdp5_hw_mask_irq(struct irq_data *irqd)
150{
151 struct mdp5_kms *mdp5_kms = irq_data_get_irq_chip_data(irqd);
152 smp_mb__before_atomic();
153 clear_bit(irqd->hwirq, &mdp5_kms->irqcontroller.enabled_mask);
154 smp_mb__after_atomic();
155}
156
157static void mdp5_hw_unmask_irq(struct irq_data *irqd)
158{
159 struct mdp5_kms *mdp5_kms = irq_data_get_irq_chip_data(irqd);
160 smp_mb__before_atomic();
161 set_bit(irqd->hwirq, &mdp5_kms->irqcontroller.enabled_mask);
162 smp_mb__after_atomic();
163}
164
165static struct irq_chip mdp5_hw_irq_chip = {
166 .name = "mdp5",
167 .irq_mask = mdp5_hw_mask_irq,
168 .irq_unmask = mdp5_hw_unmask_irq,
169};
170
171static int mdp5_hw_irqdomain_map(struct irq_domain *d,
172 unsigned int irq, irq_hw_number_t hwirq)
173{
174 struct mdp5_kms *mdp5_kms = d->host_data;
175
176 if (!(VALID_IRQS & (1 << hwirq)))
177 return -EPERM;
178
179 irq_set_chip_and_handler(irq, &mdp5_hw_irq_chip, handle_level_irq);
180 irq_set_chip_data(irq, mdp5_kms);
181
182 return 0;
183}
184
185static struct irq_domain_ops mdp5_hw_irqdomain_ops = {
186 .map = mdp5_hw_irqdomain_map,
187 .xlate = irq_domain_xlate_onecell,
188};
189
190
191int mdp5_irq_domain_init(struct mdp5_kms *mdp5_kms)
192{
193 struct device *dev = mdp5_kms->dev->dev;
194 struct irq_domain *d;
195
196 d = irq_domain_add_linear(dev->of_node, 32,
197 &mdp5_hw_irqdomain_ops, mdp5_kms);
198 if (!d) {
199 dev_err(dev, "mdp5 irq domain add failed\n");
200 return -ENXIO;
201 }
202
203 mdp5_kms->irqcontroller.enabled_mask = 0;
204 mdp5_kms->irqcontroller.domain = d;
205
206 return 0;
207}
208
209void mdp5_irq_domain_fini(struct mdp5_kms *mdp5_kms)
210{
211 if (mdp5_kms->irqcontroller.domain) {
212 irq_domain_remove(mdp5_kms->irqcontroller.domain);
213 mdp5_kms->irqcontroller.domain = NULL;
214 }
215}
216