1#ifndef __NVIF_CL5070_H__ 2#define __NVIF_CL5070_H__ 3 4#define NV50_DISP_MTHD 0x00 5 6struct nv50_disp_mthd_v0 { 7 __u8 version; 8#define NV50_DISP_SCANOUTPOS 0x00 9 __u8 method; 10 __u8 head; 11 __u8 pad03[5]; 12}; 13 14struct nv50_disp_scanoutpos_v0 { 15 __u8 version; 16 __u8 pad01[7]; 17 __s64 time[2]; 18 __u16 vblanks; 19 __u16 vblanke; 20 __u16 vtotal; 21 __u16 vline; 22 __u16 hblanks; 23 __u16 hblanke; 24 __u16 htotal; 25 __u16 hline; 26}; 27 28struct nv50_disp_mthd_v1 { 29 __u8 version; 30#define NV50_DISP_MTHD_V1_DAC_PWR 0x10 31#define NV50_DISP_MTHD_V1_DAC_LOAD 0x11 32#define NV50_DISP_MTHD_V1_SOR_PWR 0x20 33#define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 34#define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 35#define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 36#define NV50_DISP_MTHD_V1_SOR_DP_PWR 0x24 37#define NV50_DISP_MTHD_V1_PIOR_PWR 0x30 38 __u8 method; 39 __u16 hasht; 40 __u16 hashm; 41 __u8 pad06[2]; 42}; 43 44struct nv50_disp_dac_pwr_v0 { 45 __u8 version; 46 __u8 state; 47 __u8 data; 48 __u8 vsync; 49 __u8 hsync; 50 __u8 pad05[3]; 51}; 52 53struct nv50_disp_dac_load_v0 { 54 __u8 version; 55 __u8 load; 56 __u8 pad02[2]; 57 __u32 data; 58}; 59 60struct nv50_disp_sor_pwr_v0 { 61 __u8 version; 62 __u8 state; 63 __u8 pad02[6]; 64}; 65 66struct nv50_disp_sor_hda_eld_v0 { 67 __u8 version; 68 __u8 pad01[7]; 69 __u8 data[]; 70}; 71 72struct nv50_disp_sor_hdmi_pwr_v0 { 73 __u8 version; 74 __u8 state; 75 __u8 max_ac_packet; 76 __u8 rekey; 77 __u8 pad04[4]; 78}; 79 80struct nv50_disp_sor_lvds_script_v0 { 81 __u8 version; 82 __u8 pad01[1]; 83 __u16 script; 84 __u8 pad04[4]; 85}; 86 87struct nv50_disp_sor_dp_pwr_v0 { 88 __u8 version; 89 __u8 state; 90 __u8 pad02[6]; 91}; 92 93struct nv50_disp_pior_pwr_v0 { 94 __u8 version; 95 __u8 state; 96 __u8 type; 97 __u8 pad03[5]; 98}; 99#endif 100