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26#include <drm/drmP.h>
27#include <drm/drm_crtc_helper.h>
28#include <drm/drm_fb_helper.h>
29#include <drm/radeon_drm.h>
30#include <drm/drm_fixed.h>
31#include "radeon.h"
32#include "atom.h"
33#include "atom-bits.h"
34
35static void atombios_overscan_setup(struct drm_crtc *crtc,
36 struct drm_display_mode *mode,
37 struct drm_display_mode *adjusted_mode)
38{
39 struct drm_device *dev = crtc->dev;
40 struct radeon_device *rdev = dev->dev_private;
41 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
42 SET_CRTC_OVERSCAN_PS_ALLOCATION args;
43 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
44 int a1, a2;
45
46 memset(&args, 0, sizeof(args));
47
48 args.ucCRTC = radeon_crtc->crtc_id;
49
50 switch (radeon_crtc->rmx_type) {
51 case RMX_CENTER:
52 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
54 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
56 break;
57 case RMX_ASPECT:
58 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
59 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
60
61 if (a1 > a2) {
62 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
64 } else if (a2 > a1) {
65 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
67 }
68 break;
69 case RMX_FULL:
70 default:
71 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
72 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
73 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
74 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
75 break;
76 }
77 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
78}
79
80static void atombios_scaler_setup(struct drm_crtc *crtc)
81{
82 struct drm_device *dev = crtc->dev;
83 struct radeon_device *rdev = dev->dev_private;
84 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
85 ENABLE_SCALER_PS_ALLOCATION args;
86 int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
87 struct radeon_encoder *radeon_encoder =
88 to_radeon_encoder(radeon_crtc->encoder);
89
90 enum radeon_tv_std tv_std = TV_STD_NTSC;
91 bool is_tv = false, is_cv = false;
92
93 if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
94 return;
95
96 if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
97 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
98 tv_std = tv_dac->tv_std;
99 is_tv = true;
100 }
101
102 memset(&args, 0, sizeof(args));
103
104 args.ucScaler = radeon_crtc->crtc_id;
105
106 if (is_tv) {
107 switch (tv_std) {
108 case TV_STD_NTSC:
109 default:
110 args.ucTVStandard = ATOM_TV_NTSC;
111 break;
112 case TV_STD_PAL:
113 args.ucTVStandard = ATOM_TV_PAL;
114 break;
115 case TV_STD_PAL_M:
116 args.ucTVStandard = ATOM_TV_PALM;
117 break;
118 case TV_STD_PAL_60:
119 args.ucTVStandard = ATOM_TV_PAL60;
120 break;
121 case TV_STD_NTSC_J:
122 args.ucTVStandard = ATOM_TV_NTSCJ;
123 break;
124 case TV_STD_SCART_PAL:
125 args.ucTVStandard = ATOM_TV_PAL;
126 break;
127 case TV_STD_SECAM:
128 args.ucTVStandard = ATOM_TV_SECAM;
129 break;
130 case TV_STD_PAL_CN:
131 args.ucTVStandard = ATOM_TV_PALCN;
132 break;
133 }
134 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
135 } else if (is_cv) {
136 args.ucTVStandard = ATOM_TV_CV;
137 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
138 } else {
139 switch (radeon_crtc->rmx_type) {
140 case RMX_FULL:
141 args.ucEnable = ATOM_SCALER_EXPANSION;
142 break;
143 case RMX_CENTER:
144 args.ucEnable = ATOM_SCALER_CENTER;
145 break;
146 case RMX_ASPECT:
147 args.ucEnable = ATOM_SCALER_EXPANSION;
148 break;
149 default:
150 if (ASIC_IS_AVIVO(rdev))
151 args.ucEnable = ATOM_SCALER_DISABLE;
152 else
153 args.ucEnable = ATOM_SCALER_CENTER;
154 break;
155 }
156 }
157 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
158 if ((is_tv || is_cv)
159 && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
160 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
161 }
162}
163
164static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
165{
166 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
167 struct drm_device *dev = crtc->dev;
168 struct radeon_device *rdev = dev->dev_private;
169 int index =
170 GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
171 ENABLE_CRTC_PS_ALLOCATION args;
172
173 memset(&args, 0, sizeof(args));
174
175 args.ucCRTC = radeon_crtc->crtc_id;
176 args.ucEnable = lock;
177
178 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
179}
180
181static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
182{
183 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
184 struct drm_device *dev = crtc->dev;
185 struct radeon_device *rdev = dev->dev_private;
186 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
187 ENABLE_CRTC_PS_ALLOCATION args;
188
189 memset(&args, 0, sizeof(args));
190
191 args.ucCRTC = radeon_crtc->crtc_id;
192 args.ucEnable = state;
193
194 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
195}
196
197static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
198{
199 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
200 struct drm_device *dev = crtc->dev;
201 struct radeon_device *rdev = dev->dev_private;
202 int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
203 ENABLE_CRTC_PS_ALLOCATION args;
204
205 memset(&args, 0, sizeof(args));
206
207 args.ucCRTC = radeon_crtc->crtc_id;
208 args.ucEnable = state;
209
210 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
211}
212
213static const u32 vga_control_regs[6] =
214{
215 AVIVO_D1VGA_CONTROL,
216 AVIVO_D2VGA_CONTROL,
217 EVERGREEN_D3VGA_CONTROL,
218 EVERGREEN_D4VGA_CONTROL,
219 EVERGREEN_D5VGA_CONTROL,
220 EVERGREEN_D6VGA_CONTROL,
221};
222
223static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
224{
225 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
226 struct drm_device *dev = crtc->dev;
227 struct radeon_device *rdev = dev->dev_private;
228 int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
229 BLANK_CRTC_PS_ALLOCATION args;
230 u32 vga_control = 0;
231
232 memset(&args, 0, sizeof(args));
233
234 if (ASIC_IS_DCE8(rdev)) {
235 vga_control = RREG32(vga_control_regs[radeon_crtc->crtc_id]);
236 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control | 1);
237 }
238
239 args.ucCRTC = radeon_crtc->crtc_id;
240 args.ucBlanking = state;
241
242 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
243
244 if (ASIC_IS_DCE8(rdev)) {
245 WREG32(vga_control_regs[radeon_crtc->crtc_id], vga_control);
246 }
247}
248
249static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
250{
251 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
252 struct drm_device *dev = crtc->dev;
253 struct radeon_device *rdev = dev->dev_private;
254 int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
255 ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
256
257 memset(&args, 0, sizeof(args));
258
259 args.ucDispPipeId = radeon_crtc->crtc_id;
260 args.ucEnable = state;
261
262 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
263}
264
265void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
266{
267 struct drm_device *dev = crtc->dev;
268 struct radeon_device *rdev = dev->dev_private;
269 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
270
271 switch (mode) {
272 case DRM_MODE_DPMS_ON:
273 radeon_crtc->enabled = true;
274 atombios_enable_crtc(crtc, ATOM_ENABLE);
275 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
276 atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
277 atombios_blank_crtc(crtc, ATOM_DISABLE);
278 if (dev->num_crtcs > radeon_crtc->crtc_id)
279 drm_vblank_on(dev, radeon_crtc->crtc_id);
280 radeon_crtc_load_lut(crtc);
281 break;
282 case DRM_MODE_DPMS_STANDBY:
283 case DRM_MODE_DPMS_SUSPEND:
284 case DRM_MODE_DPMS_OFF:
285 if (dev->num_crtcs > radeon_crtc->crtc_id)
286 drm_vblank_off(dev, radeon_crtc->crtc_id);
287 if (radeon_crtc->enabled)
288 atombios_blank_crtc(crtc, ATOM_ENABLE);
289 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
290 atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
291 atombios_enable_crtc(crtc, ATOM_DISABLE);
292 radeon_crtc->enabled = false;
293 break;
294 }
295
296 radeon_pm_compute_clocks(rdev);
297}
298
299static void
300atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
301 struct drm_display_mode *mode)
302{
303 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
304 struct drm_device *dev = crtc->dev;
305 struct radeon_device *rdev = dev->dev_private;
306 SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
307 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
308 u16 misc = 0;
309
310 memset(&args, 0, sizeof(args));
311 args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
312 args.usH_Blanking_Time =
313 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
314 args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
315 args.usV_Blanking_Time =
316 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
317 args.usH_SyncOffset =
318 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
319 args.usH_SyncWidth =
320 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
321 args.usV_SyncOffset =
322 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
323 args.usV_SyncWidth =
324 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
325 args.ucH_Border = radeon_crtc->h_border;
326 args.ucV_Border = radeon_crtc->v_border;
327
328 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
329 misc |= ATOM_VSYNC_POLARITY;
330 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
331 misc |= ATOM_HSYNC_POLARITY;
332 if (mode->flags & DRM_MODE_FLAG_CSYNC)
333 misc |= ATOM_COMPOSITESYNC;
334 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
335 misc |= ATOM_INTERLACE;
336 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
337 misc |= ATOM_DOUBLE_CLOCK_MODE;
338 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
339 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
340
341 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
342 args.ucCRTC = radeon_crtc->crtc_id;
343
344 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
345}
346
347static void atombios_crtc_set_timing(struct drm_crtc *crtc,
348 struct drm_display_mode *mode)
349{
350 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
351 struct drm_device *dev = crtc->dev;
352 struct radeon_device *rdev = dev->dev_private;
353 SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
354 int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
355 u16 misc = 0;
356
357 memset(&args, 0, sizeof(args));
358 args.usH_Total = cpu_to_le16(mode->crtc_htotal);
359 args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
360 args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
361 args.usH_SyncWidth =
362 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
363 args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
364 args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
365 args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
366 args.usV_SyncWidth =
367 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
368
369 args.ucOverscanRight = radeon_crtc->h_border;
370 args.ucOverscanLeft = radeon_crtc->h_border;
371 args.ucOverscanBottom = radeon_crtc->v_border;
372 args.ucOverscanTop = radeon_crtc->v_border;
373
374 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
375 misc |= ATOM_VSYNC_POLARITY;
376 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
377 misc |= ATOM_HSYNC_POLARITY;
378 if (mode->flags & DRM_MODE_FLAG_CSYNC)
379 misc |= ATOM_COMPOSITESYNC;
380 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
381 misc |= ATOM_INTERLACE;
382 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
383 misc |= ATOM_DOUBLE_CLOCK_MODE;
384 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
385 misc |= ATOM_H_REPLICATIONBY2 | ATOM_V_REPLICATIONBY2;
386
387 args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
388 args.ucCRTC = radeon_crtc->crtc_id;
389
390 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
391}
392
393static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
394{
395 u32 ss_cntl;
396
397 if (ASIC_IS_DCE4(rdev)) {
398 switch (pll_id) {
399 case ATOM_PPLL1:
400 ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
401 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
402 WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
403 break;
404 case ATOM_PPLL2:
405 ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
406 ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
407 WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
408 break;
409 case ATOM_DCPLL:
410 case ATOM_PPLL_INVALID:
411 return;
412 }
413 } else if (ASIC_IS_AVIVO(rdev)) {
414 switch (pll_id) {
415 case ATOM_PPLL1:
416 ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
417 ss_cntl &= ~1;
418 WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
419 break;
420 case ATOM_PPLL2:
421 ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
422 ss_cntl &= ~1;
423 WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
424 break;
425 case ATOM_DCPLL:
426 case ATOM_PPLL_INVALID:
427 return;
428 }
429 }
430}
431
432
433union atom_enable_ss {
434 ENABLE_LVDS_SS_PARAMETERS lvds_ss;
435 ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
436 ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
437 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
438 ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
439};
440
441static void atombios_crtc_program_ss(struct radeon_device *rdev,
442 int enable,
443 int pll_id,
444 int crtc_id,
445 struct radeon_atom_ss *ss)
446{
447 unsigned i;
448 int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
449 union atom_enable_ss args;
450
451 if (enable) {
452
453
454
455
456
457 if (ss->percentage == 0)
458 return;
459 if (ss->type & ATOM_EXTERNAL_SS_MASK)
460 return;
461 } else {
462 for (i = 0; i < rdev->num_crtc; i++) {
463 if (rdev->mode_info.crtcs[i] &&
464 rdev->mode_info.crtcs[i]->enabled &&
465 i != crtc_id &&
466 pll_id == rdev->mode_info.crtcs[i]->pll_id) {
467
468
469
470
471 return;
472 }
473 }
474 }
475
476 memset(&args, 0, sizeof(args));
477
478 if (ASIC_IS_DCE5(rdev)) {
479 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
480 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
481 switch (pll_id) {
482 case ATOM_PPLL1:
483 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
484 break;
485 case ATOM_PPLL2:
486 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
487 break;
488 case ATOM_DCPLL:
489 args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
490 break;
491 case ATOM_PPLL_INVALID:
492 return;
493 }
494 args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
495 args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
496 args.v3.ucEnable = enable;
497 } else if (ASIC_IS_DCE4(rdev)) {
498 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
499 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
500 switch (pll_id) {
501 case ATOM_PPLL1:
502 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
503 break;
504 case ATOM_PPLL2:
505 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
506 break;
507 case ATOM_DCPLL:
508 args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
509 break;
510 case ATOM_PPLL_INVALID:
511 return;
512 }
513 args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
514 args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
515 args.v2.ucEnable = enable;
516 } else if (ASIC_IS_DCE3(rdev)) {
517 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
518 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
519 args.v1.ucSpreadSpectrumStep = ss->step;
520 args.v1.ucSpreadSpectrumDelay = ss->delay;
521 args.v1.ucSpreadSpectrumRange = ss->range;
522 args.v1.ucPpll = pll_id;
523 args.v1.ucEnable = enable;
524 } else if (ASIC_IS_AVIVO(rdev)) {
525 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
526 (ss->type & ATOM_EXTERNAL_SS_MASK)) {
527 atombios_disable_ss(rdev, pll_id);
528 return;
529 }
530 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
531 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
532 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
533 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
534 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
535 args.lvds_ss_2.ucEnable = enable;
536 } else {
537 if (enable == ATOM_DISABLE) {
538 atombios_disable_ss(rdev, pll_id);
539 return;
540 }
541 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
542 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
543 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
544 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
545 args.lvds_ss.ucEnable = enable;
546 }
547 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
548}
549
550union adjust_pixel_clock {
551 ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
552 ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
553};
554
555static u32 atombios_adjust_pll(struct drm_crtc *crtc,
556 struct drm_display_mode *mode)
557{
558 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
559 struct drm_device *dev = crtc->dev;
560 struct radeon_device *rdev = dev->dev_private;
561 struct drm_encoder *encoder = radeon_crtc->encoder;
562 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
563 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
564 u32 adjusted_clock = mode->clock;
565 int encoder_mode = atombios_get_encoder_mode(encoder);
566 u32 dp_clock = mode->clock;
567 u32 clock = mode->clock;
568 int bpc = radeon_crtc->bpc;
569 bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
570
571
572 radeon_crtc->pll_flags = 0;
573
574 if (ASIC_IS_AVIVO(rdev)) {
575 if ((rdev->family == CHIP_RS600) ||
576 (rdev->family == CHIP_RS690) ||
577 (rdev->family == CHIP_RS740))
578 radeon_crtc->pll_flags |= (
579 RADEON_PLL_PREFER_CLOSEST_LOWER);
580
581 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)
582 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
583 else
584 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
585
586 if (rdev->family < CHIP_RV770)
587 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
588
589 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
590 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
591
592 if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
593 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
594 if (ASIC_IS_DCE32(rdev) && mode->clock > 165000)
595 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
596 } else {
597 radeon_crtc->pll_flags |= RADEON_PLL_LEGACY;
598
599 if (mode->clock > 200000)
600 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
601 else
602 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
603 }
604
605 if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
606 (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
607 if (connector) {
608 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
609 struct radeon_connector_atom_dig *dig_connector =
610 radeon_connector->con_priv;
611
612 dp_clock = dig_connector->dp_clock;
613 }
614 }
615
616 if (radeon_encoder->is_mst_encoder) {
617 struct radeon_encoder_mst *mst_enc = radeon_encoder->enc_priv;
618 struct radeon_connector_atom_dig *dig_connector = mst_enc->connector->con_priv;
619
620 dp_clock = dig_connector->dp_clock;
621 }
622
623
624 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
625 if (radeon_crtc->ss_enabled) {
626 if (radeon_crtc->ss.refdiv) {
627 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
628 radeon_crtc->pll_reference_div = radeon_crtc->ss.refdiv;
629 if (ASIC_IS_AVIVO(rdev))
630 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
631 }
632 }
633 }
634
635 if (ASIC_IS_AVIVO(rdev)) {
636
637 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
638 adjusted_clock = mode->clock * 2;
639 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
640 radeon_crtc->pll_flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
641 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
642 radeon_crtc->pll_flags |= RADEON_PLL_IS_LCD;
643 } else {
644 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
645 radeon_crtc->pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
646 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
647 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
648 }
649
650
651 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
652 switch (bpc) {
653 case 8:
654 default:
655 break;
656 case 10:
657 clock = (clock * 5) / 4;
658 break;
659 case 12:
660 clock = (clock * 3) / 2;
661 break;
662 case 16:
663 clock = clock * 2;
664 break;
665 }
666 }
667
668
669
670
671
672 if (ASIC_IS_DCE3(rdev)) {
673 union adjust_pixel_clock args;
674 u8 frev, crev;
675 int index;
676
677 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
678 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
679 &crev))
680 return adjusted_clock;
681
682 memset(&args, 0, sizeof(args));
683
684 switch (frev) {
685 case 1:
686 switch (crev) {
687 case 1:
688 case 2:
689 args.v1.usPixelClock = cpu_to_le16(clock / 10);
690 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
691 args.v1.ucEncodeMode = encoder_mode;
692 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
693 args.v1.ucConfig |=
694 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
695
696 atom_execute_table(rdev->mode_info.atom_context,
697 index, (uint32_t *)&args);
698 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
699 break;
700 case 3:
701 args.v3.sInput.usPixelClock = cpu_to_le16(clock / 10);
702 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
703 args.v3.sInput.ucEncodeMode = encoder_mode;
704 args.v3.sInput.ucDispPllConfig = 0;
705 if (radeon_crtc->ss_enabled && radeon_crtc->ss.percentage)
706 args.v3.sInput.ucDispPllConfig |=
707 DISPPLL_CONFIG_SS_ENABLE;
708 if (ENCODER_MODE_IS_DP(encoder_mode)) {
709 args.v3.sInput.ucDispPllConfig |=
710 DISPPLL_CONFIG_COHERENT_MODE;
711
712 args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
713 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
714 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
715 if (dig->coherent_mode)
716 args.v3.sInput.ucDispPllConfig |=
717 DISPPLL_CONFIG_COHERENT_MODE;
718 if (is_duallink)
719 args.v3.sInput.ucDispPllConfig |=
720 DISPPLL_CONFIG_DUAL_LINK;
721 }
722 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
723 ENCODER_OBJECT_ID_NONE)
724 args.v3.sInput.ucExtTransmitterID =
725 radeon_encoder_get_dp_bridge_encoder_id(encoder);
726 else
727 args.v3.sInput.ucExtTransmitterID = 0;
728
729 atom_execute_table(rdev->mode_info.atom_context,
730 index, (uint32_t *)&args);
731 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
732 if (args.v3.sOutput.ucRefDiv) {
733 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
734 radeon_crtc->pll_flags |= RADEON_PLL_USE_REF_DIV;
735 radeon_crtc->pll_reference_div = args.v3.sOutput.ucRefDiv;
736 }
737 if (args.v3.sOutput.ucPostDiv) {
738 radeon_crtc->pll_flags |= RADEON_PLL_USE_FRAC_FB_DIV;
739 radeon_crtc->pll_flags |= RADEON_PLL_USE_POST_DIV;
740 radeon_crtc->pll_post_div = args.v3.sOutput.ucPostDiv;
741 }
742 break;
743 default:
744 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
745 return adjusted_clock;
746 }
747 break;
748 default:
749 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
750 return adjusted_clock;
751 }
752 }
753 return adjusted_clock;
754}
755
756union set_pixel_clock {
757 SET_PIXEL_CLOCK_PS_ALLOCATION base;
758 PIXEL_CLOCK_PARAMETERS v1;
759 PIXEL_CLOCK_PARAMETERS_V2 v2;
760 PIXEL_CLOCK_PARAMETERS_V3 v3;
761 PIXEL_CLOCK_PARAMETERS_V5 v5;
762 PIXEL_CLOCK_PARAMETERS_V6 v6;
763};
764
765
766
767
768static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
769 u32 dispclk)
770{
771 u8 frev, crev;
772 int index;
773 union set_pixel_clock args;
774
775 memset(&args, 0, sizeof(args));
776
777 index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
778 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
779 &crev))
780 return;
781
782 switch (frev) {
783 case 1:
784 switch (crev) {
785 case 5:
786
787
788
789 args.v5.ucCRTC = ATOM_CRTC_INVALID;
790 args.v5.usPixelClock = cpu_to_le16(dispclk);
791 args.v5.ucPpll = ATOM_DCPLL;
792 break;
793 case 6:
794
795
796
797 args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
798 if (ASIC_IS_DCE61(rdev) || ASIC_IS_DCE8(rdev))
799 args.v6.ucPpll = ATOM_EXT_PLL1;
800 else if (ASIC_IS_DCE6(rdev))
801 args.v6.ucPpll = ATOM_PPLL0;
802 else
803 args.v6.ucPpll = ATOM_DCPLL;
804 break;
805 default:
806 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
807 return;
808 }
809 break;
810 default:
811 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
812 return;
813 }
814 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
815}
816
817static void atombios_crtc_program_pll(struct drm_crtc *crtc,
818 u32 crtc_id,
819 int pll_id,
820 u32 encoder_mode,
821 u32 encoder_id,
822 u32 clock,
823 u32 ref_div,
824 u32 fb_div,
825 u32 frac_fb_div,
826 u32 post_div,
827 int bpc,
828 bool ss_enabled,
829 struct radeon_atom_ss *ss)
830{
831 struct drm_device *dev = crtc->dev;
832 struct radeon_device *rdev = dev->dev_private;
833 u8 frev, crev;
834 int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
835 union set_pixel_clock args;
836
837 memset(&args, 0, sizeof(args));
838
839 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
840 &crev))
841 return;
842
843 switch (frev) {
844 case 1:
845 switch (crev) {
846 case 1:
847 if (clock == ATOM_DISABLE)
848 return;
849 args.v1.usPixelClock = cpu_to_le16(clock / 10);
850 args.v1.usRefDiv = cpu_to_le16(ref_div);
851 args.v1.usFbDiv = cpu_to_le16(fb_div);
852 args.v1.ucFracFbDiv = frac_fb_div;
853 args.v1.ucPostDiv = post_div;
854 args.v1.ucPpll = pll_id;
855 args.v1.ucCRTC = crtc_id;
856 args.v1.ucRefDivSrc = 1;
857 break;
858 case 2:
859 args.v2.usPixelClock = cpu_to_le16(clock / 10);
860 args.v2.usRefDiv = cpu_to_le16(ref_div);
861 args.v2.usFbDiv = cpu_to_le16(fb_div);
862 args.v2.ucFracFbDiv = frac_fb_div;
863 args.v2.ucPostDiv = post_div;
864 args.v2.ucPpll = pll_id;
865 args.v2.ucCRTC = crtc_id;
866 args.v2.ucRefDivSrc = 1;
867 break;
868 case 3:
869 args.v3.usPixelClock = cpu_to_le16(clock / 10);
870 args.v3.usRefDiv = cpu_to_le16(ref_div);
871 args.v3.usFbDiv = cpu_to_le16(fb_div);
872 args.v3.ucFracFbDiv = frac_fb_div;
873 args.v3.ucPostDiv = post_div;
874 args.v3.ucPpll = pll_id;
875 if (crtc_id == ATOM_CRTC2)
876 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2;
877 else
878 args.v3.ucMiscInfo = PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1;
879 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
880 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
881 args.v3.ucTransmitterId = encoder_id;
882 args.v3.ucEncoderMode = encoder_mode;
883 break;
884 case 5:
885 args.v5.ucCRTC = crtc_id;
886 args.v5.usPixelClock = cpu_to_le16(clock / 10);
887 args.v5.ucRefDiv = ref_div;
888 args.v5.usFbDiv = cpu_to_le16(fb_div);
889 args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
890 args.v5.ucPostDiv = post_div;
891 args.v5.ucMiscInfo = 0;
892 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
893 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
894 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
895 switch (bpc) {
896 case 8:
897 default:
898 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
899 break;
900 case 10:
901
902 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_32BPP;
903 break;
904 case 12:
905
906 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
907 break;
908 }
909 }
910 args.v5.ucTransmitterID = encoder_id;
911 args.v5.ucEncoderMode = encoder_mode;
912 args.v5.ucPpll = pll_id;
913 break;
914 case 6:
915 args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
916 args.v6.ucRefDiv = ref_div;
917 args.v6.usFbDiv = cpu_to_le16(fb_div);
918 args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
919 args.v6.ucPostDiv = post_div;
920 args.v6.ucMiscInfo = 0;
921 if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
922 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
923 if (encoder_mode == ATOM_ENCODER_MODE_HDMI) {
924 switch (bpc) {
925 case 8:
926 default:
927 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
928 break;
929 case 10:
930 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6;
931 break;
932 case 12:
933 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6;
934 break;
935 case 16:
936 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
937 break;
938 }
939 }
940 args.v6.ucTransmitterID = encoder_id;
941 args.v6.ucEncoderMode = encoder_mode;
942 args.v6.ucPpll = pll_id;
943 break;
944 default:
945 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
946 return;
947 }
948 break;
949 default:
950 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
951 return;
952 }
953
954 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
955}
956
957static bool atombios_crtc_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
958{
959 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
960 struct drm_device *dev = crtc->dev;
961 struct radeon_device *rdev = dev->dev_private;
962 struct radeon_encoder *radeon_encoder =
963 to_radeon_encoder(radeon_crtc->encoder);
964 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
965
966 radeon_crtc->bpc = 8;
967 radeon_crtc->ss_enabled = false;
968
969 if (radeon_encoder->is_mst_encoder) {
970 radeon_dp_mst_prepare_pll(crtc, mode);
971 } else if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
972 (radeon_encoder_get_dp_bridge_encoder_id(radeon_crtc->encoder) != ENCODER_OBJECT_ID_NONE)) {
973 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
974 struct drm_connector *connector =
975 radeon_get_connector_for_encoder(radeon_crtc->encoder);
976 struct radeon_connector *radeon_connector =
977 to_radeon_connector(connector);
978 struct radeon_connector_atom_dig *dig_connector =
979 radeon_connector->con_priv;
980 int dp_clock;
981
982
983 radeon_connector->pixelclock_for_modeset = mode->clock;
984 radeon_crtc->bpc = radeon_get_monitor_bpc(connector);
985
986 switch (encoder_mode) {
987 case ATOM_ENCODER_MODE_DP_MST:
988 case ATOM_ENCODER_MODE_DP:
989
990 dp_clock = dig_connector->dp_clock / 10;
991 if (ASIC_IS_DCE4(rdev))
992 radeon_crtc->ss_enabled =
993 radeon_atombios_get_asic_ss_info(rdev, &radeon_crtc->ss,
994 ASIC_INTERNAL_SS_ON_DP,
995 dp_clock);
996 else {
997 if (dp_clock == 16200) {
998 radeon_crtc->ss_enabled =
999 radeon_atombios_get_ppll_ss_info(rdev,
1000 &radeon_crtc->ss,
1001 ATOM_DP_SS_ID2);
1002 if (!radeon_crtc->ss_enabled)
1003 radeon_crtc->ss_enabled =
1004 radeon_atombios_get_ppll_ss_info(rdev,
1005 &radeon_crtc->ss,
1006 ATOM_DP_SS_ID1);
1007 } else {
1008 radeon_crtc->ss_enabled =
1009 radeon_atombios_get_ppll_ss_info(rdev,
1010 &radeon_crtc->ss,
1011 ATOM_DP_SS_ID1);
1012 }
1013
1014 radeon_crtc->ss_enabled = false;
1015 }
1016 break;
1017 case ATOM_ENCODER_MODE_LVDS:
1018 if (ASIC_IS_DCE4(rdev))
1019 radeon_crtc->ss_enabled =
1020 radeon_atombios_get_asic_ss_info(rdev,
1021 &radeon_crtc->ss,
1022 dig->lcd_ss_id,
1023 mode->clock / 10);
1024 else
1025 radeon_crtc->ss_enabled =
1026 radeon_atombios_get_ppll_ss_info(rdev,
1027 &radeon_crtc->ss,
1028 dig->lcd_ss_id);
1029 break;
1030 case ATOM_ENCODER_MODE_DVI:
1031 if (ASIC_IS_DCE4(rdev))
1032 radeon_crtc->ss_enabled =
1033 radeon_atombios_get_asic_ss_info(rdev,
1034 &radeon_crtc->ss,
1035 ASIC_INTERNAL_SS_ON_TMDS,
1036 mode->clock / 10);
1037 break;
1038 case ATOM_ENCODER_MODE_HDMI:
1039 if (ASIC_IS_DCE4(rdev))
1040 radeon_crtc->ss_enabled =
1041 radeon_atombios_get_asic_ss_info(rdev,
1042 &radeon_crtc->ss,
1043 ASIC_INTERNAL_SS_ON_HDMI,
1044 mode->clock / 10);
1045 break;
1046 default:
1047 break;
1048 }
1049 }
1050
1051
1052 radeon_crtc->adjusted_clock = atombios_adjust_pll(crtc, mode);
1053
1054 return true;
1055}
1056
1057static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
1058{
1059 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1060 struct drm_device *dev = crtc->dev;
1061 struct radeon_device *rdev = dev->dev_private;
1062 struct radeon_encoder *radeon_encoder =
1063 to_radeon_encoder(radeon_crtc->encoder);
1064 u32 pll_clock = mode->clock;
1065 u32 clock = mode->clock;
1066 u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
1067 struct radeon_pll *pll;
1068 int encoder_mode = atombios_get_encoder_mode(radeon_crtc->encoder);
1069
1070
1071 if (ASIC_IS_DCE5(rdev) &&
1072 (encoder_mode == ATOM_ENCODER_MODE_HDMI) &&
1073 (radeon_crtc->bpc > 8))
1074 clock = radeon_crtc->adjusted_clock;
1075
1076 switch (radeon_crtc->pll_id) {
1077 case ATOM_PPLL1:
1078 pll = &rdev->clock.p1pll;
1079 break;
1080 case ATOM_PPLL2:
1081 pll = &rdev->clock.p2pll;
1082 break;
1083 case ATOM_DCPLL:
1084 case ATOM_PPLL_INVALID:
1085 default:
1086 pll = &rdev->clock.dcpll;
1087 break;
1088 }
1089
1090
1091 pll->flags = radeon_crtc->pll_flags;
1092 pll->reference_div = radeon_crtc->pll_reference_div;
1093 pll->post_div = radeon_crtc->pll_post_div;
1094
1095 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1096
1097 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1098 &fb_div, &frac_fb_div, &ref_div, &post_div);
1099 else if (ASIC_IS_AVIVO(rdev))
1100 radeon_compute_pll_avivo(pll, radeon_crtc->adjusted_clock, &pll_clock,
1101 &fb_div, &frac_fb_div, &ref_div, &post_div);
1102 else
1103 radeon_compute_pll_legacy(pll, radeon_crtc->adjusted_clock, &pll_clock,
1104 &fb_div, &frac_fb_div, &ref_div, &post_div);
1105
1106 atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id,
1107 radeon_crtc->crtc_id, &radeon_crtc->ss);
1108
1109 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1110 encoder_mode, radeon_encoder->encoder_id, clock,
1111 ref_div, fb_div, frac_fb_div, post_div,
1112 radeon_crtc->bpc, radeon_crtc->ss_enabled, &radeon_crtc->ss);
1113
1114 if (radeon_crtc->ss_enabled) {
1115
1116 if (ASIC_IS_DCE4(rdev)) {
1117 u32 step_size;
1118 u32 amount = (((fb_div * 10) + frac_fb_div) *
1119 (u32)radeon_crtc->ss.percentage) /
1120 (100 * (u32)radeon_crtc->ss.percentage_divider);
1121 radeon_crtc->ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1122 radeon_crtc->ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1123 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1124 if (radeon_crtc->ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1125 step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1126 (125 * 25 * pll->reference_freq / 100);
1127 else
1128 step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) /
1129 (125 * 25 * pll->reference_freq / 100);
1130 radeon_crtc->ss.step = step_size;
1131 }
1132
1133 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id,
1134 radeon_crtc->crtc_id, &radeon_crtc->ss);
1135 }
1136}
1137
1138static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1139 struct drm_framebuffer *fb,
1140 int x, int y, int atomic)
1141{
1142 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1143 struct drm_device *dev = crtc->dev;
1144 struct radeon_device *rdev = dev->dev_private;
1145 struct radeon_framebuffer *radeon_fb;
1146 struct drm_framebuffer *target_fb;
1147 struct drm_gem_object *obj;
1148 struct radeon_bo *rbo;
1149 uint64_t fb_location;
1150 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1151 unsigned bankw, bankh, mtaspect, tile_split;
1152 u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1153 u32 tmp, viewport_w, viewport_h;
1154 int r;
1155 bool bypass_lut = false;
1156
1157
1158 if (!atomic && !crtc->primary->fb) {
1159 DRM_DEBUG_KMS("No FB bound\n");
1160 return 0;
1161 }
1162
1163 if (atomic) {
1164 radeon_fb = to_radeon_framebuffer(fb);
1165 target_fb = fb;
1166 }
1167 else {
1168 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1169 target_fb = crtc->primary->fb;
1170 }
1171
1172
1173
1174
1175 obj = radeon_fb->obj;
1176 rbo = gem_to_radeon_bo(obj);
1177 r = radeon_bo_reserve(rbo, false);
1178 if (unlikely(r != 0))
1179 return r;
1180
1181 if (atomic)
1182 fb_location = radeon_bo_gpu_offset(rbo);
1183 else {
1184 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1185 if (unlikely(r != 0)) {
1186 radeon_bo_unreserve(rbo);
1187 return -EINVAL;
1188 }
1189 }
1190
1191 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1192 radeon_bo_unreserve(rbo);
1193
1194 switch (target_fb->pixel_format) {
1195 case DRM_FORMAT_C8:
1196 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1197 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1198 break;
1199 case DRM_FORMAT_XRGB4444:
1200 case DRM_FORMAT_ARGB4444:
1201 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1202 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB4444));
1203#ifdef __BIG_ENDIAN
1204 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1205#endif
1206 break;
1207 case DRM_FORMAT_XRGB1555:
1208 case DRM_FORMAT_ARGB1555:
1209 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1210 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1211#ifdef __BIG_ENDIAN
1212 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1213#endif
1214 break;
1215 case DRM_FORMAT_BGRX5551:
1216 case DRM_FORMAT_BGRA5551:
1217 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1218 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA5551));
1219#ifdef __BIG_ENDIAN
1220 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1221#endif
1222 break;
1223 case DRM_FORMAT_RGB565:
1224 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1225 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1226#ifdef __BIG_ENDIAN
1227 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1228#endif
1229 break;
1230 case DRM_FORMAT_XRGB8888:
1231 case DRM_FORMAT_ARGB8888:
1232 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1233 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1234#ifdef __BIG_ENDIAN
1235 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1236#endif
1237 break;
1238 case DRM_FORMAT_XRGB2101010:
1239 case DRM_FORMAT_ARGB2101010:
1240 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1241 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB2101010));
1242#ifdef __BIG_ENDIAN
1243 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1244#endif
1245
1246 bypass_lut = true;
1247 break;
1248 case DRM_FORMAT_BGRX1010102:
1249 case DRM_FORMAT_BGRA1010102:
1250 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1251 EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_BGRA1010102));
1252#ifdef __BIG_ENDIAN
1253 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1254#endif
1255
1256 bypass_lut = true;
1257 break;
1258 default:
1259 DRM_ERROR("Unsupported screen format %s\n",
1260 drm_get_format_name(target_fb->pixel_format));
1261 return -EINVAL;
1262 }
1263
1264 if (tiling_flags & RADEON_TILING_MACRO) {
1265 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1266
1267
1268 if (rdev->family >= CHIP_TAHITI) {
1269 unsigned index, num_banks;
1270
1271 if (rdev->family >= CHIP_BONAIRE) {
1272 unsigned tileb, tile_split_bytes;
1273
1274
1275 tile_split_bytes = 64 << tile_split;
1276 tileb = 8 * 8 * target_fb->bits_per_pixel / 8;
1277 tileb = min(tile_split_bytes, tileb);
1278
1279 for (index = 0; tileb > 64; index++)
1280 tileb >>= 1;
1281
1282 if (index >= 16) {
1283 DRM_ERROR("Wrong screen bpp (%u) or tile split (%u)\n",
1284 target_fb->bits_per_pixel, tile_split);
1285 return -EINVAL;
1286 }
1287
1288 num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3;
1289 } else {
1290 switch (target_fb->bits_per_pixel) {
1291 case 8:
1292 index = 10;
1293 break;
1294 case 16:
1295 index = SI_TILE_MODE_COLOR_2D_SCANOUT_16BPP;
1296 break;
1297 default:
1298 case 32:
1299 index = SI_TILE_MODE_COLOR_2D_SCANOUT_32BPP;
1300 break;
1301 }
1302
1303 num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3;
1304 }
1305
1306 fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks);
1307 } else {
1308
1309 if (rdev->family >= CHIP_CAYMAN)
1310 tmp = rdev->config.cayman.tile_config;
1311 else
1312 tmp = rdev->config.evergreen.tile_config;
1313
1314 switch ((tmp & 0xf0) >> 4) {
1315 case 0:
1316 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1317 break;
1318 case 1:
1319 default:
1320 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1321 break;
1322 case 2:
1323 fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1324 break;
1325 }
1326 }
1327
1328 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1329 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1330 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1331 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1332 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1333 if (rdev->family >= CHIP_BONAIRE) {
1334
1335 fb_format |= CIK_GRPH_MICRO_TILE_MODE(CIK_DISPLAY_MICRO_TILING);
1336 }
1337 } else if (tiling_flags & RADEON_TILING_MICRO)
1338 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1339
1340 if (rdev->family >= CHIP_BONAIRE) {
1341
1342
1343
1344 u32 pipe_config = (rdev->config.cik.tile_mode_array[10] >> 6) & 0x1f;
1345
1346 fb_format |= CIK_GRPH_PIPE_CONFIG(pipe_config);
1347 } else if ((rdev->family == CHIP_TAHITI) ||
1348 (rdev->family == CHIP_PITCAIRN))
1349 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P8_32x32_8x16);
1350 else if ((rdev->family == CHIP_VERDE) ||
1351 (rdev->family == CHIP_OLAND) ||
1352 (rdev->family == CHIP_HAINAN))
1353 fb_format |= SI_GRPH_PIPE_CONFIG(SI_ADDR_SURF_P4_8x16);
1354
1355 switch (radeon_crtc->crtc_id) {
1356 case 0:
1357 WREG32(AVIVO_D1VGA_CONTROL, 0);
1358 break;
1359 case 1:
1360 WREG32(AVIVO_D2VGA_CONTROL, 0);
1361 break;
1362 case 2:
1363 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1364 break;
1365 case 3:
1366 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1367 break;
1368 case 4:
1369 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1370 break;
1371 case 5:
1372 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1373 break;
1374 default:
1375 break;
1376 }
1377
1378 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1379 upper_32_bits(fb_location));
1380 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1381 upper_32_bits(fb_location));
1382 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1383 (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1384 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1385 (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1386 WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1387 WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1388
1389
1390
1391
1392
1393
1394 WREG32_P(EVERGREEN_GRPH_LUT_10BIT_BYPASS_CONTROL + radeon_crtc->crtc_offset,
1395 (bypass_lut ? EVERGREEN_LUT_10BIT_BYPASS_EN : 0),
1396 ~EVERGREEN_LUT_10BIT_BYPASS_EN);
1397
1398 if (bypass_lut)
1399 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1400
1401 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1402 WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1403 WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1404 WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1405 WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1406 WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1407
1408 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1409 WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1410 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1411
1412 if (rdev->family >= CHIP_BONAIRE)
1413 WREG32(CIK_LB_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1414 target_fb->height);
1415 else
1416 WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1417 target_fb->height);
1418 x &= ~3;
1419 y &= ~1;
1420 WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1421 (x << 16) | y);
1422 viewport_w = crtc->mode.hdisplay;
1423 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1424 if ((rdev->family >= CHIP_BONAIRE) &&
1425 (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE))
1426 viewport_h *= 2;
1427 WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1428 (viewport_w << 16) | viewport_h);
1429
1430
1431
1432 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1433 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1434 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1435
1436
1437 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1438
1439 if (!atomic && fb && fb != crtc->primary->fb) {
1440 radeon_fb = to_radeon_framebuffer(fb);
1441 rbo = gem_to_radeon_bo(radeon_fb->obj);
1442 r = radeon_bo_reserve(rbo, false);
1443 if (unlikely(r != 0))
1444 return r;
1445 radeon_bo_unpin(rbo);
1446 radeon_bo_unreserve(rbo);
1447 }
1448
1449
1450 radeon_bandwidth_update(rdev);
1451
1452 return 0;
1453}
1454
1455static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1456 struct drm_framebuffer *fb,
1457 int x, int y, int atomic)
1458{
1459 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1460 struct drm_device *dev = crtc->dev;
1461 struct radeon_device *rdev = dev->dev_private;
1462 struct radeon_framebuffer *radeon_fb;
1463 struct drm_gem_object *obj;
1464 struct radeon_bo *rbo;
1465 struct drm_framebuffer *target_fb;
1466 uint64_t fb_location;
1467 uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1468 u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1469 u32 tmp, viewport_w, viewport_h;
1470 int r;
1471 bool bypass_lut = false;
1472
1473
1474 if (!atomic && !crtc->primary->fb) {
1475 DRM_DEBUG_KMS("No FB bound\n");
1476 return 0;
1477 }
1478
1479 if (atomic) {
1480 radeon_fb = to_radeon_framebuffer(fb);
1481 target_fb = fb;
1482 }
1483 else {
1484 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
1485 target_fb = crtc->primary->fb;
1486 }
1487
1488 obj = radeon_fb->obj;
1489 rbo = gem_to_radeon_bo(obj);
1490 r = radeon_bo_reserve(rbo, false);
1491 if (unlikely(r != 0))
1492 return r;
1493
1494
1495
1496
1497 if (atomic)
1498 fb_location = radeon_bo_gpu_offset(rbo);
1499 else {
1500 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1501 if (unlikely(r != 0)) {
1502 radeon_bo_unreserve(rbo);
1503 return -EINVAL;
1504 }
1505 }
1506 radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1507 radeon_bo_unreserve(rbo);
1508
1509 switch (target_fb->pixel_format) {
1510 case DRM_FORMAT_C8:
1511 fb_format =
1512 AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1513 AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1514 break;
1515 case DRM_FORMAT_XRGB4444:
1516 case DRM_FORMAT_ARGB4444:
1517 fb_format =
1518 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1519 AVIVO_D1GRPH_CONTROL_16BPP_ARGB4444;
1520#ifdef __BIG_ENDIAN
1521 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1522#endif
1523 break;
1524 case DRM_FORMAT_XRGB1555:
1525 fb_format =
1526 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1527 AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1528#ifdef __BIG_ENDIAN
1529 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1530#endif
1531 break;
1532 case DRM_FORMAT_RGB565:
1533 fb_format =
1534 AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1535 AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1536#ifdef __BIG_ENDIAN
1537 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1538#endif
1539 break;
1540 case DRM_FORMAT_XRGB8888:
1541 case DRM_FORMAT_ARGB8888:
1542 fb_format =
1543 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1544 AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1545#ifdef __BIG_ENDIAN
1546 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1547#endif
1548 break;
1549 case DRM_FORMAT_XRGB2101010:
1550 case DRM_FORMAT_ARGB2101010:
1551 fb_format =
1552 AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1553 AVIVO_D1GRPH_CONTROL_32BPP_ARGB2101010;
1554#ifdef __BIG_ENDIAN
1555 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1556#endif
1557
1558 bypass_lut = true;
1559 break;
1560 default:
1561 DRM_ERROR("Unsupported screen format %s\n",
1562 drm_get_format_name(target_fb->pixel_format));
1563 return -EINVAL;
1564 }
1565
1566 if (rdev->family >= CHIP_R600) {
1567 if (tiling_flags & RADEON_TILING_MACRO)
1568 fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1569 else if (tiling_flags & RADEON_TILING_MICRO)
1570 fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1571 } else {
1572 if (tiling_flags & RADEON_TILING_MACRO)
1573 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1574
1575 if (tiling_flags & RADEON_TILING_MICRO)
1576 fb_format |= AVIVO_D1GRPH_TILED;
1577 }
1578
1579 if (radeon_crtc->crtc_id == 0)
1580 WREG32(AVIVO_D1VGA_CONTROL, 0);
1581 else
1582 WREG32(AVIVO_D2VGA_CONTROL, 0);
1583
1584 if (rdev->family >= CHIP_RV770) {
1585 if (radeon_crtc->crtc_id) {
1586 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1587 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1588 } else {
1589 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1590 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1591 }
1592 }
1593 WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1594 (u32) fb_location);
1595 WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1596 radeon_crtc->crtc_offset, (u32) fb_location);
1597 WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1598 if (rdev->family >= CHIP_R600)
1599 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1600
1601
1602 WREG32_P(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset,
1603 (bypass_lut ? AVIVO_LUT_10BIT_BYPASS_EN : 0), ~AVIVO_LUT_10BIT_BYPASS_EN);
1604
1605 if (bypass_lut)
1606 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
1607
1608 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1609 WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1610 WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1611 WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1612 WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1613 WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1614
1615 fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1616 WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1617 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1618
1619 WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1620 target_fb->height);
1621 x &= ~3;
1622 y &= ~1;
1623 WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1624 (x << 16) | y);
1625 viewport_w = crtc->mode.hdisplay;
1626 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1627 WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1628 (viewport_w << 16) | viewport_h);
1629
1630
1631
1632 tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1633 tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1634 WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1635
1636
1637 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 3);
1638
1639 if (!atomic && fb && fb != crtc->primary->fb) {
1640 radeon_fb = to_radeon_framebuffer(fb);
1641 rbo = gem_to_radeon_bo(radeon_fb->obj);
1642 r = radeon_bo_reserve(rbo, false);
1643 if (unlikely(r != 0))
1644 return r;
1645 radeon_bo_unpin(rbo);
1646 radeon_bo_unreserve(rbo);
1647 }
1648
1649
1650 radeon_bandwidth_update(rdev);
1651
1652 return 0;
1653}
1654
1655int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1656 struct drm_framebuffer *old_fb)
1657{
1658 struct drm_device *dev = crtc->dev;
1659 struct radeon_device *rdev = dev->dev_private;
1660
1661 if (ASIC_IS_DCE4(rdev))
1662 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1663 else if (ASIC_IS_AVIVO(rdev))
1664 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1665 else
1666 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1667}
1668
1669int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1670 struct drm_framebuffer *fb,
1671 int x, int y, enum mode_set_atomic state)
1672{
1673 struct drm_device *dev = crtc->dev;
1674 struct radeon_device *rdev = dev->dev_private;
1675
1676 if (ASIC_IS_DCE4(rdev))
1677 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1678 else if (ASIC_IS_AVIVO(rdev))
1679 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1680 else
1681 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1682}
1683
1684
1685static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1686{
1687 struct drm_device *dev = crtc->dev;
1688 struct radeon_device *rdev = dev->dev_private;
1689 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1690 u32 disp_merge_cntl;
1691
1692 switch (radeon_crtc->crtc_id) {
1693 case 0:
1694 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1695 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1696 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1697 break;
1698 case 1:
1699 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1700 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1701 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1702 WREG32(RADEON_FP_H2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1703 WREG32(RADEON_FP_V2_SYNC_STRT_WID, RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1704 break;
1705 }
1706}
1707
1708
1709
1710
1711
1712
1713
1714
1715static u32 radeon_get_pll_use_mask(struct drm_crtc *crtc)
1716{
1717 struct drm_device *dev = crtc->dev;
1718 struct drm_crtc *test_crtc;
1719 struct radeon_crtc *test_radeon_crtc;
1720 u32 pll_in_use = 0;
1721
1722 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1723 if (crtc == test_crtc)
1724 continue;
1725
1726 test_radeon_crtc = to_radeon_crtc(test_crtc);
1727 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1728 pll_in_use |= (1 << test_radeon_crtc->pll_id);
1729 }
1730 return pll_in_use;
1731}
1732
1733
1734
1735
1736
1737
1738
1739
1740
1741
1742static int radeon_get_shared_dp_ppll(struct drm_crtc *crtc)
1743{
1744 struct drm_device *dev = crtc->dev;
1745 struct radeon_device *rdev = dev->dev_private;
1746 struct drm_crtc *test_crtc;
1747 struct radeon_crtc *test_radeon_crtc;
1748
1749 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1750 if (crtc == test_crtc)
1751 continue;
1752 test_radeon_crtc = to_radeon_crtc(test_crtc);
1753 if (test_radeon_crtc->encoder &&
1754 ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1755
1756 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1757 test_radeon_crtc->pll_id == ATOM_PPLL2)
1758 continue;
1759
1760 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1761 return test_radeon_crtc->pll_id;
1762 }
1763 }
1764 return ATOM_PPLL_INVALID;
1765}
1766
1767
1768
1769
1770
1771
1772
1773
1774
1775
1776static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
1777{
1778 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1779 struct drm_device *dev = crtc->dev;
1780 struct radeon_device *rdev = dev->dev_private;
1781 struct drm_crtc *test_crtc;
1782 struct radeon_crtc *test_radeon_crtc;
1783 u32 adjusted_clock, test_adjusted_clock;
1784
1785 adjusted_clock = radeon_crtc->adjusted_clock;
1786
1787 if (adjusted_clock == 0)
1788 return ATOM_PPLL_INVALID;
1789
1790 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1791 if (crtc == test_crtc)
1792 continue;
1793 test_radeon_crtc = to_radeon_crtc(test_crtc);
1794 if (test_radeon_crtc->encoder &&
1795 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
1796
1797 if (ASIC_IS_DCE61(rdev) && !ASIC_IS_DCE8(rdev) &&
1798 test_radeon_crtc->pll_id == ATOM_PPLL2)
1799 continue;
1800
1801 if (test_radeon_crtc->connector == radeon_crtc->connector) {
1802
1803 if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
1804 return test_radeon_crtc->pll_id;
1805 }
1806
1807 test_adjusted_clock = test_radeon_crtc->adjusted_clock;
1808 if ((crtc->mode.clock == test_crtc->mode.clock) &&
1809 (adjusted_clock == test_adjusted_clock) &&
1810 (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
1811 (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
1812 return test_radeon_crtc->pll_id;
1813 }
1814 }
1815 return ATOM_PPLL_INVALID;
1816}
1817
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847
1848
1849
1850
1851
1852
1853
1854
1855static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1856{
1857 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1858 struct drm_device *dev = crtc->dev;
1859 struct radeon_device *rdev = dev->dev_private;
1860 struct radeon_encoder *radeon_encoder =
1861 to_radeon_encoder(radeon_crtc->encoder);
1862 u32 pll_in_use;
1863 int pll;
1864
1865 if (ASIC_IS_DCE8(rdev)) {
1866 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1867 if (rdev->clock.dp_extclk)
1868
1869 return ATOM_PPLL_INVALID;
1870 else {
1871
1872 pll = radeon_get_shared_dp_ppll(crtc);
1873 if (pll != ATOM_PPLL_INVALID)
1874 return pll;
1875 }
1876 } else {
1877
1878 pll = radeon_get_shared_nondp_ppll(crtc);
1879 if (pll != ATOM_PPLL_INVALID)
1880 return pll;
1881 }
1882
1883 if ((rdev->family == CHIP_KABINI) ||
1884 (rdev->family == CHIP_MULLINS)) {
1885
1886 pll_in_use = radeon_get_pll_use_mask(crtc);
1887 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1888 return ATOM_PPLL2;
1889 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1890 return ATOM_PPLL1;
1891 DRM_ERROR("unable to allocate a PPLL\n");
1892 return ATOM_PPLL_INVALID;
1893 } else {
1894
1895 pll_in_use = radeon_get_pll_use_mask(crtc);
1896 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1897 return ATOM_PPLL2;
1898 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1899 return ATOM_PPLL1;
1900 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1901 return ATOM_PPLL0;
1902 DRM_ERROR("unable to allocate a PPLL\n");
1903 return ATOM_PPLL_INVALID;
1904 }
1905 } else if (ASIC_IS_DCE61(rdev)) {
1906 struct radeon_encoder_atom_dig *dig =
1907 radeon_encoder->enc_priv;
1908
1909 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1910 (dig->linkb == false))
1911
1912 return ATOM_PPLL2;
1913 else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1914
1915 if (rdev->clock.dp_extclk)
1916
1917 return ATOM_PPLL_INVALID;
1918 else {
1919
1920 pll = radeon_get_shared_dp_ppll(crtc);
1921 if (pll != ATOM_PPLL_INVALID)
1922 return pll;
1923 }
1924 } else {
1925
1926 pll = radeon_get_shared_nondp_ppll(crtc);
1927 if (pll != ATOM_PPLL_INVALID)
1928 return pll;
1929 }
1930
1931 pll_in_use = radeon_get_pll_use_mask(crtc);
1932 if (!(pll_in_use & (1 << ATOM_PPLL0)))
1933 return ATOM_PPLL0;
1934 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1935 return ATOM_PPLL1;
1936 DRM_ERROR("unable to allocate a PPLL\n");
1937 return ATOM_PPLL_INVALID;
1938 } else if (ASIC_IS_DCE41(rdev)) {
1939
1940 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1941 if (rdev->clock.dp_extclk)
1942
1943 return ATOM_PPLL_INVALID;
1944 }
1945 pll_in_use = radeon_get_pll_use_mask(crtc);
1946 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1947 return ATOM_PPLL1;
1948 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1949 return ATOM_PPLL2;
1950 DRM_ERROR("unable to allocate a PPLL\n");
1951 return ATOM_PPLL_INVALID;
1952 } else if (ASIC_IS_DCE4(rdev)) {
1953
1954
1955
1956
1957
1958
1959
1960
1961
1962
1963 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
1964 if (rdev->clock.dp_extclk)
1965
1966 return ATOM_PPLL_INVALID;
1967 else if (ASIC_IS_DCE6(rdev))
1968
1969 return ATOM_PPLL0;
1970 else if (ASIC_IS_DCE5(rdev))
1971
1972 return ATOM_DCPLL;
1973 else {
1974
1975 pll = radeon_get_shared_dp_ppll(crtc);
1976 if (pll != ATOM_PPLL_INVALID)
1977 return pll;
1978 }
1979 } else {
1980
1981 pll = radeon_get_shared_nondp_ppll(crtc);
1982 if (pll != ATOM_PPLL_INVALID)
1983 return pll;
1984 }
1985
1986 pll_in_use = radeon_get_pll_use_mask(crtc);
1987 if (!(pll_in_use & (1 << ATOM_PPLL1)))
1988 return ATOM_PPLL1;
1989 if (!(pll_in_use & (1 << ATOM_PPLL2)))
1990 return ATOM_PPLL2;
1991 DRM_ERROR("unable to allocate a PPLL\n");
1992 return ATOM_PPLL_INVALID;
1993 } else {
1994
1995
1996
1997
1998
1999
2000
2001
2002
2003
2004
2005
2006
2007
2008
2009 return radeon_crtc->crtc_id;
2010 }
2011}
2012
2013void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
2014{
2015
2016 if (ASIC_IS_DCE6(rdev))
2017 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2018 else if (ASIC_IS_DCE4(rdev)) {
2019 struct radeon_atom_ss ss;
2020 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
2021 ASIC_INTERNAL_SS_ON_DCPLL,
2022 rdev->clock.default_dispclk);
2023 if (ss_enabled)
2024 atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
2025
2026 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
2027 if (ss_enabled)
2028 atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
2029 }
2030
2031}
2032
2033int atombios_crtc_mode_set(struct drm_crtc *crtc,
2034 struct drm_display_mode *mode,
2035 struct drm_display_mode *adjusted_mode,
2036 int x, int y, struct drm_framebuffer *old_fb)
2037{
2038 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2039 struct drm_device *dev = crtc->dev;
2040 struct radeon_device *rdev = dev->dev_private;
2041 struct radeon_encoder *radeon_encoder =
2042 to_radeon_encoder(radeon_crtc->encoder);
2043 bool is_tvcv = false;
2044
2045 if (radeon_encoder->active_device &
2046 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2047 is_tvcv = true;
2048
2049 if (!radeon_crtc->adjusted_clock)
2050 return -EINVAL;
2051
2052 atombios_crtc_set_pll(crtc, adjusted_mode);
2053
2054 if (ASIC_IS_DCE4(rdev))
2055 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2056 else if (ASIC_IS_AVIVO(rdev)) {
2057 if (is_tvcv)
2058 atombios_crtc_set_timing(crtc, adjusted_mode);
2059 else
2060 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2061 } else {
2062 atombios_crtc_set_timing(crtc, adjusted_mode);
2063 if (radeon_crtc->crtc_id == 0)
2064 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
2065 radeon_legacy_atom_fixup(crtc);
2066 }
2067 atombios_crtc_set_base(crtc, x, y, old_fb);
2068 atombios_overscan_setup(crtc, mode, adjusted_mode);
2069 atombios_scaler_setup(crtc);
2070 radeon_cursor_reset(crtc);
2071
2072 radeon_crtc->hw_mode = *adjusted_mode;
2073
2074 return 0;
2075}
2076
2077static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
2078 const struct drm_display_mode *mode,
2079 struct drm_display_mode *adjusted_mode)
2080{
2081 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_encoder *encoder;
2084
2085
2086 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2087 if (encoder->crtc == crtc) {
2088 radeon_crtc->encoder = encoder;
2089 radeon_crtc->connector = radeon_get_connector_for_encoder(encoder);
2090 break;
2091 }
2092 }
2093 if ((radeon_crtc->encoder == NULL) || (radeon_crtc->connector == NULL)) {
2094 radeon_crtc->encoder = NULL;
2095 radeon_crtc->connector = NULL;
2096 return false;
2097 }
2098 if (radeon_crtc->encoder) {
2099 struct radeon_encoder *radeon_encoder =
2100 to_radeon_encoder(radeon_crtc->encoder);
2101
2102 radeon_crtc->output_csc = radeon_encoder->output_csc;
2103 }
2104 if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2105 return false;
2106 if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
2107 return false;
2108
2109 radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
2110
2111 if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
2112 !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))
2113 return false;
2114
2115 return true;
2116}
2117
2118static void atombios_crtc_prepare(struct drm_crtc *crtc)
2119{
2120 struct drm_device *dev = crtc->dev;
2121 struct radeon_device *rdev = dev->dev_private;
2122
2123
2124 if (ASIC_IS_DCE6(rdev))
2125 atombios_powergate_crtc(crtc, ATOM_DISABLE);
2126
2127 atombios_lock_crtc(crtc, ATOM_ENABLE);
2128 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2129}
2130
2131static void atombios_crtc_commit(struct drm_crtc *crtc)
2132{
2133 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2134 atombios_lock_crtc(crtc, ATOM_DISABLE);
2135}
2136
2137static void atombios_crtc_disable(struct drm_crtc *crtc)
2138{
2139 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
2140 struct drm_device *dev = crtc->dev;
2141 struct radeon_device *rdev = dev->dev_private;
2142 struct radeon_atom_ss ss;
2143 int i;
2144
2145 atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2146 if (crtc->primary->fb) {
2147 int r;
2148 struct radeon_framebuffer *radeon_fb;
2149 struct radeon_bo *rbo;
2150
2151 radeon_fb = to_radeon_framebuffer(crtc->primary->fb);
2152 rbo = gem_to_radeon_bo(radeon_fb->obj);
2153 r = radeon_bo_reserve(rbo, false);
2154 if (unlikely(r))
2155 DRM_ERROR("failed to reserve rbo before unpin\n");
2156 else {
2157 radeon_bo_unpin(rbo);
2158 radeon_bo_unreserve(rbo);
2159 }
2160 }
2161
2162 if (ASIC_IS_DCE4(rdev))
2163 WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2164 else if (ASIC_IS_AVIVO(rdev))
2165 WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 0);
2166
2167 if (ASIC_IS_DCE6(rdev))
2168 atombios_powergate_crtc(crtc, ATOM_ENABLE);
2169
2170 for (i = 0; i < rdev->num_crtc; i++) {
2171 if (rdev->mode_info.crtcs[i] &&
2172 rdev->mode_info.crtcs[i]->enabled &&
2173 i != radeon_crtc->crtc_id &&
2174 radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
2175
2176
2177
2178 goto done;
2179 }
2180 }
2181
2182 switch (radeon_crtc->pll_id) {
2183 case ATOM_PPLL1:
2184 case ATOM_PPLL2:
2185
2186 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2187 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2188 break;
2189 case ATOM_PPLL0:
2190
2191 if ((rdev->family == CHIP_ARUBA) ||
2192 (rdev->family == CHIP_KAVERI) ||
2193 (rdev->family == CHIP_BONAIRE) ||
2194 (rdev->family == CHIP_HAWAII))
2195 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
2196 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2197 break;
2198 default:
2199 break;
2200 }
2201done:
2202 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2203 radeon_crtc->adjusted_clock = 0;
2204 radeon_crtc->encoder = NULL;
2205 radeon_crtc->connector = NULL;
2206}
2207
2208static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
2209 .dpms = atombios_crtc_dpms,
2210 .mode_fixup = atombios_crtc_mode_fixup,
2211 .mode_set = atombios_crtc_mode_set,
2212 .mode_set_base = atombios_crtc_set_base,
2213 .mode_set_base_atomic = atombios_crtc_set_base_atomic,
2214 .prepare = atombios_crtc_prepare,
2215 .commit = atombios_crtc_commit,
2216 .load_lut = radeon_crtc_load_lut,
2217 .disable = atombios_crtc_disable,
2218};
2219
2220void radeon_atombios_init_crtc(struct drm_device *dev,
2221 struct radeon_crtc *radeon_crtc)
2222{
2223 struct radeon_device *rdev = dev->dev_private;
2224
2225 if (ASIC_IS_DCE4(rdev)) {
2226 switch (radeon_crtc->crtc_id) {
2227 case 0:
2228 default:
2229 radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
2230 break;
2231 case 1:
2232 radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
2233 break;
2234 case 2:
2235 radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
2236 break;
2237 case 3:
2238 radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
2239 break;
2240 case 4:
2241 radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
2242 break;
2243 case 5:
2244 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
2245 break;
2246 }
2247 } else {
2248 if (radeon_crtc->crtc_id == 1)
2249 radeon_crtc->crtc_offset =
2250 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
2251 else
2252 radeon_crtc->crtc_offset = 0;
2253 }
2254 radeon_crtc->pll_id = ATOM_PPLL_INVALID;
2255 radeon_crtc->adjusted_clock = 0;
2256 radeon_crtc->encoder = NULL;
2257 radeon_crtc->connector = NULL;
2258 drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
2259}
2260
