LXR linux/drivers/gpu/drm/sti/sti

   1/*
   2 * Copyright (C) STMicroelectronics SA 2014
   3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
   4 *          Fabien Dessenne <fabien.dessenne@st.com>
   5 *          Vincent Abriou <vincent.abriou@st.com>
   6 *          for STMicroelectronics.
   7 * License terms:  GNU General Public License (GPL), version 2
   8 */
   9
  10#include <linux/module.h>
  11#include <linux/notifier.h>
  12#include <linux/platform_device.h>
  13
  14#include <drm/drmP.h>
  15
  16#include "sti_vtg.h"
  17
  18#define VTG_MODE_MASTER         0
  19#define VTG_MODE_SLAVE_BY_EXT0  1
  20
  21/* registers offset */
  22#define VTG_MODE            0x0000
  23#define VTG_CLKLN           0x0008
  24#define VTG_HLFLN           0x000C
  25#define VTG_DRST_AUTOC      0x0010
  26#define VTG_VID_TFO         0x0040
  27#define VTG_VID_TFS         0x0044
  28#define VTG_VID_BFO         0x0048
  29#define VTG_VID_BFS         0x004C
  30
  31#define VTG_HOST_ITS        0x0078
  32#define VTG_HOST_ITS_BCLR   0x007C
  33#define VTG_HOST_ITM_BCLR   0x0088
  34#define VTG_HOST_ITM_BSET   0x008C
  35
  36#define VTG_H_HD_1          0x00C0
  37#define VTG_TOP_V_VD_1      0x00C4
  38#define VTG_BOT_V_VD_1      0x00C8
  39#define VTG_TOP_V_HD_1      0x00CC
  40#define VTG_BOT_V_HD_1      0x00D0
  41
  42#define VTG_H_HD_2          0x00E0
  43#define VTG_TOP_V_VD_2      0x00E4
  44#define VTG_BOT_V_VD_2      0x00E8
  45#define VTG_TOP_V_HD_2      0x00EC
  46#define VTG_BOT_V_HD_2      0x00F0
  47
  48#define VTG_H_HD_3          0x0100
  49#define VTG_TOP_V_VD_3      0x0104
  50#define VTG_BOT_V_VD_3      0x0108
  51#define VTG_TOP_V_HD_3      0x010C
  52#define VTG_BOT_V_HD_3      0x0110
  53
  54#define VTG_H_HD_4          0x0120
  55#define VTG_TOP_V_VD_4      0x0124
  56#define VTG_BOT_V_VD_4      0x0128
  57#define VTG_TOP_V_HD_4      0x012c
  58#define VTG_BOT_V_HD_4      0x0130
  59
  60#define VTG_IRQ_BOTTOM      BIT(0)
  61#define VTG_IRQ_TOP         BIT(1)
  62#define VTG_IRQ_MASK        (VTG_IRQ_TOP | VTG_IRQ_BOTTOM)
  63
  64/* Delay introduced by the HDMI in nb of pixel */
  65#define HDMI_DELAY          (5)
  66
  67/* Delay introduced by the DVO in nb of pixel */
  68#define DVO_DELAY           (2)
  69
  70/* delay introduced by the Arbitrary Waveform Generator in nb of pixels */
  71#define AWG_DELAY_HD        (-9)
  72#define AWG_DELAY_ED        (-8)
  73#define AWG_DELAY_SD        (-7)
  74
  75LIST_HEAD(vtg_lookup);
  76
  77/*
  78 * STI VTG register offset structure
  79 *
  80 *@h_hd:     stores the VTG_H_HD_x     register offset
  81 *@top_v_vd: stores the VTG_TOP_V_VD_x register offset
  82 *@bot_v_vd: stores the VTG_BOT_V_VD_x register offset
  83 *@top_v_hd: stores the VTG_TOP_V_HD_x register offset
  84 *@bot_v_hd: stores the VTG_BOT_V_HD_x register offset
  85 */
  86struct sti_vtg_regs_offs {
  87        u32 h_hd;
  88        u32 top_v_vd;
  89        u32 bot_v_vd;
  90        u32 top_v_hd;
  91        u32 bot_v_hd;
  92};
  93
  94#define VTG_MAX_SYNC_OUTPUT 4
  95static const struct sti_vtg_regs_offs vtg_regs_offs[VTG_MAX_SYNC_OUTPUT] = {
  96        { VTG_H_HD_1,
  97          VTG_TOP_V_VD_1, VTG_BOT_V_VD_1, VTG_TOP_V_HD_1, VTG_BOT_V_HD_1 },
  98        { VTG_H_HD_2,
  99          VTG_TOP_V_VD_2, VTG_BOT_V_VD_2, VTG_TOP_V_HD_2, VTG_BOT_V_HD_2 },
 100        { VTG_H_HD_3,
 101          VTG_TOP_V_VD_3, VTG_BOT_V_VD_3, VTG_TOP_V_HD_3, VTG_BOT_V_HD_3 },
 102        { VTG_H_HD_4,
 103          VTG_TOP_V_VD_4, VTG_BOT_V_VD_4, VTG_TOP_V_HD_4, VTG_BOT_V_HD_4 }
 104};
 105
 106/*
 107 * STI VTG synchronisation parameters structure
 108 *
 109 *@hsync: sample number falling and rising edge
 110 *@vsync_line_top: vertical top field line number falling and rising edge
 111 *@vsync_line_bot: vertical bottom field line number falling and rising edge
 112 *@vsync_off_top: vertical top field sample number rising and falling edge
 113 *@vsync_off_bot: vertical bottom field sample number rising and falling edge
 114 */
 115struct sti_vtg_sync_params {
 116        u32 hsync;
 117        u32 vsync_line_top;
 118        u32 vsync_line_bot;
 119        u32 vsync_off_top;
 120        u32 vsync_off_bot;
 121};
 122
 123/**
 124 * STI VTG structure
 125 *
 126 * @dev: pointer to device driver
 127 * @np: device node
 128 * @regs: register mapping
 129 * @sync_params: synchronisation parameters used to generate timings
 130 * @irq: VTG irq
 131 * @irq_status: store the IRQ status value
 132 * @notifier_list: notifier callback
 133 * @crtc: the CRTC for vblank event
 134 * @slave: slave vtg
 135 * @link: List node to link the structure in lookup list
 136 */
 137struct sti_vtg {
 138        struct device *dev;
 139        struct device_node *np;
 140        void __iomem *regs;
 141        struct sti_vtg_sync_params sync_params[VTG_MAX_SYNC_OUTPUT];
 142        int irq;
 143        u32 irq_status;
 144        struct raw_notifier_head notifier_list;
 145        struct drm_crtc *crtc;
 146        struct sti_vtg *slave;
 147        struct list_head link;
 148};
 149
 150static void vtg_register(struct sti_vtg *vtg)
 151{
 152        list_add_tail(&vtg->link, &vtg_lookup);
 153}
 154
 155struct sti_vtg *of_vtg_find(struct device_node *np)
 156{
 157        struct sti_vtg *vtg;
 158
 159        list_for_each_entry(vtg, &vtg_lookup, link) {
 160                if (vtg->np == np)
 161                        return vtg;
 162        }
 163        return NULL;
 164}
 165
 166static void vtg_reset(struct sti_vtg *vtg)
 167{
 168        /* reset slave and then master */
 169        if (vtg->slave)
 170                vtg_reset(vtg->slave);
 171
 172        writel(1, vtg->regs + VTG_DRST_AUTOC);
 173}
 174
 175static void vtg_set_output_window(void __iomem *regs,
 176                                  const struct drm_display_mode *mode)
 177{
 178        u32 video_top_field_start;
 179        u32 video_top_field_stop;
 180        u32 video_bottom_field_start;
 181        u32 video_bottom_field_stop;
 182        u32 xstart = sti_vtg_get_pixel_number(*mode, 0);
 183        u32 ystart = sti_vtg_get_line_number(*mode, 0);
 184        u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
 185        u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
 186
 187        /* Set output window to fit the display mode selected */
 188        video_top_field_start = (ystart << 16) | xstart;
 189        video_top_field_stop = (ystop << 16) | xstop;
 190
 191        /* Only progressive supported for now */
 192        video_bottom_field_start = video_top_field_start;
 193        video_bottom_field_stop = video_top_field_stop;
 194
 195        writel(video_top_field_start, regs + VTG_VID_TFO);
 196        writel(video_top_field_stop, regs + VTG_VID_TFS);
 197        writel(video_bottom_field_start, regs + VTG_VID_BFO);
 198        writel(video_bottom_field_stop, regs + VTG_VID_BFS);
 199}
 200
 201static void vtg_set_hsync_vsync_pos(struct sti_vtg_sync_params *sync,
 202                                    int delay,
 203                                    const struct drm_display_mode *mode)
 204{
 205        long clocksperline, start, stop;
 206        u32 risesync_top, fallsync_top;
 207        u32 risesync_offs_top, fallsync_offs_top;
 208
 209        clocksperline = mode->htotal;
 210
 211        /* Get the hsync position */
 212        start = 0;
 213        stop = mode->hsync_end - mode->hsync_start;
 214
 215        start += delay;
 216        stop  += delay;
 217
 218        if (start < 0)
 219                start += clocksperline;
 220        else if (start >= clocksperline)
 221                start -= clocksperline;
 222
 223        if (stop < 0)
 224                stop += clocksperline;
 225        else if (stop >= clocksperline)
 226                stop -= clocksperline;
 227
 228        sync->hsync = (stop << 16) | start;
 229
 230        /* Get the vsync position */
 231        if (delay >= 0) {
 232                risesync_top = 1;
 233                fallsync_top = risesync_top;
 234                fallsync_top += mode->vsync_end - mode->vsync_start;
 235
 236                fallsync_offs_top = (u32)delay;
 237                risesync_offs_top = (u32)delay;
 238        } else {
 239                risesync_top = mode->vtotal;
 240                fallsync_top = mode->vsync_end - mode->vsync_start;
 241
 242                fallsync_offs_top = clocksperline + delay;
 243                risesync_offs_top = clocksperline + delay;
 244        }
 245
 246        sync->vsync_line_top = (fallsync_top << 16) | risesync_top;
 247        sync->vsync_off_top = (fallsync_offs_top << 16) | risesync_offs_top;
 248
 249        /* Only progressive supported for now */
 250        sync->vsync_line_bot = sync->vsync_line_top;
 251        sync->vsync_off_bot = sync->vsync_off_top;
 252}
 253
 254static void vtg_set_mode(struct sti_vtg *vtg,
 255                         int type,
 256                         struct sti_vtg_sync_params *sync,
 257                         const struct drm_display_mode *mode)
 258{
 259        unsigned int i;
 260
 261        if (vtg->slave)
 262                vtg_set_mode(vtg->slave, VTG_MODE_SLAVE_BY_EXT0,
 263                             vtg->sync_params, mode);
 264
 265        /* Set the number of clock cycles per line */
 266        writel(mode->htotal, vtg->regs + VTG_CLKLN);
 267
 268        /* Set Half Line Per Field (only progressive supported for now) */
 269        writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN);
 270
 271        /* Program output window */
 272        vtg_set_output_window(vtg->regs, mode);
 273
 274        /* Set hsync and vsync position for HDMI */
 275        vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDMI - 1], HDMI_DELAY, mode);
 276
 277        /* Set hsync and vsync position for HD DCS */
 278        vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDDCS - 1], 0, mode);
 279
 280        /* Set hsync and vsync position for HDF */
 281        vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDF - 1], AWG_DELAY_HD, mode);
 282
 283        /* Set hsync and vsync position for DVO */
 284        vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_DVO - 1], DVO_DELAY, mode);
 285
 286        /* Progam the syncs outputs */
 287        for (i = 0; i < VTG_MAX_SYNC_OUTPUT ; i++) {
 288                writel(sync[i].hsync,
 289                       vtg->regs + vtg_regs_offs[i].h_hd);
 290                writel(sync[i].vsync_line_top,
 291                       vtg->regs + vtg_regs_offs[i].top_v_vd);
 292                writel(sync[i].vsync_line_bot,
 293                       vtg->regs + vtg_regs_offs[i].bot_v_vd);
 294                writel(sync[i].vsync_off_top,
 295                       vtg->regs + vtg_regs_offs[i].top_v_hd);
 296                writel(sync[i].vsync_off_bot,
 297                       vtg->regs + vtg_regs_offs[i].bot_v_hd);
 298        }
 299
 300        /* mode */
 301        writel(type, vtg->regs + VTG_MODE);
 302}
 303
 304static void vtg_enable_irq(struct sti_vtg *vtg)
 305{
 306        /* clear interrupt status and mask */
 307        writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR);
 308        writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR);
 309        writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET);
 310}
 311
 312void sti_vtg_set_config(struct sti_vtg *vtg,
 313                const struct drm_display_mode *mode)
 314{
 315        /* write configuration */
 316        vtg_set_mode(vtg, VTG_MODE_MASTER, vtg->sync_params, mode);
 317
 318        vtg_reset(vtg);
 319
 320        /* enable irq for the vtg vblank synchro */
 321        if (vtg->slave)
 322                vtg_enable_irq(vtg->slave);
 323        else
 324                vtg_enable_irq(vtg);
 325}
 326
 327/**
 328 * sti_vtg_get_line_number
 329 *
 330 * @mode: display mode to be used
 331 * @y:    line
 332 *
 333 * Return the line number according to the display mode taking
 334 * into account the Sync and Back Porch information.
 335 * Video frame line numbers start at 1, y starts at 0.
 336 * In interlaced modes the start line is the field line number of the odd
 337 * field, but y is still defined as a progressive frame.
 338 */
 339u32 sti_vtg_get_line_number(struct drm_display_mode mode, int y)
 340{
 341        u32 start_line = mode.vtotal - mode.vsync_start + 1;
 342
 343        if (mode.flags & DRM_MODE_FLAG_INTERLACE)
 344                start_line *= 2;
 345
 346        return start_line + y;
 347}
 348
 349/**
 350 * sti_vtg_get_pixel_number
 351 *
 352 * @mode: display mode to be used
 353 * @x:    row
 354 *
 355 * Return the pixel number according to the display mode taking
 356 * into account the Sync and Back Porch information.
 357 * Pixels are counted from 0.
 358 */
 359u32 sti_vtg_get_pixel_number(struct drm_display_mode mode, int x)
 360{
 361        return mode.htotal - mode.hsync_start + x;
 362}
 363
 364int sti_vtg_register_client(struct sti_vtg *vtg, struct notifier_block *nb,
 365                            struct drm_crtc *crtc)
 366{
 367        if (vtg->slave)
 368                return sti_vtg_register_client(vtg->slave, nb, crtc);
 369
 370        vtg->crtc = crtc;
 371        return raw_notifier_chain_register(&vtg->notifier_list, nb);
 372}
 373
 374int sti_vtg_unregister_client(struct sti_vtg *vtg, struct notifier_block *nb)
 375{
 376        if (vtg->slave)
 377                return sti_vtg_unregister_client(vtg->slave, nb);
 378
 379        return raw_notifier_chain_unregister(&vtg->notifier_list, nb);
 380}
 381
 382static irqreturn_t vtg_irq_thread(int irq, void *arg)
 383{
 384        struct sti_vtg *vtg = arg;
 385        u32 event;
 386
 387        event = (vtg->irq_status & VTG_IRQ_TOP) ?
 388                VTG_TOP_FIELD_EVENT : VTG_BOTTOM_FIELD_EVENT;
 389
 390        raw_notifier_call_chain(&vtg->notifier_list, event, vtg->crtc);
 391
 392        return IRQ_HANDLED;
 393}
 394
 395static irqreturn_t vtg_irq(int irq, void *arg)
 396{
 397        struct sti_vtg *vtg = arg;
 398
 399        vtg->irq_status = readl(vtg->regs + VTG_HOST_ITS);
 400
 401        writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR);
 402
 403        /* force sync bus write */
 404        readl(vtg->regs + VTG_HOST_ITS);
 405
 406        return IRQ_WAKE_THREAD;
 407}
 408
 409static int vtg_probe(struct platform_device *pdev)
 410{
 411        struct device *dev = &pdev->dev;
 412        struct device_node *np;
 413        struct sti_vtg *vtg;
 414        struct resource *res;
 415        int ret;
 416
 417        vtg = devm_kzalloc(dev, sizeof(*vtg), GFP_KERNEL);
 418        if (!vtg)
 419                return -ENOMEM;
 420
 421        vtg->dev = dev;
 422        vtg->np = pdev->dev.of_node;
 423
 424        /* Get Memory ressources */
 425        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 426        if (!res) {
 427                DRM_ERROR("Get memory resource failed\n");
 428                return -ENOMEM;
 429        }
 430        vtg->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
 431
 432        np = of_parse_phandle(pdev->dev.of_node, "st,slave", 0);
 433        if (np) {
 434                vtg->slave = of_vtg_find(np);
 435
 436                if (!vtg->slave)
 437                        return -EPROBE_DEFER;
 438        } else {
 439                vtg->irq = platform_get_irq(pdev, 0);
 440                if (IS_ERR_VALUE(vtg->irq)) {
 441                        DRM_ERROR("Failed to get VTG interrupt\n");
 442                        return vtg->irq;
 443                }
 444
 445                RAW_INIT_NOTIFIER_HEAD(&vtg->notifier_list);
 446
 447                ret = devm_request_threaded_irq(dev, vtg->irq, vtg_irq,
 448                                vtg_irq_thread, IRQF_ONESHOT,
 449                                dev_name(dev), vtg);
 450                if (IS_ERR_VALUE(ret)) {
 451                        DRM_ERROR("Failed to register VTG interrupt\n");
 452                        return ret;
 453                }
 454        }
 455
 456        vtg_register(vtg);
 457        platform_set_drvdata(pdev, vtg);
 458
 459        DRM_INFO("%s %s\n", __func__, dev_name(vtg->dev));
 460
 461        return 0;
 462}
 463
 464static int vtg_remove(struct platform_device *pdev)
 465{
 466        return 0;
 467}
 468
 469static const struct of_device_id vtg_of_match[] = {
 470        { .compatible = "st,vtg", },
 471        { /* sentinel */ }
 472};
 473MODULE_DEVICE_TABLE(of, vtg_of_match);
 474
 475struct platform_driver sti_vtg_driver = {
 476        .driver = {
 477                .name = "sti-vtg",
 478                .owner = THIS_MODULE,
 479                .of_match_table = vtg_of_match,
 480        },
 481        .probe  = vtg_probe,
 482        .remove = vtg_remove,
 483};
 484
 485MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
 486MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
 487MODULE_LICENSE("GPL");
 488