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28#include "vmwgfx_kms.h"
29#include "device_include/svga3d_surfacedefs.h"
30#include <drm/drm_plane_helper.h>
31
32#define vmw_crtc_to_stdu(x) \
33 container_of(x, struct vmw_screen_target_display_unit, base.crtc)
34#define vmw_encoder_to_stdu(x) \
35 container_of(x, struct vmw_screen_target_display_unit, base.encoder)
36#define vmw_connector_to_stdu(x) \
37 container_of(x, struct vmw_screen_target_display_unit, base.connector)
38
39
40
41enum stdu_content_type {
42 SAME_AS_DISPLAY = 0,
43 SEPARATE_SURFACE,
44 SEPARATE_DMA
45};
46
47
48
49
50
51
52
53
54
55
56
57
58
59struct vmw_stdu_dirty {
60 struct vmw_kms_dirty base;
61 SVGA3dTransferType transfer;
62 s32 left, right, top, bottom;
63 u32 pitch;
64 union {
65 struct vmw_dma_buffer *buf;
66 u32 sid;
67 };
68};
69
70
71
72
73
74struct vmw_stdu_update {
75 SVGA3dCmdHeader header;
76 SVGA3dCmdUpdateGBScreenTarget body;
77};
78
79struct vmw_stdu_dma {
80 SVGA3dCmdHeader header;
81 SVGA3dCmdSurfaceDMA body;
82};
83
84struct vmw_stdu_surface_copy {
85 SVGA3dCmdHeader header;
86 SVGA3dCmdSurfaceCopy body;
87};
88
89
90
91
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95
96
97
98
99
100
101
102struct vmw_screen_target_display_unit {
103 struct vmw_display_unit base;
104
105 struct vmw_surface *display_srf;
106 enum stdu_content_type content_fb_type;
107
108 bool defined;
109};
110
111
112
113static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu);
114
115
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120
121
122
123
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125
126
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129
130
131static void vmw_stdu_unpin_display(struct vmw_screen_target_display_unit *stdu)
132{
133 if (stdu->display_srf) {
134 struct vmw_resource *res = &stdu->display_srf->res;
135
136 vmw_resource_unpin(res);
137 vmw_surface_unreference(&stdu->display_srf);
138 }
139}
140
141
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150
151
152
153static void vmw_stdu_crtc_destroy(struct drm_crtc *crtc)
154{
155 vmw_stdu_destroy(vmw_crtc_to_stdu(crtc));
156}
157
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160
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171
172
173static int vmw_stdu_define_st(struct vmw_private *dev_priv,
174 struct vmw_screen_target_display_unit *stdu,
175 struct drm_display_mode *mode,
176 int crtc_x, int crtc_y)
177{
178 struct {
179 SVGA3dCmdHeader header;
180 SVGA3dCmdDefineGBScreenTarget body;
181 } *cmd;
182
183 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
184
185 if (unlikely(cmd == NULL)) {
186 DRM_ERROR("Out of FIFO space defining Screen Target\n");
187 return -ENOMEM;
188 }
189
190 cmd->header.id = SVGA_3D_CMD_DEFINE_GB_SCREENTARGET;
191 cmd->header.size = sizeof(cmd->body);
192
193 cmd->body.stid = stdu->base.unit;
194 cmd->body.width = mode->hdisplay;
195 cmd->body.height = mode->vdisplay;
196 cmd->body.flags = (0 == cmd->body.stid) ? SVGA_STFLAG_PRIMARY : 0;
197 cmd->body.dpi = 0;
198 if (stdu->base.is_implicit) {
199 cmd->body.xRoot = crtc_x;
200 cmd->body.yRoot = crtc_y;
201 } else {
202 cmd->body.xRoot = stdu->base.gui_x;
203 cmd->body.yRoot = stdu->base.gui_y;
204 }
205 stdu->base.set_gui_x = cmd->body.xRoot;
206 stdu->base.set_gui_y = cmd->body.yRoot;
207
208 vmw_fifo_commit(dev_priv, sizeof(*cmd));
209
210 stdu->defined = true;
211
212 return 0;
213}
214
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225
226static int vmw_stdu_bind_st(struct vmw_private *dev_priv,
227 struct vmw_screen_target_display_unit *stdu,
228 struct vmw_resource *res)
229{
230 SVGA3dSurfaceImageId image;
231
232 struct {
233 SVGA3dCmdHeader header;
234 SVGA3dCmdBindGBScreenTarget body;
235 } *cmd;
236
237
238 if (!stdu->defined) {
239 DRM_ERROR("No screen target defined\n");
240 return -EINVAL;
241 }
242
243
244 memset(&image, 0, sizeof(image));
245 image.sid = res ? res->id : SVGA3D_INVALID_ID;
246
247 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
248
249 if (unlikely(cmd == NULL)) {
250 DRM_ERROR("Out of FIFO space binding a screen target\n");
251 return -ENOMEM;
252 }
253
254 cmd->header.id = SVGA_3D_CMD_BIND_GB_SCREENTARGET;
255 cmd->header.size = sizeof(cmd->body);
256
257 cmd->body.stid = stdu->base.unit;
258 cmd->body.image = image;
259
260 vmw_fifo_commit(dev_priv, sizeof(*cmd));
261
262 return 0;
263}
264
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273
274
275
276static void vmw_stdu_populate_update(void *cmd, int unit,
277 s32 left, s32 right, s32 top, s32 bottom)
278{
279 struct vmw_stdu_update *update = cmd;
280
281 update->header.id = SVGA_3D_CMD_UPDATE_GB_SCREENTARGET;
282 update->header.size = sizeof(update->body);
283
284 update->body.stid = unit;
285 update->body.rect.x = left;
286 update->body.rect.y = top;
287 update->body.rect.w = right - left;
288 update->body.rect.h = bottom - top;
289}
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302
303
304static int vmw_stdu_update_st(struct vmw_private *dev_priv,
305 struct vmw_screen_target_display_unit *stdu)
306{
307 struct vmw_stdu_update *cmd;
308 struct drm_crtc *crtc = &stdu->base.crtc;
309
310 if (!stdu->defined) {
311 DRM_ERROR("No screen target defined");
312 return -EINVAL;
313 }
314
315 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
316
317 if (unlikely(cmd == NULL)) {
318 DRM_ERROR("Out of FIFO space updating a Screen Target\n");
319 return -ENOMEM;
320 }
321
322 vmw_stdu_populate_update(cmd, stdu->base.unit, 0, crtc->mode.hdisplay,
323 0, crtc->mode.vdisplay);
324
325 vmw_fifo_commit(dev_priv, sizeof(*cmd));
326
327 return 0;
328}
329
330
331
332
333
334
335
336
337
338static int vmw_stdu_destroy_st(struct vmw_private *dev_priv,
339 struct vmw_screen_target_display_unit *stdu)
340{
341 int ret;
342
343 struct {
344 SVGA3dCmdHeader header;
345 SVGA3dCmdDestroyGBScreenTarget body;
346 } *cmd;
347
348
349
350 if (unlikely(!stdu->defined))
351 return 0;
352
353 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
354
355 if (unlikely(cmd == NULL)) {
356 DRM_ERROR("Out of FIFO space, screen target not destroyed\n");
357 return -ENOMEM;
358 }
359
360 cmd->header.id = SVGA_3D_CMD_DESTROY_GB_SCREENTARGET;
361 cmd->header.size = sizeof(cmd->body);
362
363 cmd->body.stid = stdu->base.unit;
364
365 vmw_fifo_commit(dev_priv, sizeof(*cmd));
366
367
368 ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);
369 if (unlikely(ret != 0))
370 DRM_ERROR("Failed to sync with HW");
371
372 stdu->defined = false;
373
374 return ret;
375}
376
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386
387
388static int vmw_stdu_bind_fb(struct vmw_private *dev_priv,
389 struct drm_crtc *crtc,
390 struct drm_display_mode *mode,
391 struct drm_framebuffer *new_fb)
392{
393 struct vmw_screen_target_display_unit *stdu = vmw_crtc_to_stdu(crtc);
394 struct vmw_framebuffer *vfb = vmw_framebuffer_to_vfb(new_fb);
395 struct vmw_surface *new_display_srf = NULL;
396 enum stdu_content_type new_content_type;
397 struct vmw_framebuffer_surface *new_vfbs;
398 int ret;
399
400 WARN_ON_ONCE(!stdu->defined);
401
402 if (!vfb->dmabuf && new_fb->width == mode->hdisplay &&
403 new_fb->height == mode->vdisplay)
404 new_content_type = SAME_AS_DISPLAY;
405 else if (vfb->dmabuf)
406 new_content_type = SEPARATE_DMA;
407 else
408 new_content_type = SEPARATE_SURFACE;
409
410 if (new_content_type != SAME_AS_DISPLAY &&
411 !stdu->display_srf) {
412 struct vmw_surface content_srf;
413 struct drm_vmw_size display_base_size = {0};
414
415 display_base_size.width = mode->hdisplay;
416 display_base_size.height = mode->vdisplay;
417 display_base_size.depth = 1;
418
419
420
421
422
423 if (new_content_type == SEPARATE_DMA) {
424
425 switch (new_fb->bits_per_pixel) {
426 case 32:
427 content_srf.format = SVGA3D_X8R8G8B8;
428 break;
429
430 case 16:
431 content_srf.format = SVGA3D_R5G6B5;
432 break;
433
434 case 8:
435 content_srf.format = SVGA3D_P8;
436 break;
437
438 default:
439 DRM_ERROR("Invalid format\n");
440 return -EINVAL;
441 }
442
443 content_srf.flags = 0;
444 content_srf.mip_levels[0] = 1;
445 content_srf.multisample_count = 0;
446 } else {
447 new_vfbs = vmw_framebuffer_to_vfbs(new_fb);
448 content_srf = *new_vfbs->surface;
449 }
450
451
452 ret = vmw_surface_gb_priv_define(crtc->dev,
453 0,
454 content_srf.flags,
455 content_srf.format,
456 true,
457 content_srf.mip_levels[0],
458 content_srf.multisample_count,
459 0,
460 display_base_size,
461 &new_display_srf);
462 if (unlikely(ret != 0)) {
463 DRM_ERROR("Could not allocate screen target surface.\n");
464 return ret;
465 }
466 } else if (new_content_type == SAME_AS_DISPLAY) {
467 new_vfbs = vmw_framebuffer_to_vfbs(new_fb);
468 new_display_srf = vmw_surface_reference(new_vfbs->surface);
469 }
470
471 if (new_display_srf) {
472
473 ret = vmw_resource_pin(&new_display_srf->res, false);
474 if (ret)
475 goto out_srf_unref;
476
477 ret = vmw_stdu_bind_st(dev_priv, stdu, &new_display_srf->res);
478 if (ret)
479 goto out_srf_unpin;
480
481
482 vmw_stdu_unpin_display(stdu);
483
484
485 stdu->display_srf = new_display_srf;
486 new_display_srf = NULL;
487 }
488
489 crtc->primary->fb = new_fb;
490 stdu->content_fb_type = new_content_type;
491 return 0;
492
493out_srf_unpin:
494 vmw_resource_unpin(&new_display_srf->res);
495out_srf_unref:
496 vmw_surface_unreference(&new_display_srf);
497 return ret;
498}
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510
511
512static int vmw_stdu_crtc_set_config(struct drm_mode_set *set)
513{
514 struct vmw_private *dev_priv;
515 struct vmw_framebuffer *vfb;
516 struct vmw_screen_target_display_unit *stdu;
517 struct drm_display_mode *mode;
518 struct drm_framebuffer *new_fb;
519 struct drm_crtc *crtc;
520 struct drm_encoder *encoder;
521 struct drm_connector *connector;
522 bool turning_off;
523 int ret;
524
525
526 if (!set || !set->crtc)
527 return -EINVAL;
528
529 crtc = set->crtc;
530 stdu = vmw_crtc_to_stdu(crtc);
531 mode = set->mode;
532 new_fb = set->fb;
533 dev_priv = vmw_priv(crtc->dev);
534 turning_off = set->num_connectors == 0 || !mode || !new_fb;
535 vfb = (new_fb) ? vmw_framebuffer_to_vfb(new_fb) : NULL;
536
537 if (set->num_connectors > 1) {
538 DRM_ERROR("Too many connectors\n");
539 return -EINVAL;
540 }
541
542 if (set->num_connectors == 1 &&
543 set->connectors[0] != &stdu->base.connector) {
544 DRM_ERROR("Connectors don't match %p %p\n",
545 set->connectors[0], &stdu->base.connector);
546 return -EINVAL;
547 }
548
549 if (!turning_off && (set->x + mode->hdisplay > new_fb->width ||
550 set->y + mode->vdisplay > new_fb->height)) {
551 DRM_ERROR("Set outside of framebuffer\n");
552 return -EINVAL;
553 }
554
555
556 if (!turning_off && stdu->base.is_implicit && dev_priv->implicit_fb &&
557 !(dev_priv->num_implicit == 1 && stdu->base.active_implicit)
558 && dev_priv->implicit_fb != vfb) {
559 DRM_ERROR("Multiple implicit framebuffers not supported.\n");
560 return -EINVAL;
561 }
562
563
564 connector = &stdu->base.connector;
565 encoder = &stdu->base.encoder;
566
567 if (stdu->defined) {
568 ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);
569 if (ret)
570 return ret;
571
572 vmw_stdu_unpin_display(stdu);
573 (void) vmw_stdu_update_st(dev_priv, stdu);
574 vmw_kms_del_active(dev_priv, &stdu->base);
575
576 ret = vmw_stdu_destroy_st(dev_priv, stdu);
577 if (ret)
578 return ret;
579
580 crtc->primary->fb = NULL;
581 crtc->enabled = false;
582 encoder->crtc = NULL;
583 connector->encoder = NULL;
584 stdu->content_fb_type = SAME_AS_DISPLAY;
585 crtc->x = set->x;
586 crtc->y = set->y;
587 }
588
589 if (turning_off)
590 return 0;
591
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606 vmw_svga_enable(dev_priv);
607 ret = vmw_stdu_define_st(dev_priv, stdu, mode, set->x, set->y);
608 if (ret)
609 return ret;
610
611 crtc->x = set->x;
612 crtc->y = set->y;
613 crtc->mode = *mode;
614
615 ret = vmw_stdu_bind_fb(dev_priv, crtc, mode, new_fb);
616 if (ret)
617 return ret;
618
619 vmw_kms_add_active(dev_priv, &stdu->base, vfb);
620 crtc->enabled = true;
621 connector->encoder = encoder;
622 encoder->crtc = crtc;
623
624 return 0;
625}
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646static int vmw_stdu_crtc_page_flip(struct drm_crtc *crtc,
647 struct drm_framebuffer *new_fb,
648 struct drm_pending_vblank_event *event,
649 uint32_t flags)
650
651{
652 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
653 struct vmw_screen_target_display_unit *stdu;
654 struct drm_vmw_rect vclips;
655 struct vmw_framebuffer *vfb = vmw_framebuffer_to_vfb(new_fb);
656 int ret;
657
658 dev_priv = vmw_priv(crtc->dev);
659 stdu = vmw_crtc_to_stdu(crtc);
660
661 if (!stdu->defined || !vmw_kms_crtc_flippable(dev_priv, crtc))
662 return -EINVAL;
663
664 ret = vmw_stdu_bind_fb(dev_priv, crtc, &crtc->mode, new_fb);
665 if (ret)
666 return ret;
667
668 if (stdu->base.is_implicit)
669 vmw_kms_update_implicit_fb(dev_priv, crtc);
670
671 vclips.x = crtc->x;
672 vclips.y = crtc->y;
673 vclips.w = crtc->mode.hdisplay;
674 vclips.h = crtc->mode.vdisplay;
675 if (vfb->dmabuf)
676 ret = vmw_kms_stdu_dma(dev_priv, NULL, vfb, NULL, NULL, &vclips,
677 1, 1, true, false);
678 else
679 ret = vmw_kms_stdu_surface_dirty(dev_priv, vfb, NULL, &vclips,
680 NULL, 0, 0, 1, 1, NULL);
681 if (ret)
682 return ret;
683
684 if (event) {
685 struct vmw_fence_obj *fence = NULL;
686 struct drm_file *file_priv = event->base.file_priv;
687
688 vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);
689 if (!fence)
690 return -ENOMEM;
691
692 ret = vmw_event_fence_action_queue(file_priv, fence,
693 &event->base,
694 &event->event.tv_sec,
695 &event->event.tv_usec,
696 true);
697 vmw_fence_obj_unreference(&fence);
698 } else {
699 vmw_fifo_flush(dev_priv, false);
700 }
701
702 return 0;
703}
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712
713
714static void vmw_stdu_dmabuf_clip(struct vmw_kms_dirty *dirty)
715{
716 struct vmw_stdu_dirty *ddirty =
717 container_of(dirty, struct vmw_stdu_dirty, base);
718 struct vmw_stdu_dma *cmd = dirty->cmd;
719 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
720
721 blit += dirty->num_hits;
722 blit->srcx = dirty->fb_x;
723 blit->srcy = dirty->fb_y;
724 blit->x = dirty->unit_x1;
725 blit->y = dirty->unit_y1;
726 blit->d = 1;
727 blit->w = dirty->unit_x2 - dirty->unit_x1;
728 blit->h = dirty->unit_y2 - dirty->unit_y1;
729 dirty->num_hits++;
730
731 if (ddirty->transfer != SVGA3D_WRITE_HOST_VRAM)
732 return;
733
734
735 ddirty->left = min_t(s32, ddirty->left, dirty->unit_x1);
736 ddirty->top = min_t(s32, ddirty->top, dirty->unit_y1);
737 ddirty->right = max_t(s32, ddirty->right, dirty->unit_x2);
738 ddirty->bottom = max_t(s32, ddirty->bottom, dirty->unit_y2);
739}
740
741
742
743
744
745
746
747
748
749static void vmw_stdu_dmabuf_fifo_commit(struct vmw_kms_dirty *dirty)
750{
751 struct vmw_stdu_dirty *ddirty =
752 container_of(dirty, struct vmw_stdu_dirty, base);
753 struct vmw_screen_target_display_unit *stdu =
754 container_of(dirty->unit, typeof(*stdu), base);
755 struct vmw_stdu_dma *cmd = dirty->cmd;
756 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
757 SVGA3dCmdSurfaceDMASuffix *suffix =
758 (SVGA3dCmdSurfaceDMASuffix *) &blit[dirty->num_hits];
759 size_t blit_size = sizeof(*blit) * dirty->num_hits + sizeof(*suffix);
760
761 if (!dirty->num_hits) {
762 vmw_fifo_commit(dirty->dev_priv, 0);
763 return;
764 }
765
766 cmd->header.id = SVGA_3D_CMD_SURFACE_DMA;
767 cmd->header.size = sizeof(cmd->body) + blit_size;
768 vmw_bo_get_guest_ptr(&ddirty->buf->base, &cmd->body.guest.ptr);
769 cmd->body.guest.pitch = ddirty->pitch;
770 cmd->body.host.sid = stdu->display_srf->res.id;
771 cmd->body.host.face = 0;
772 cmd->body.host.mipmap = 0;
773 cmd->body.transfer = ddirty->transfer;
774 suffix->suffixSize = sizeof(*suffix);
775 suffix->maximumOffset = ddirty->buf->base.num_pages * PAGE_SIZE;
776
777 if (ddirty->transfer == SVGA3D_WRITE_HOST_VRAM) {
778 blit_size += sizeof(struct vmw_stdu_update);
779
780 vmw_stdu_populate_update(&suffix[1], stdu->base.unit,
781 ddirty->left, ddirty->right,
782 ddirty->top, ddirty->bottom);
783 }
784
785 vmw_fifo_commit(dirty->dev_priv, sizeof(*cmd) + blit_size);
786
787 ddirty->left = ddirty->top = S32_MAX;
788 ddirty->right = ddirty->bottom = S32_MIN;
789}
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814int vmw_kms_stdu_dma(struct vmw_private *dev_priv,
815 struct drm_file *file_priv,
816 struct vmw_framebuffer *vfb,
817 struct drm_vmw_fence_rep __user *user_fence_rep,
818 struct drm_clip_rect *clips,
819 struct drm_vmw_rect *vclips,
820 uint32_t num_clips,
821 int increment,
822 bool to_surface,
823 bool interruptible)
824{
825 struct vmw_dma_buffer *buf =
826 container_of(vfb, struct vmw_framebuffer_dmabuf, base)->buffer;
827 struct vmw_stdu_dirty ddirty;
828 int ret;
829
830 ret = vmw_kms_helper_buffer_prepare(dev_priv, buf, interruptible,
831 false);
832 if (ret)
833 return ret;
834
835 ddirty.transfer = (to_surface) ? SVGA3D_WRITE_HOST_VRAM :
836 SVGA3D_READ_HOST_VRAM;
837 ddirty.left = ddirty.top = S32_MAX;
838 ddirty.right = ddirty.bottom = S32_MIN;
839 ddirty.pitch = vfb->base.pitches[0];
840 ddirty.buf = buf;
841 ddirty.base.fifo_commit = vmw_stdu_dmabuf_fifo_commit;
842 ddirty.base.clip = vmw_stdu_dmabuf_clip;
843 ddirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_dma) +
844 num_clips * sizeof(SVGA3dCopyBox) +
845 sizeof(SVGA3dCmdSurfaceDMASuffix);
846 if (to_surface)
847 ddirty.base.fifo_reserve_size += sizeof(struct vmw_stdu_update);
848
849 ret = vmw_kms_helper_dirty(dev_priv, vfb, clips, vclips,
850 0, 0, num_clips, increment, &ddirty.base);
851 vmw_kms_helper_buffer_finish(dev_priv, file_priv, buf, NULL,
852 user_fence_rep);
853
854 return ret;
855}
856
857
858
859
860
861
862
863
864
865static void vmw_kms_stdu_surface_clip(struct vmw_kms_dirty *dirty)
866{
867 struct vmw_stdu_dirty *sdirty =
868 container_of(dirty, struct vmw_stdu_dirty, base);
869 struct vmw_stdu_surface_copy *cmd = dirty->cmd;
870 struct vmw_screen_target_display_unit *stdu =
871 container_of(dirty->unit, typeof(*stdu), base);
872
873 if (sdirty->sid != stdu->display_srf->res.id) {
874 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
875
876 blit += dirty->num_hits;
877 blit->srcx = dirty->fb_x;
878 blit->srcy = dirty->fb_y;
879 blit->x = dirty->unit_x1;
880 blit->y = dirty->unit_y1;
881 blit->d = 1;
882 blit->w = dirty->unit_x2 - dirty->unit_x1;
883 blit->h = dirty->unit_y2 - dirty->unit_y1;
884 }
885
886 dirty->num_hits++;
887
888
889 sdirty->left = min_t(s32, sdirty->left, dirty->unit_x1);
890 sdirty->top = min_t(s32, sdirty->top, dirty->unit_y1);
891 sdirty->right = max_t(s32, sdirty->right, dirty->unit_x2);
892 sdirty->bottom = max_t(s32, sdirty->bottom, dirty->unit_y2);
893}
894
895
896
897
898
899
900
901
902
903
904static void vmw_kms_stdu_surface_fifo_commit(struct vmw_kms_dirty *dirty)
905{
906 struct vmw_stdu_dirty *sdirty =
907 container_of(dirty, struct vmw_stdu_dirty, base);
908 struct vmw_screen_target_display_unit *stdu =
909 container_of(dirty->unit, typeof(*stdu), base);
910 struct vmw_stdu_surface_copy *cmd = dirty->cmd;
911 struct vmw_stdu_update *update;
912 size_t blit_size = sizeof(SVGA3dCopyBox) * dirty->num_hits;
913 size_t commit_size;
914
915 if (!dirty->num_hits) {
916 vmw_fifo_commit(dirty->dev_priv, 0);
917 return;
918 }
919
920 if (sdirty->sid != stdu->display_srf->res.id) {
921 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
922
923 cmd->header.id = SVGA_3D_CMD_SURFACE_COPY;
924 cmd->header.size = sizeof(cmd->body) + blit_size;
925 cmd->body.src.sid = sdirty->sid;
926 cmd->body.dest.sid = stdu->display_srf->res.id;
927 update = (struct vmw_stdu_update *) &blit[dirty->num_hits];
928 commit_size = sizeof(*cmd) + blit_size + sizeof(*update);
929 } else {
930 update = dirty->cmd;
931 commit_size = sizeof(*update);
932 }
933
934 vmw_stdu_populate_update(update, stdu->base.unit, sdirty->left,
935 sdirty->right, sdirty->top, sdirty->bottom);
936
937 vmw_fifo_commit(dirty->dev_priv, commit_size);
938
939 sdirty->left = sdirty->top = S32_MAX;
940 sdirty->right = sdirty->bottom = S32_MIN;
941}
942
943
944
945
946
947
948
949
950
951
952
953
954
955
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957
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959
960
961
962
963
964int vmw_kms_stdu_surface_dirty(struct vmw_private *dev_priv,
965 struct vmw_framebuffer *framebuffer,
966 struct drm_clip_rect *clips,
967 struct drm_vmw_rect *vclips,
968 struct vmw_resource *srf,
969 s32 dest_x,
970 s32 dest_y,
971 unsigned num_clips, int inc,
972 struct vmw_fence_obj **out_fence)
973{
974 struct vmw_framebuffer_surface *vfbs =
975 container_of(framebuffer, typeof(*vfbs), base);
976 struct vmw_stdu_dirty sdirty;
977 int ret;
978
979 if (!srf)
980 srf = &vfbs->surface->res;
981
982 ret = vmw_kms_helper_resource_prepare(srf, true);
983 if (ret)
984 return ret;
985
986 if (vfbs->is_dmabuf_proxy) {
987 ret = vmw_kms_update_proxy(srf, clips, num_clips, inc);
988 if (ret)
989 goto out_finish;
990 }
991
992 sdirty.base.fifo_commit = vmw_kms_stdu_surface_fifo_commit;
993 sdirty.base.clip = vmw_kms_stdu_surface_clip;
994 sdirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_surface_copy) +
995 sizeof(SVGA3dCopyBox) * num_clips +
996 sizeof(struct vmw_stdu_update);
997 sdirty.sid = srf->id;
998 sdirty.left = sdirty.top = S32_MAX;
999 sdirty.right = sdirty.bottom = S32_MIN;
1000
1001 ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,
1002 dest_x, dest_y, num_clips, inc,
1003 &sdirty.base);
1004out_finish:
1005 vmw_kms_helper_resource_finish(srf, out_fence);
1006
1007 return ret;
1008}
1009
1010
1011
1012
1013
1014static const struct drm_crtc_funcs vmw_stdu_crtc_funcs = {
1015 .cursor_set2 = vmw_du_crtc_cursor_set2,
1016 .cursor_move = vmw_du_crtc_cursor_move,
1017 .gamma_set = vmw_du_crtc_gamma_set,
1018 .destroy = vmw_stdu_crtc_destroy,
1019 .set_config = vmw_stdu_crtc_set_config,
1020 .page_flip = vmw_stdu_crtc_page_flip,
1021};
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039static void vmw_stdu_encoder_destroy(struct drm_encoder *encoder)
1040{
1041 vmw_stdu_destroy(vmw_encoder_to_stdu(encoder));
1042}
1043
1044static const struct drm_encoder_funcs vmw_stdu_encoder_funcs = {
1045 .destroy = vmw_stdu_encoder_destroy,
1046};
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064static void vmw_stdu_connector_destroy(struct drm_connector *connector)
1065{
1066 vmw_stdu_destroy(vmw_connector_to_stdu(connector));
1067}
1068
1069
1070
1071static const struct drm_connector_funcs vmw_stdu_connector_funcs = {
1072 .dpms = vmw_du_connector_dpms,
1073 .detect = vmw_du_connector_detect,
1074 .fill_modes = vmw_du_connector_fill_modes,
1075 .set_property = vmw_du_connector_set_property,
1076 .destroy = vmw_stdu_connector_destroy,
1077};
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091static int vmw_stdu_init(struct vmw_private *dev_priv, unsigned unit)
1092{
1093 struct vmw_screen_target_display_unit *stdu;
1094 struct drm_device *dev = dev_priv->dev;
1095 struct drm_connector *connector;
1096 struct drm_encoder *encoder;
1097 struct drm_crtc *crtc;
1098
1099
1100 stdu = kzalloc(sizeof(*stdu), GFP_KERNEL);
1101 if (!stdu)
1102 return -ENOMEM;
1103
1104 stdu->base.unit = unit;
1105 crtc = &stdu->base.crtc;
1106 encoder = &stdu->base.encoder;
1107 connector = &stdu->base.connector;
1108
1109 stdu->base.pref_active = (unit == 0);
1110 stdu->base.pref_width = dev_priv->initial_width;
1111 stdu->base.pref_height = dev_priv->initial_height;
1112 stdu->base.is_implicit = false;
1113
1114 drm_connector_init(dev, connector, &vmw_stdu_connector_funcs,
1115 DRM_MODE_CONNECTOR_VIRTUAL);
1116 connector->status = vmw_du_connector_detect(connector, false);
1117
1118 drm_encoder_init(dev, encoder, &vmw_stdu_encoder_funcs,
1119 DRM_MODE_ENCODER_VIRTUAL, NULL);
1120 drm_mode_connector_attach_encoder(connector, encoder);
1121 encoder->possible_crtcs = (1 << unit);
1122 encoder->possible_clones = 0;
1123
1124 (void) drm_connector_register(connector);
1125
1126 drm_crtc_init(dev, crtc, &vmw_stdu_crtc_funcs);
1127
1128 drm_mode_crtc_set_gamma_size(crtc, 256);
1129
1130 drm_object_attach_property(&connector->base,
1131 dev->mode_config.dirty_info_property,
1132 1);
1133 drm_object_attach_property(&connector->base,
1134 dev_priv->hotplug_mode_update_property, 1);
1135 drm_object_attach_property(&connector->base,
1136 dev->mode_config.suggested_x_property, 0);
1137 drm_object_attach_property(&connector->base,
1138 dev->mode_config.suggested_y_property, 0);
1139 if (dev_priv->implicit_placement_property)
1140 drm_object_attach_property
1141 (&connector->base,
1142 dev_priv->implicit_placement_property,
1143 stdu->base.is_implicit);
1144 return 0;
1145}
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu)
1157{
1158 vmw_stdu_unpin_display(stdu);
1159
1160 vmw_du_cleanup(&stdu->base);
1161 kfree(stdu);
1162}
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185int vmw_kms_stdu_init_display(struct vmw_private *dev_priv)
1186{
1187 struct drm_device *dev = dev_priv->dev;
1188 int i, ret;
1189
1190
1191
1192 if (!VMWGFX_ENABLE_SCREEN_TARGET_OTABLE)
1193 return -ENOSYS;
1194
1195 if (!(dev_priv->capabilities & SVGA_CAP_GBOBJECTS))
1196 return -ENOSYS;
1197
1198 ret = drm_vblank_init(dev, VMWGFX_NUM_DISPLAY_UNITS);
1199 if (unlikely(ret != 0))
1200 return ret;
1201
1202 ret = drm_mode_create_dirty_info_property(dev);
1203 if (unlikely(ret != 0))
1204 goto err_vblank_cleanup;
1205
1206 dev_priv->active_display_unit = vmw_du_screen_target;
1207
1208 vmw_kms_create_implicit_placement_property(dev_priv, false);
1209
1210 for (i = 0; i < VMWGFX_NUM_DISPLAY_UNITS; ++i) {
1211 ret = vmw_stdu_init(dev_priv, i);
1212
1213 if (unlikely(ret != 0)) {
1214 DRM_ERROR("Failed to initialize STDU %d", i);
1215 goto err_vblank_cleanup;
1216 }
1217 }
1218
1219 DRM_INFO("Screen Target Display device initialized\n");
1220
1221 return 0;
1222
1223err_vblank_cleanup:
1224 drm_vblank_cleanup(dev);
1225 return ret;
1226}
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240int vmw_kms_stdu_close_display(struct vmw_private *dev_priv)
1241{
1242 struct drm_device *dev = dev_priv->dev;
1243
1244 drm_vblank_cleanup(dev);
1245
1246 return 0;
1247}
1248